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linux-libre
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drivers
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net
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ethernet
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intel
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e1000e
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regs.h

regs.h 14 KB
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  1. /* Intel PRO/1000 Linux driver
    2. 

  2.  * Copyright(c) 1999 - 2015 Intel Corporation.
    3. 

  3.  *
    4. 

  4.  * This program is free software; you can redistribute it and/or modify it
    5. 

  5.  * under the terms and conditions of the GNU General Public License,
    6. 

  6.  * version 2, as published by the Free Software Foundation.
    7. 

  7.  *
    8. 

  8.  * This program is distributed in the hope it will be useful, but WITHOUT
    9. 

  9.  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    10. 

  10.  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
    11. 

  11.  * more details.
    12. 

  12.  *
    13. 

  13.  * The full GNU General Public License is included in this distribution in
    14. 

  14.  * the file called "COPYING".
    15. 

  15.  *
    16. 

  16.  * Contact Information:
    17. 

  17.  * Linux NICS <linux.nics@intel.com>
    18. 

  18.  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
    19. 

  19.  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
    20. 

  20.  */
    21. 

  21. 

  22. #ifndef _E1000E_REGS_H_
    23. 

  23. #define _E1000E_REGS_H_
    24. 

  24. 

  25. #define E1000_CTRL	0x00000	/* Device Control - RW */
    26. 

  26. #define E1000_STATUS	0x00008	/* Device Status - RO */
    27. 

  27. #define E1000_EECD	0x00010	/* EEPROM/Flash Control - RW */
    28. 

  28. #define E1000_EERD	0x00014	/* EEPROM Read - RW */
    29. 

  29. #define E1000_CTRL_EXT	0x00018	/* Extended Device Control - RW */
    30. 

  30. #define E1000_FLA	0x0001C	/* Flash Access - RW */
    31. 

  31. #define E1000_MDIC	0x00020	/* MDI Control - RW */
    32. 

  32. #define E1000_SCTL	0x00024	/* SerDes Control - RW */
    33. 

  33. #define E1000_FCAL	0x00028	/* Flow Control Address Low - RW */
    34. 

  34. #define E1000_FCAH	0x0002C	/* Flow Control Address High -RW */
    35. 

  35. #define E1000_FEXT	0x0002C	/* Future Extended - RW */
    36. 

  36. #define E1000_FEXTNVM	0x00028	/* Future Extended NVM - RW */
    37. 

  37. #define E1000_FEXTNVM3	0x0003C	/* Future Extended NVM 3 - RW */
    38. 

  38. #define E1000_FEXTNVM4	0x00024	/* Future Extended NVM 4 - RW */
    39. 

  39. #define E1000_FEXTNVM6	0x00010	/* Future Extended NVM 6 - RW */
    40. 

  40. #define E1000_FEXTNVM7	0x000E4	/* Future Extended NVM 7 - RW */
    41. 

  41. #define E1000_FEXTNVM9	0x5BB4	/* Future Extended NVM 9 - RW */
    42. 

  42. #define E1000_FEXTNVM11	0x5BBC	/* Future Extended NVM 11 - RW */
    43. 

  43. #define E1000_PCIEANACFG	0x00F18	/* PCIE Analog Config */
    44. 

  44. #define E1000_FCT	0x00030	/* Flow Control Type - RW */
    45. 

  45. #define E1000_VET	0x00038	/* VLAN Ether Type - RW */
    46. 

  46. #define E1000_ICR	0x000C0	/* Interrupt Cause Read - R/clr */
    47. 

  47. #define E1000_ITR	0x000C4	/* Interrupt Throttling Rate - RW */
    48. 

  48. #define E1000_ICS	0x000C8	/* Interrupt Cause Set - WO */
    49. 

  49. #define E1000_IMS	0x000D0	/* Interrupt Mask Set - RW */
    50. 

  50. #define E1000_IMC	0x000D8	/* Interrupt Mask Clear - WO */
    51. 

  51. #define E1000_IAM	0x000E0	/* Interrupt Acknowledge Auto Mask */
    52. 

  52. #define E1000_IVAR	0x000E4	/* Interrupt Vector Allocation Register - RW */
    53. 

  53. #define E1000_SVCR	0x000F0
    54. 

  54. #define E1000_SVT	0x000F4
    55. 

  55. #define E1000_LPIC	0x000FC	/* Low Power IDLE control */
    56. 

  56. #define E1000_RCTL	0x00100	/* Rx Control - RW */
    57. 

  57. #define E1000_FCTTV	0x00170	/* Flow Control Transmit Timer Value - RW */
    58. 

  58. #define E1000_TXCW	0x00178	/* Tx Configuration Word - RW */
    59. 

  59. #define E1000_RXCW	0x00180	/* Rx Configuration Word - RO */
    60. 

  60. #define E1000_PBA_ECC	0x01100	/* PBA ECC Register */
    61. 

  61. #define E1000_TCTL	0x00400	/* Tx Control - RW */
    62. 

  62. #define E1000_TCTL_EXT	0x00404	/* Extended Tx Control - RW */
    63. 

  63. #define E1000_TIPG	0x00410	/* Tx Inter-packet gap -RW */
    64. 

  64. #define E1000_AIT	0x00458	/* Adaptive Interframe Spacing Throttle - RW */
    65. 

  65. #define E1000_LEDCTL	0x00E00	/* LED Control - RW */
    66. 

  66. #define E1000_EXTCNF_CTRL	0x00F00	/* Extended Configuration Control */
    67. 

  67. #define E1000_EXTCNF_SIZE	0x00F08	/* Extended Configuration Size */
    68. 

  68. #define E1000_PHY_CTRL	0x00F10	/* PHY Control Register in CSR */
    69. 

  69. #define E1000_POEMB	E1000_PHY_CTRL	/* PHY OEM Bits */
    70. 

  70. #define E1000_PBA	0x01000	/* Packet Buffer Allocation - RW */
    71. 

  71. #define E1000_PBS	0x01008	/* Packet Buffer Size */
    72. 

  72. #define E1000_PBECCSTS	0x0100C	/* Packet Buffer ECC Status - RW */
    73. 

  73. #define E1000_IOSFPC	0x00F28	/* TX corrupted data  */
    74. 

  74. #define E1000_EEMNGCTL	0x01010	/* MNG EEprom Control */
    75. 

  75. #define E1000_EEWR	0x0102C	/* EEPROM Write Register - RW */
    76. 

  76. #define E1000_FLOP	0x0103C	/* FLASH Opcode Register */
    77. 

  77. #define E1000_ERT	0x02008	/* Early Rx Threshold - RW */
    78. 

  78. #define E1000_FCRTL	0x02160	/* Flow Control Receive Threshold Low - RW */
    79. 

  79. #define E1000_FCRTH	0x02168	/* Flow Control Receive Threshold High - RW */
    80. 

  80. #define E1000_PSRCTL	0x02170	/* Packet Split Receive Control - RW */
    81. 

  81. #define E1000_RDFH	0x02410	/* Rx Data FIFO Head - RW */
    82. 

  82. #define E1000_RDFT	0x02418	/* Rx Data FIFO Tail - RW */
    83. 

  83. #define E1000_RDFHS	0x02420	/* Rx Data FIFO Head Saved - RW */
    84. 

  84. #define E1000_RDFTS	0x02428	/* Rx Data FIFO Tail Saved - RW */
    85. 

  85. #define E1000_RDFPC	0x02430	/* Rx Data FIFO Packet Count - RW */
    86. 

  86. /* Split and Replication Rx Control - RW */
    87. 

  87. #define E1000_RDTR	0x02820	/* Rx Delay Timer - RW */
    88. 

  88. #define E1000_RADV	0x0282C	/* Rx Interrupt Absolute Delay Timer - RW */
    89. 

  89. /* Convenience macros
    90. 

  90.  *
    91. 

  91.  * Note: "_n" is the queue number of the register to be written to.
    92. 

  92.  *
    93. 

  93.  * Example usage:
    94. 

  94.  * E1000_RDBAL_REG(current_rx_queue)
    95. 

  95.  */
    96. 

  96. #define E1000_RDBAL(_n)	((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
    97. 

  97. 			 (0x0C000 + ((_n) * 0x40)))
    98. 

  98. #define E1000_RDBAH(_n)	((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
    99. 

  99. 			 (0x0C004 + ((_n) * 0x40)))
    100. 

  100. #define E1000_RDLEN(_n)	((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
    101. 

  101. 			 (0x0C008 + ((_n) * 0x40)))
    102. 

  102. #define E1000_RDH(_n)	((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
    103. 

  103. 			 (0x0C010 + ((_n) * 0x40)))
    104. 

  104. #define E1000_RDT(_n)	((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
    105. 

  105. 			 (0x0C018 + ((_n) * 0x40)))
    106. 

  106. #define E1000_RXDCTL(_n)	((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
    107. 

  107. 				 (0x0C028 + ((_n) * 0x40)))
    108. 

  108. #define E1000_TDBAL(_n)	((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
    109. 

  109. 			 (0x0E000 + ((_n) * 0x40)))
    110. 

  110. #define E1000_TDBAH(_n)	((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
    111. 

  111. 			 (0x0E004 + ((_n) * 0x40)))
    112. 

  112. #define E1000_TDLEN(_n)	((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
    113. 

  113. 			 (0x0E008 + ((_n) * 0x40)))
    114. 

  114. #define E1000_TDH(_n)	((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \
    115. 

  115. 			 (0x0E010 + ((_n) * 0x40)))
    116. 

  116. #define E1000_TDT(_n)	((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \
    117. 

  117. 			 (0x0E018 + ((_n) * 0x40)))
    118. 

  118. #define E1000_TXDCTL(_n)	((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \
    119. 

  119. 				 (0x0E028 + ((_n) * 0x40)))
    120. 

  120. #define E1000_TARC(_n)		(0x03840 + ((_n) * 0x100))
    121. 

  121. #define E1000_KABGTXD		0x03004	/* AFE Band Gap Transmit Ref Data */
    122. 

  122. #define E1000_RAL(_i)		(((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
    123. 

  123. 				 (0x054E0 + ((_i - 16) * 8)))
    124. 

  124. #define E1000_RAH(_i)		(((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
    125. 

  125. 				 (0x054E4 + ((_i - 16) * 8)))
    126. 

  126. #define E1000_SHRAL(_i)		(0x05438 + ((_i) * 8))
    127. 

  127. #define E1000_SHRAH(_i)		(0x0543C + ((_i) * 8))
    128. 

  128. #define E1000_TDFH		0x03410	/* Tx Data FIFO Head - RW */
    129. 

  129. #define E1000_TDFT		0x03418	/* Tx Data FIFO Tail - RW */
    130. 

  130. #define E1000_TDFHS		0x03420	/* Tx Data FIFO Head Saved - RW */
    131. 

  131. #define E1000_TDFTS		0x03428	/* Tx Data FIFO Tail Saved - RW */
    132. 

  132. #define E1000_TDFPC		0x03430	/* Tx Data FIFO Packet Count - RW */
    133. 

  133. #define E1000_TIDV	0x03820	/* Tx Interrupt Delay Value - RW */
    134. 

  134. #define E1000_TADV	0x0382C	/* Tx Interrupt Absolute Delay Val - RW */
    135. 

  135. #define E1000_CRCERRS	0x04000	/* CRC Error Count - R/clr */
    136. 

  136. #define E1000_ALGNERRC	0x04004	/* Alignment Error Count - R/clr */
    137. 

  137. #define E1000_SYMERRS	0x04008	/* Symbol Error Count - R/clr */
    138. 

  138. #define E1000_RXERRC	0x0400C	/* Receive Error Count - R/clr */
    139. 

  139. #define E1000_MPC	0x04010	/* Missed Packet Count - R/clr */
    140. 

  140. #define E1000_SCC	0x04014	/* Single Collision Count - R/clr */
    141. 

  141. #define E1000_ECOL	0x04018	/* Excessive Collision Count - R/clr */
    142. 

  142. #define E1000_MCC	0x0401C	/* Multiple Collision Count - R/clr */
    143. 

  143. #define E1000_LATECOL	0x04020	/* Late Collision Count - R/clr */
    144. 

  144. #define E1000_COLC	0x04028	/* Collision Count - R/clr */
    145. 

  145. #define E1000_DC	0x04030	/* Defer Count - R/clr */
    146. 

  146. #define E1000_TNCRS	0x04034	/* Tx-No CRS - R/clr */
    147. 

  147. #define E1000_SEC	0x04038	/* Sequence Error Count - R/clr */
    148. 

  148. #define E1000_CEXTERR	0x0403C	/* Carrier Extension Error Count - R/clr */
    149. 

  149. #define E1000_RLEC	0x04040	/* Receive Length Error Count - R/clr */
    150. 

  150. #define E1000_XONRXC	0x04048	/* XON Rx Count - R/clr */
    151. 

  151. #define E1000_XONTXC	0x0404C	/* XON Tx Count - R/clr */
    152. 

  152. #define E1000_XOFFRXC	0x04050	/* XOFF Rx Count - R/clr */
    153. 

  153. #define E1000_XOFFTXC	0x04054	/* XOFF Tx Count - R/clr */
    154. 

  154. #define E1000_FCRUC	0x04058	/* Flow Control Rx Unsupported Count- R/clr */
    155. 

  155. #define E1000_PRC64	0x0405C	/* Packets Rx (64 bytes) - R/clr */
    156. 

  156. #define E1000_PRC127	0x04060	/* Packets Rx (65-127 bytes) - R/clr */
    157. 

  157. #define E1000_PRC255	0x04064	/* Packets Rx (128-255 bytes) - R/clr */
    158. 

  158. #define E1000_PRC511	0x04068	/* Packets Rx (255-511 bytes) - R/clr */
    159. 

  159. #define E1000_PRC1023	0x0406C	/* Packets Rx (512-1023 bytes) - R/clr */
    160. 

  160. #define E1000_PRC1522	0x04070	/* Packets Rx (1024-1522 bytes) - R/clr */
    161. 

  161. #define E1000_GPRC	0x04074	/* Good Packets Rx Count - R/clr */
    162. 

  162. #define E1000_BPRC	0x04078	/* Broadcast Packets Rx Count - R/clr */
    163. 

  163. #define E1000_MPRC	0x0407C	/* Multicast Packets Rx Count - R/clr */
    164. 

  164. #define E1000_GPTC	0x04080	/* Good Packets Tx Count - R/clr */
    165. 

  165. #define E1000_GORCL	0x04088	/* Good Octets Rx Count Low - R/clr */
    166. 

  166. #define E1000_GORCH	0x0408C	/* Good Octets Rx Count High - R/clr */
    167. 

  167. #define E1000_GOTCL	0x04090	/* Good Octets Tx Count Low - R/clr */
    168. 

  168. #define E1000_GOTCH	0x04094	/* Good Octets Tx Count High - R/clr */
    169. 

  169. #define E1000_RNBC	0x040A0	/* Rx No Buffers Count - R/clr */
    170. 

  170. #define E1000_RUC	0x040A4	/* Rx Undersize Count - R/clr */
    171. 

  171. #define E1000_RFC	0x040A8	/* Rx Fragment Count - R/clr */
    172. 

  172. #define E1000_ROC	0x040AC	/* Rx Oversize Count - R/clr */
    173. 

  173. #define E1000_RJC	0x040B0	/* Rx Jabber Count - R/clr */
    174. 

  174. #define E1000_MGTPRC	0x040B4	/* Management Packets Rx Count - R/clr */
    175. 

  175. #define E1000_MGTPDC	0x040B8	/* Management Packets Dropped Count - R/clr */
    176. 

  176. #define E1000_MGTPTC	0x040BC	/* Management Packets Tx Count - R/clr */
    177. 

  177. #define E1000_TORL	0x040C0	/* Total Octets Rx Low - R/clr */
    178. 

  178. #define E1000_TORH	0x040C4	/* Total Octets Rx High - R/clr */
    179. 

  179. #define E1000_TOTL	0x040C8	/* Total Octets Tx Low - R/clr */
    180. 

  180. #define E1000_TOTH	0x040CC	/* Total Octets Tx High - R/clr */
    181. 

  181. #define E1000_TPR	0x040D0	/* Total Packets Rx - R/clr */
    182. 

  182. #define E1000_TPT	0x040D4	/* Total Packets Tx - R/clr */
    183. 

  183. #define E1000_PTC64	0x040D8	/* Packets Tx (64 bytes) - R/clr */
    184. 

  184. #define E1000_PTC127	0x040DC	/* Packets Tx (65-127 bytes) - R/clr */
    185. 

  185. #define E1000_PTC255	0x040E0	/* Packets Tx (128-255 bytes) - R/clr */
    186. 

  186. #define E1000_PTC511	0x040E4	/* Packets Tx (256-511 bytes) - R/clr */
    187. 

  187. #define E1000_PTC1023	0x040E8	/* Packets Tx (512-1023 bytes) - R/clr */
    188. 

  188. #define E1000_PTC1522	0x040EC	/* Packets Tx (1024-1522 Bytes) - R/clr */
    189. 

  189. #define E1000_MPTC	0x040F0	/* Multicast Packets Tx Count - R/clr */
    190. 

  190. #define E1000_BPTC	0x040F4	/* Broadcast Packets Tx Count - R/clr */
    191. 

  191. #define E1000_TSCTC	0x040F8	/* TCP Segmentation Context Tx - R/clr */
    192. 

  192. #define E1000_TSCTFC	0x040FC	/* TCP Segmentation Context Tx Fail - R/clr */
    193. 

  193. #define E1000_IAC	0x04100	/* Interrupt Assertion Count */
    194. 

  194. #define E1000_ICRXPTC	0x04104	/* Interrupt Cause Rx Pkt Timer Expire Count */
    195. 

  195. #define E1000_ICRXATC	0x04108	/* Interrupt Cause Rx Abs Timer Expire Count */
    196. 

  196. #define E1000_ICTXPTC	0x0410C	/* Interrupt Cause Tx Pkt Timer Expire Count */
    197. 

  197. #define E1000_ICTXATC	0x04110	/* Interrupt Cause Tx Abs Timer Expire Count */
    198. 

  198. #define E1000_ICTXQEC	0x04118	/* Interrupt Cause Tx Queue Empty Count */
    199. 

  199. #define E1000_ICTXQMTC	0x0411C	/* Interrupt Cause Tx Queue Min Thresh Count */
    200. 

  200. #define E1000_ICRXDMTC	0x04120	/* Interrupt Cause Rx Desc Min Thresh Count */
    201. 

  201. #define E1000_ICRXOC	0x04124	/* Interrupt Cause Receiver Overrun Count */
    202. 

  202. #define E1000_CRC_OFFSET	0x05F50	/* CRC Offset register */
    203. 

  203. 

  204. #define E1000_PCS_LCTL	0x04208	/* PCS Link Control - RW */
    205. 

  205. #define E1000_PCS_LSTAT	0x0420C	/* PCS Link Status - RO */
    206. 

  206. #define E1000_PCS_ANADV	0x04218	/* AN advertisement - RW */
    207. 

  207. #define E1000_PCS_LPAB	0x0421C	/* Link Partner Ability - RW */
    208. 

  208. #define E1000_RXCSUM	0x05000	/* Rx Checksum Control - RW */
    209. 

  209. #define E1000_RFCTL	0x05008	/* Receive Filter Control */
    210. 

  210. #define E1000_MTA	0x05200	/* Multicast Table Array - RW Array */
    211. 

  211. #define E1000_RA	0x05400	/* Receive Address - RW Array */
    212. 

  212. #define E1000_VFTA	0x05600	/* VLAN Filter Table Array - RW Array */
    213. 

  213. #define E1000_WUC	0x05800	/* Wakeup Control - RW */
    214. 

  214. #define E1000_WUFC	0x05808	/* Wakeup Filter Control - RW */
    215. 

  215. #define E1000_WUS	0x05810	/* Wakeup Status - RO */
    216. 

  216. #define E1000_MANC	0x05820	/* Management Control - RW */
    217. 

  217. #define E1000_FFLT	0x05F00	/* Flexible Filter Length Table - RW Array */
    218. 

  218. #define E1000_HOST_IF	0x08800	/* Host Interface */
    219. 

  219. 

  220. #define E1000_KMRNCTRLSTA	0x00034	/* MAC-PHY interface - RW */
    221. 

  221. #define E1000_MANC2H		0x05860	/* Management Control To Host - RW */
    222. 

  222. /* Management Decision Filters */
    223. 

  223. #define E1000_MDEF(_n)		(0x05890 + (4 * (_n)))
    224. 

  224. #define E1000_SW_FW_SYNC	0x05B5C	/* SW-FW Synchronization - RW */
    225. 

  225. #define E1000_GCR	0x05B00	/* PCI-Ex Control */
    226. 

  226. #define E1000_GCR2	0x05B64	/* PCI-Ex Control #2 */
    227. 

  227. #define E1000_FACTPS	0x05B30	/* Function Active and Power State to MNG */
    228. 

  228. #define E1000_SWSM	0x05B50	/* SW Semaphore */
    229. 

  229. #define E1000_FWSM	0x05B54	/* FW Semaphore */
    230. 

  230. /* Driver-only SW semaphore (not used by BOOT agents) */
    231. 

  231. #define E1000_SWSM2	0x05B58
    232. 

  232. #define E1000_FFLT_DBG	0x05F04	/* Debug Register */
    233. 

  233. #define E1000_HICR	0x08F00	/* Host Interface Control */
    234. 

  234. 

  235. /* RSS registers */
    236. 

  236. #define E1000_MRQC	0x05818	/* Multiple Receive Control - RW */
    237. 

  237. #define E1000_RETA(_i)	(0x05C00 + ((_i) * 4))	/* Redirection Table - RW */
    238. 

  238. #define E1000_RSSRK(_i)	(0x05C80 + ((_i) * 4))	/* RSS Random Key - RW */
    239. 

  239. #define E1000_TSYNCRXCTL	0x0B620	/* Rx Time Sync Control register - RW */
    240. 

  240. #define E1000_TSYNCTXCTL	0x0B614	/* Tx Time Sync Control register - RW */
    241. 

  241. #define E1000_RXSTMPL	0x0B624	/* Rx timestamp Low - RO */
    242. 

  242. #define E1000_RXSTMPH	0x0B628	/* Rx timestamp High - RO */
    243. 

  243. #define E1000_TXSTMPL	0x0B618	/* Tx timestamp value Low - RO */
    244. 

  244. #define E1000_TXSTMPH	0x0B61C	/* Tx timestamp value High - RO */
    245. 

  245. #define E1000_SYSTIML	0x0B600	/* System time register Low - RO */
    246. 

  246. #define E1000_SYSTIMH	0x0B604	/* System time register High - RO */
    247. 

  247. #define E1000_TIMINCA	0x0B608	/* Increment attributes register - RW */
    248. 

  248. #define E1000_SYSSTMPL  0x0B648 /* HH Timesync system stamp low register */
    249. 

  249. #define E1000_SYSSTMPH  0x0B64C /* HH Timesync system stamp hi register */
    250. 

  250. #define E1000_PLTSTMPL  0x0B640 /* HH Timesync platform stamp low register */
    251. 

  251. #define E1000_PLTSTMPH  0x0B644 /* HH Timesync platform stamp hi register */
    252. 

  252. #define E1000_RXMTRL	0x0B634	/* Time sync Rx EtherType and Msg Type - RW */
    253. 

  253. #define E1000_RXUDP	0x0B638	/* Time Sync Rx UDP Port - RW */
    254. 

  254. 

  255. #endif
    256. 

  256.