t104xsi-pre.dtsi 3.2 KB

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  1. /*
  2. * T1040/T1042 Silicon/SoC Device Tree Source (pre include)
  3. *
  4. * Copyright 2013-2014 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. /dts-v1/;
  35. /include/ "e5500_power_isa.dtsi"
  36. / {
  37. #address-cells = <2>;
  38. #size-cells = <2>;
  39. interrupt-parent = <&mpic>;
  40. aliases {
  41. ccsr = &soc;
  42. dcsr = &dcsr;
  43. serial0 = &serial0;
  44. serial1 = &serial1;
  45. serial2 = &serial2;
  46. serial3 = &serial3;
  47. pci0 = &pci0;
  48. pci1 = &pci1;
  49. pci2 = &pci2;
  50. pci3 = &pci3;
  51. usb0 = &usb0;
  52. usb1 = &usb1;
  53. sdhc = &sdhc;
  54. crypto = &crypto;
  55. fman0 = &fman0;
  56. ethernet0 = &enet0;
  57. ethernet1 = &enet1;
  58. ethernet2 = &enet2;
  59. ethernet3 = &enet3;
  60. ethernet4 = &enet4;
  61. };
  62. cpus {
  63. #address-cells = <1>;
  64. #size-cells = <0>;
  65. cpu0: PowerPC,e5500@0 {
  66. device_type = "cpu";
  67. reg = <0>;
  68. clocks = <&mux0>;
  69. next-level-cache = <&L2_1>;
  70. #cooling-cells = <2>;
  71. L2_1: l2-cache {
  72. next-level-cache = <&cpc>;
  73. };
  74. };
  75. cpu1: PowerPC,e5500@1 {
  76. device_type = "cpu";
  77. reg = <1>;
  78. clocks = <&mux1>;
  79. next-level-cache = <&L2_2>;
  80. #cooling-cells = <2>;
  81. L2_2: l2-cache {
  82. next-level-cache = <&cpc>;
  83. };
  84. };
  85. cpu2: PowerPC,e5500@2 {
  86. device_type = "cpu";
  87. reg = <2>;
  88. clocks = <&mux2>;
  89. next-level-cache = <&L2_3>;
  90. #cooling-cells = <2>;
  91. L2_3: l2-cache {
  92. next-level-cache = <&cpc>;
  93. };
  94. };
  95. cpu3: PowerPC,e5500@3 {
  96. device_type = "cpu";
  97. reg = <3>;
  98. clocks = <&mux3>;
  99. next-level-cache = <&L2_4>;
  100. #cooling-cells = <2>;
  101. L2_4: l2-cache {
  102. next-level-cache = <&cpc>;
  103. };
  104. };
  105. };
  106. };