ppa8548.dts 2.8 KB

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  1. /*
  2. * PPA8548 Device Tree Source (36-bit address map)
  3. * Copyright 2013 Prodrive B.V.
  4. *
  5. * Based on:
  6. * MPC8548 CDS Device Tree Source (36-bit address map)
  7. * Copyright 2012 Freescale Semiconductor Inc.
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. */
  14. /include/ "mpc8548si-pre.dtsi"
  15. / {
  16. model = "ppa8548";
  17. compatible = "ppa8548";
  18. #address-cells = <2>;
  19. #size-cells = <2>;
  20. interrupt-parent = <&mpic>;
  21. memory {
  22. device_type = "memory";
  23. reg = <0 0 0x0 0x40000000>;
  24. };
  25. lbc: localbus@fe0005000 {
  26. reg = <0xf 0xe0005000 0 0x1000>;
  27. ranges = <0x0 0x0 0xf 0xff800000 0x00800000>;
  28. };
  29. soc: soc8548@fe0000000 {
  30. ranges = <0 0xf 0xe0000000 0x100000>;
  31. };
  32. pci0: pci@fe0008000 {
  33. /* ppa8548 board doesn't support PCI */
  34. status = "disabled";
  35. };
  36. pci1: pci@fe0009000 {
  37. /* ppa8548 board doesn't support PCI */
  38. status = "disabled";
  39. };
  40. pci2: pcie@fe000a000 {
  41. /* ppa8548 board doesn't support PCI */
  42. status = "disabled";
  43. };
  44. rio: rapidio@fe00c0000 {
  45. reg = <0xf 0xe00c0000 0x0 0x11000>;
  46. port1 {
  47. ranges = <0x0 0x0 0x0 0x80000000 0x0 0x40000000>;
  48. };
  49. };
  50. };
  51. &lbc {
  52. nor@0 {
  53. #address-cells = <1>;
  54. #size-cells = <1>;
  55. compatible = "cfi-flash";
  56. reg = <0x0 0x0 0x00800000>;
  57. bank-width = <2>;
  58. device-width = <2>;
  59. partition@0 {
  60. reg = <0x0 0x7A0000>;
  61. label = "user";
  62. };
  63. partition@7A0000 {
  64. reg = <0x7A0000 0x20000>;
  65. label = "env";
  66. read-only;
  67. };
  68. partition@7C0000 {
  69. reg = <0x7C0000 0x40000>;
  70. label = "u-boot";
  71. read-only;
  72. };
  73. };
  74. };
  75. &soc {
  76. i2c@3000 {
  77. rtc@6f {
  78. compatible = "intersil,isl1208";
  79. reg = <0x6f>;
  80. };
  81. };
  82. i2c@3100 {
  83. };
  84. /*
  85. * Only ethernet controller @25000 and @26000 are used.
  86. * Use alias enet2 and enet3 for the remainig controllers,
  87. * to stay compatible with mpc8548si-pre.dtsi.
  88. */
  89. enet2: ethernet@24000 {
  90. status = "disabled";
  91. };
  92. mdio@24520 {
  93. phy0: ethernet-phy@0 {
  94. interrupts = <7 1 0 0>;
  95. reg = <0x0>;
  96. };
  97. phy1: ethernet-phy@1 {
  98. interrupts = <8 1 0 0>;
  99. reg = <0x1>;
  100. };
  101. tbi0: tbi-phy@11 {
  102. reg = <0x11>;
  103. device_type = "tbi-phy";
  104. };
  105. };
  106. enet0: ethernet@25000 {
  107. tbi-handle = <&tbi1>;
  108. phy-handle = <&phy0>;
  109. };
  110. mdio@25520 {
  111. tbi1: tbi-phy@11 {
  112. reg = <0x11>;
  113. device_type = "tbi-phy";
  114. };
  115. };
  116. enet1: ethernet@26000 {
  117. tbi-handle = <&tbi2>;
  118. phy-handle = <&phy1>;
  119. };
  120. mdio@26520 {
  121. tbi2: tbi-phy@11 {
  122. reg = <0x11>;
  123. device_type = "tbi-phy";
  124. };
  125. };
  126. enet3: ethernet@27000 {
  127. status = "disabled";
  128. };
  129. mdio@27520 {
  130. tbi3: tbi-phy@11 {
  131. reg = <0x11>;
  132. device_type = "tbi-phy";
  133. };
  134. };
  135. crypto@30000 {
  136. status = "disabled";
  137. };
  138. };
  139. /include/ "mpc8548si-post.dtsi"