p1022si-post.dtsi 6.2 KB

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  1. /*
  2. * P1022/P1013 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2011 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &lbc {
  35. #address-cells = <2>;
  36. #size-cells = <1>;
  37. /*
  38. * The localbus on the P1022 is not a simple-bus because of the eLBC
  39. * pin muxing when the DIU is enabled.
  40. */
  41. compatible = "fsl,p1022-elbc", "fsl,elbc";
  42. interrupts = <19 2 0 0>,
  43. <16 2 0 0>;
  44. };
  45. /* controller at 0x9000 */
  46. &pci0 {
  47. compatible = "fsl,mpc8548-pcie";
  48. device_type = "pci";
  49. #size-cells = <2>;
  50. #address-cells = <3>;
  51. bus-range = <0 255>;
  52. clock-frequency = <33333333>;
  53. interrupts = <16 2 0 0>;
  54. pcie@0 {
  55. reg = <0 0 0 0 0>;
  56. #interrupt-cells = <1>;
  57. #size-cells = <2>;
  58. #address-cells = <3>;
  59. device_type = "pci";
  60. interrupts = <16 2 0 0>;
  61. interrupt-map-mask = <0xf800 0 0 7>;
  62. interrupt-map = <
  63. /* IDSEL 0x0 */
  64. 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
  65. 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
  66. 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
  67. 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
  68. >;
  69. };
  70. };
  71. /* controller at 0xa000 */
  72. &pci1 {
  73. compatible = "fsl,mpc8548-pcie";
  74. device_type = "pci";
  75. #size-cells = <2>;
  76. #address-cells = <3>;
  77. bus-range = <0 255>;
  78. clock-frequency = <33333333>;
  79. interrupts = <16 2 0 0>;
  80. pcie@0 {
  81. reg = <0 0 0 0 0>;
  82. #interrupt-cells = <1>;
  83. #size-cells = <2>;
  84. #address-cells = <3>;
  85. device_type = "pci";
  86. interrupts = <16 2 0 0>;
  87. interrupt-map-mask = <0xf800 0 0 7>;
  88. interrupt-map = <
  89. /* IDSEL 0x0 */
  90. 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
  91. 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
  92. 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
  93. 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
  94. >;
  95. };
  96. };
  97. /* controller at 0xb000 */
  98. &pci2 {
  99. compatible = "fsl,mpc8548-pcie";
  100. device_type = "pci";
  101. #size-cells = <2>;
  102. #address-cells = <3>;
  103. bus-range = <0 255>;
  104. clock-frequency = <33333333>;
  105. interrupts = <16 2 0 0>;
  106. pcie@0 {
  107. reg = <0 0 0 0 0>;
  108. #interrupt-cells = <1>;
  109. #size-cells = <2>;
  110. #address-cells = <3>;
  111. device_type = "pci";
  112. interrupts = <16 2 0 0>;
  113. interrupt-map-mask = <0xf800 0 0 7>;
  114. interrupt-map = <
  115. /* IDSEL 0x0 */
  116. 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
  117. 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
  118. 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
  119. 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
  120. >;
  121. };
  122. };
  123. &soc {
  124. #address-cells = <1>;
  125. #size-cells = <1>;
  126. device_type = "soc";
  127. compatible = "fsl,p1022-immr", "simple-bus";
  128. bus-frequency = <0>; // Filled out by uboot.
  129. ecm-law@0 {
  130. compatible = "fsl,ecm-law";
  131. reg = <0x0 0x1000>;
  132. fsl,num-laws = <12>;
  133. };
  134. ecm@1000 {
  135. compatible = "fsl,p1022-ecm", "fsl,ecm";
  136. reg = <0x1000 0x1000>;
  137. interrupts = <16 2 0 0>;
  138. };
  139. memory-controller@2000 {
  140. compatible = "fsl,p1022-memory-controller";
  141. reg = <0x2000 0x1000>;
  142. interrupts = <16 2 0 0>;
  143. };
  144. /include/ "pq3-i2c-0.dtsi"
  145. /include/ "pq3-i2c-1.dtsi"
  146. /include/ "pq3-duart-0.dtsi"
  147. /include/ "pq3-espi-0.dtsi"
  148. spi@7000 {
  149. fsl,espi-num-chipselects = <4>;
  150. };
  151. /include/ "pq3-dma-1.dtsi"
  152. dma@c300 {
  153. dma00: dma-channel@0 {
  154. compatible = "fsl,ssi-dma-channel";
  155. };
  156. dma01: dma-channel@80 {
  157. compatible = "fsl,ssi-dma-channel";
  158. };
  159. };
  160. /include/ "pq3-gpio-0.dtsi"
  161. display: display@10000 {
  162. compatible = "fsl,diu", "fsl,p1022-diu";
  163. reg = <0x10000 1000>;
  164. interrupts = <64 2 0 0>;
  165. };
  166. ssi@15000 {
  167. compatible = "fsl,mpc8610-ssi";
  168. cell-index = <0>;
  169. reg = <0x15000 0x100>;
  170. interrupts = <75 2 0 0>;
  171. fsl,playback-dma = <&dma00>;
  172. fsl,capture-dma = <&dma01>;
  173. fsl,fifo-depth = <15>;
  174. };
  175. /include/ "pq3-sata2-0.dtsi"
  176. /include/ "pq3-sata2-1.dtsi"
  177. L2: l2-cache-controller@20000 {
  178. compatible = "fsl,p1022-l2-cache-controller";
  179. reg = <0x20000 0x1000>;
  180. cache-line-size = <32>; // 32 bytes
  181. cache-size = <0x40000>; // L2,256K
  182. interrupts = <16 2 0 0>;
  183. };
  184. /include/ "pq3-dma-0.dtsi"
  185. /include/ "pq3-usb2-dr-0.dtsi"
  186. usb@22000 {
  187. compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
  188. };
  189. /include/ "pq3-usb2-dr-1.dtsi"
  190. usb@23000 {
  191. compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
  192. };
  193. /include/ "pq3-esdhc-0.dtsi"
  194. sdhc@2e000 {
  195. compatible = "fsl,p1022-esdhc", "fsl,esdhc";
  196. sdhci,auto-cmd12;
  197. };
  198. /include/ "pq3-sec3.3-0.dtsi"
  199. /include/ "pq3-mpic.dtsi"
  200. /include/ "pq3-mpic-timer-B.dtsi"
  201. /include/ "pq3-etsec2-0.dtsi"
  202. enet0: enet0_grp2: ethernet@b0000 {
  203. fsl,wake-on-filer;
  204. };
  205. /include/ "pq3-etsec2-1.dtsi"
  206. enet1: enet1_grp2: ethernet@b1000 {
  207. fsl,wake-on-filer;
  208. };
  209. global-utilities@e0000 {
  210. compatible = "fsl,p1022-guts";
  211. reg = <0xe0000 0x1000>;
  212. fsl,has-rstcr;
  213. };
  214. power@e0070{
  215. compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
  216. reg = <0xe0070 0x20>;
  217. };
  218. };
  219. /include/ "pq3-etsec2-grp2-0.dtsi"
  220. /include/ "pq3-etsec2-grp2-1.dtsi"