gef_ppc9a.dts 4.5 KB

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  1. /*
  2. * GE PPC9A Device Tree Source
  3. *
  4. * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. *
  11. * Based on: SBS CM6 Device Tree Source
  12. * Copyright 2007 SBS Technologies GmbH & Co. KG
  13. * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
  14. * Copyright 2006 Freescale Semiconductor Inc.
  15. */
  16. /*
  17. * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
  18. */
  19. /include/ "mpc8641si-pre.dtsi"
  20. / {
  21. model = "GEF_PPC9A";
  22. compatible = "gef,ppc9a";
  23. memory {
  24. device_type = "memory";
  25. reg = <0x0 0x40000000>; // set by uboot
  26. };
  27. lbc: localbus@fef05000 {
  28. reg = <0xfef05000 0x1000>;
  29. ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
  30. 1 0 0xe8000000 0x08000000 // Paged Flash 0
  31. 2 0 0xe0000000 0x08000000 // Paged Flash 1
  32. 3 0 0xfc100000 0x00020000 // NVRAM
  33. 4 0 0xfc000000 0x00008000 // FPGA
  34. 5 0 0xfc008000 0x00008000 // AFIX FPGA
  35. 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
  36. 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
  37. /* flash@0,0 is a mirror of part of the memory in flash@1,0
  38. flash@0,0 {
  39. compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
  40. reg = <0x0 0x0 0x1000000>;
  41. bank-width = <4>;
  42. device-width = <2>;
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. partition@0 {
  46. label = "firmware";
  47. reg = <0x0 0x1000000>;
  48. read-only;
  49. };
  50. };
  51. */
  52. flash@1,0 {
  53. compatible = "gef,ppc9a-paged-flash", "cfi-flash";
  54. reg = <0x1 0x0 0x8000000>;
  55. bank-width = <4>;
  56. device-width = <2>;
  57. #address-cells = <1>;
  58. #size-cells = <1>;
  59. partition@0 {
  60. label = "user";
  61. reg = <0x0 0x7800000>;
  62. };
  63. partition@7800000 {
  64. label = "firmware";
  65. reg = <0x7800000 0x800000>;
  66. read-only;
  67. };
  68. };
  69. nvram@3,0 {
  70. device_type = "nvram";
  71. compatible = "simtek,stk14ca8";
  72. reg = <0x3 0x0 0x20000>;
  73. };
  74. fpga@4,0 {
  75. compatible = "gef,ppc9a-fpga-regs";
  76. reg = <0x4 0x0 0x40>;
  77. };
  78. wdt@4,2000 {
  79. compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
  80. "gef,fpga-wdt";
  81. reg = <0x4 0x2000 0x8>;
  82. interrupts = <0x1a 0x4>;
  83. interrupt-parent = <&gef_pic>;
  84. };
  85. /* Second watchdog available, driver currently supports one.
  86. wdt@4,2010 {
  87. compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
  88. "gef,fpga-wdt";
  89. reg = <0x4 0x2010 0x8>;
  90. interrupts = <0x1b 0x4>;
  91. interrupt-parent = <&gef_pic>;
  92. };
  93. */
  94. gef_pic: pic@4,4000 {
  95. #interrupt-cells = <1>;
  96. interrupt-controller;
  97. compatible = "gef,ppc9a-fpga-pic", "gef,fpga-pic-1.00";
  98. reg = <0x4 0x4000 0x20>;
  99. interrupts = <0x8 0x9 0 0>;
  100. };
  101. gef_gpio: gpio@7,14000 {
  102. #gpio-cells = <2>;
  103. compatible = "gef,ppc9a-gpio", "gef,sbc610-gpio";
  104. reg = <0x7 0x14000 0x24>;
  105. gpio-controller;
  106. };
  107. };
  108. soc: soc@fef00000 {
  109. ranges = <0x0 0xfef00000 0x00100000>;
  110. i2c@3000 {
  111. hwmon@48 {
  112. compatible = "national,lm92";
  113. reg = <0x48>;
  114. };
  115. hwmon@4c {
  116. compatible = "adi,adt7461";
  117. reg = <0x4c>;
  118. };
  119. rtc@51 {
  120. compatible = "epson,rx8581";
  121. reg = <0x00000051>;
  122. };
  123. eti@6b {
  124. compatible = "dallas,ds1682";
  125. reg = <0x6b>;
  126. };
  127. };
  128. enet0: ethernet@24000 {
  129. tbi-handle = <&tbi0>;
  130. phy-handle = <&phy0>;
  131. phy-connection-type = "gmii";
  132. };
  133. mdio@24520 {
  134. phy0: ethernet-phy@0 {
  135. interrupt-parent = <&gef_pic>;
  136. interrupts = <0x9 0x4>;
  137. reg = <1>;
  138. };
  139. phy2: ethernet-phy@2 {
  140. interrupt-parent = <&gef_pic>;
  141. interrupts = <0x8 0x4>;
  142. reg = <3>;
  143. };
  144. tbi0: tbi-phy@11 {
  145. reg = <0x11>;
  146. device_type = "tbi-phy";
  147. };
  148. };
  149. enet1: ethernet@26000 {
  150. tbi-handle = <&tbi2>;
  151. phy-handle = <&phy2>;
  152. phy-connection-type = "gmii";
  153. };
  154. mdio@26520 {
  155. tbi2: tbi-phy@11 {
  156. reg = <0x11>;
  157. device_type = "tbi-phy";
  158. };
  159. };
  160. enet2: ethernet@25000 {
  161. status = "disabled";
  162. };
  163. mdio@25520 {
  164. status = "disabled";
  165. };
  166. enet3: ethernet@27000 {
  167. status = "disabled";
  168. };
  169. mdio@27520 {
  170. status = "disabled";
  171. };
  172. };
  173. pci0: pcie@fef08000 {
  174. reg = <0xfef08000 0x1000>;
  175. ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
  176. 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
  177. pcie@0 {
  178. ranges = <0x02000000 0x0 0x80000000
  179. 0x02000000 0x0 0x80000000
  180. 0x0 0x40000000
  181. 0x01000000 0x0 0x00000000
  182. 0x01000000 0x0 0x00000000
  183. 0x0 0x00400000>;
  184. };
  185. };
  186. pci1: pcie@fef09000 {
  187. status = "disabled";
  188. };
  189. };
  190. /include/ "mpc8641si-post.dtsi"