smsc911x.c 69 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669
  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2004-2008 SMSC
  4. * Copyright (C) 2005-2008 ARM
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18. *
  19. ***************************************************************************
  20. * Rewritten, heavily based on smsc911x simple driver by SMSC.
  21. * Partly uses io macros from smc91x.c by Nicolas Pitre
  22. *
  23. * Supported devices:
  24. * LAN9115, LAN9116, LAN9117, LAN9118
  25. * LAN9215, LAN9216, LAN9217, LAN9218
  26. * LAN9210, LAN9211
  27. * LAN9220, LAN9221
  28. * LAN89218
  29. *
  30. */
  31. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  32. #include <linux/crc32.h>
  33. #include <linux/clk.h>
  34. #include <linux/delay.h>
  35. #include <linux/errno.h>
  36. #include <linux/etherdevice.h>
  37. #include <linux/ethtool.h>
  38. #include <linux/init.h>
  39. #include <linux/interrupt.h>
  40. #include <linux/ioport.h>
  41. #include <linux/kernel.h>
  42. #include <linux/module.h>
  43. #include <linux/netdevice.h>
  44. #include <linux/platform_device.h>
  45. #include <linux/regulator/consumer.h>
  46. #include <linux/sched.h>
  47. #include <linux/timer.h>
  48. #include <linux/bug.h>
  49. #include <linux/bitops.h>
  50. #include <linux/irq.h>
  51. #include <linux/io.h>
  52. #include <linux/swab.h>
  53. #include <linux/phy.h>
  54. #include <linux/smsc911x.h>
  55. #include <linux/device.h>
  56. #include <linux/of.h>
  57. #include <linux/of_device.h>
  58. #include <linux/of_gpio.h>
  59. #include <linux/of_net.h>
  60. #include <linux/acpi.h>
  61. #include <linux/pm_runtime.h>
  62. #include <linux/property.h>
  63. #include <linux/gpio/consumer.h>
  64. #include "smsc911x.h"
  65. #define SMSC_CHIPNAME "smsc911x"
  66. #define SMSC_MDIONAME "smsc911x-mdio"
  67. #define SMSC_DRV_VERSION "2008-10-21"
  68. MODULE_LICENSE("GPL");
  69. MODULE_VERSION(SMSC_DRV_VERSION);
  70. MODULE_ALIAS("platform:smsc911x");
  71. #if USE_DEBUG > 0
  72. static int debug = 16;
  73. #else
  74. static int debug = 3;
  75. #endif
  76. module_param(debug, int, 0);
  77. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  78. struct smsc911x_data;
  79. struct smsc911x_ops {
  80. u32 (*reg_read)(struct smsc911x_data *pdata, u32 reg);
  81. void (*reg_write)(struct smsc911x_data *pdata, u32 reg, u32 val);
  82. void (*rx_readfifo)(struct smsc911x_data *pdata,
  83. unsigned int *buf, unsigned int wordcount);
  84. void (*tx_writefifo)(struct smsc911x_data *pdata,
  85. unsigned int *buf, unsigned int wordcount);
  86. };
  87. #define SMSC911X_NUM_SUPPLIES 2
  88. struct smsc911x_data {
  89. void __iomem *ioaddr;
  90. unsigned int idrev;
  91. /* used to decide which workarounds apply */
  92. unsigned int generation;
  93. /* device configuration (copied from platform_data during probe) */
  94. struct smsc911x_platform_config config;
  95. /* This needs to be acquired before calling any of below:
  96. * smsc911x_mac_read(), smsc911x_mac_write()
  97. */
  98. spinlock_t mac_lock;
  99. /* spinlock to ensure register accesses are serialised */
  100. spinlock_t dev_lock;
  101. struct mii_bus *mii_bus;
  102. unsigned int using_extphy;
  103. int last_duplex;
  104. int last_carrier;
  105. u32 msg_enable;
  106. unsigned int gpio_setting;
  107. unsigned int gpio_orig_setting;
  108. struct net_device *dev;
  109. struct napi_struct napi;
  110. unsigned int software_irq_signal;
  111. #ifdef USE_PHY_WORK_AROUND
  112. #define MIN_PACKET_SIZE (64)
  113. char loopback_tx_pkt[MIN_PACKET_SIZE];
  114. char loopback_rx_pkt[MIN_PACKET_SIZE];
  115. unsigned int resetcount;
  116. #endif
  117. /* Members for Multicast filter workaround */
  118. unsigned int multicast_update_pending;
  119. unsigned int set_bits_mask;
  120. unsigned int clear_bits_mask;
  121. unsigned int hashhi;
  122. unsigned int hashlo;
  123. /* register access functions */
  124. const struct smsc911x_ops *ops;
  125. /* regulators */
  126. struct regulator_bulk_data supplies[SMSC911X_NUM_SUPPLIES];
  127. /* Reset GPIO */
  128. struct gpio_desc *reset_gpiod;
  129. /* clock */
  130. struct clk *clk;
  131. };
  132. /* Easy access to information */
  133. #define __smsc_shift(pdata, reg) ((reg) << ((pdata)->config.shift))
  134. static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
  135. {
  136. if (pdata->config.flags & SMSC911X_USE_32BIT)
  137. return readl(pdata->ioaddr + reg);
  138. if (pdata->config.flags & SMSC911X_USE_16BIT)
  139. return ((readw(pdata->ioaddr + reg) & 0xFFFF) |
  140. ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
  141. BUG();
  142. return 0;
  143. }
  144. static inline u32
  145. __smsc911x_reg_read_shift(struct smsc911x_data *pdata, u32 reg)
  146. {
  147. if (pdata->config.flags & SMSC911X_USE_32BIT)
  148. return readl(pdata->ioaddr + __smsc_shift(pdata, reg));
  149. if (pdata->config.flags & SMSC911X_USE_16BIT)
  150. return (readw(pdata->ioaddr +
  151. __smsc_shift(pdata, reg)) & 0xFFFF) |
  152. ((readw(pdata->ioaddr +
  153. __smsc_shift(pdata, reg + 2)) & 0xFFFF) << 16);
  154. BUG();
  155. return 0;
  156. }
  157. static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
  158. {
  159. u32 data;
  160. unsigned long flags;
  161. spin_lock_irqsave(&pdata->dev_lock, flags);
  162. data = pdata->ops->reg_read(pdata, reg);
  163. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  164. return data;
  165. }
  166. static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
  167. u32 val)
  168. {
  169. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  170. writel(val, pdata->ioaddr + reg);
  171. return;
  172. }
  173. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  174. writew(val & 0xFFFF, pdata->ioaddr + reg);
  175. writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
  176. return;
  177. }
  178. BUG();
  179. }
  180. static inline void
  181. __smsc911x_reg_write_shift(struct smsc911x_data *pdata, u32 reg, u32 val)
  182. {
  183. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  184. writel(val, pdata->ioaddr + __smsc_shift(pdata, reg));
  185. return;
  186. }
  187. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  188. writew(val & 0xFFFF,
  189. pdata->ioaddr + __smsc_shift(pdata, reg));
  190. writew((val >> 16) & 0xFFFF,
  191. pdata->ioaddr + __smsc_shift(pdata, reg + 2));
  192. return;
  193. }
  194. BUG();
  195. }
  196. static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
  197. u32 val)
  198. {
  199. unsigned long flags;
  200. spin_lock_irqsave(&pdata->dev_lock, flags);
  201. pdata->ops->reg_write(pdata, reg, val);
  202. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  203. }
  204. /* Writes a packet to the TX_DATA_FIFO */
  205. static inline void
  206. smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
  207. unsigned int wordcount)
  208. {
  209. unsigned long flags;
  210. spin_lock_irqsave(&pdata->dev_lock, flags);
  211. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  212. while (wordcount--)
  213. __smsc911x_reg_write(pdata, TX_DATA_FIFO,
  214. swab32(*buf++));
  215. goto out;
  216. }
  217. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  218. iowrite32_rep(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
  219. goto out;
  220. }
  221. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  222. while (wordcount--)
  223. __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
  224. goto out;
  225. }
  226. BUG();
  227. out:
  228. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  229. }
  230. /* Writes a packet to the TX_DATA_FIFO - shifted version */
  231. static inline void
  232. smsc911x_tx_writefifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
  233. unsigned int wordcount)
  234. {
  235. unsigned long flags;
  236. spin_lock_irqsave(&pdata->dev_lock, flags);
  237. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  238. while (wordcount--)
  239. __smsc911x_reg_write_shift(pdata, TX_DATA_FIFO,
  240. swab32(*buf++));
  241. goto out;
  242. }
  243. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  244. iowrite32_rep(pdata->ioaddr + __smsc_shift(pdata,
  245. TX_DATA_FIFO), buf, wordcount);
  246. goto out;
  247. }
  248. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  249. while (wordcount--)
  250. __smsc911x_reg_write_shift(pdata,
  251. TX_DATA_FIFO, *buf++);
  252. goto out;
  253. }
  254. BUG();
  255. out:
  256. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  257. }
  258. /* Reads a packet out of the RX_DATA_FIFO */
  259. static inline void
  260. smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
  261. unsigned int wordcount)
  262. {
  263. unsigned long flags;
  264. spin_lock_irqsave(&pdata->dev_lock, flags);
  265. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  266. while (wordcount--)
  267. *buf++ = swab32(__smsc911x_reg_read(pdata,
  268. RX_DATA_FIFO));
  269. goto out;
  270. }
  271. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  272. ioread32_rep(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
  273. goto out;
  274. }
  275. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  276. while (wordcount--)
  277. *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO);
  278. goto out;
  279. }
  280. BUG();
  281. out:
  282. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  283. }
  284. /* Reads a packet out of the RX_DATA_FIFO - shifted version */
  285. static inline void
  286. smsc911x_rx_readfifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
  287. unsigned int wordcount)
  288. {
  289. unsigned long flags;
  290. spin_lock_irqsave(&pdata->dev_lock, flags);
  291. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  292. while (wordcount--)
  293. *buf++ = swab32(__smsc911x_reg_read_shift(pdata,
  294. RX_DATA_FIFO));
  295. goto out;
  296. }
  297. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  298. ioread32_rep(pdata->ioaddr + __smsc_shift(pdata,
  299. RX_DATA_FIFO), buf, wordcount);
  300. goto out;
  301. }
  302. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  303. while (wordcount--)
  304. *buf++ = __smsc911x_reg_read_shift(pdata,
  305. RX_DATA_FIFO);
  306. goto out;
  307. }
  308. BUG();
  309. out:
  310. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  311. }
  312. /*
  313. * enable regulator and clock resources.
  314. */
  315. static int smsc911x_enable_resources(struct platform_device *pdev)
  316. {
  317. struct net_device *ndev = platform_get_drvdata(pdev);
  318. struct smsc911x_data *pdata = netdev_priv(ndev);
  319. int ret = 0;
  320. ret = regulator_bulk_enable(ARRAY_SIZE(pdata->supplies),
  321. pdata->supplies);
  322. if (ret)
  323. netdev_err(ndev, "failed to enable regulators %d\n",
  324. ret);
  325. if (!IS_ERR(pdata->clk)) {
  326. ret = clk_prepare_enable(pdata->clk);
  327. if (ret < 0)
  328. netdev_err(ndev, "failed to enable clock %d\n", ret);
  329. }
  330. return ret;
  331. }
  332. /*
  333. * disable resources, currently just regulators.
  334. */
  335. static int smsc911x_disable_resources(struct platform_device *pdev)
  336. {
  337. struct net_device *ndev = platform_get_drvdata(pdev);
  338. struct smsc911x_data *pdata = netdev_priv(ndev);
  339. int ret = 0;
  340. ret = regulator_bulk_disable(ARRAY_SIZE(pdata->supplies),
  341. pdata->supplies);
  342. if (!IS_ERR(pdata->clk))
  343. clk_disable_unprepare(pdata->clk);
  344. return ret;
  345. }
  346. /*
  347. * Request resources, currently just regulators.
  348. *
  349. * The SMSC911x has two power pins: vddvario and vdd33a, in designs where
  350. * these are not always-on we need to request regulators to be turned on
  351. * before we can try to access the device registers.
  352. */
  353. static int smsc911x_request_resources(struct platform_device *pdev)
  354. {
  355. struct net_device *ndev = platform_get_drvdata(pdev);
  356. struct smsc911x_data *pdata = netdev_priv(ndev);
  357. int ret = 0;
  358. /* Request regulators */
  359. pdata->supplies[0].supply = "vdd33a";
  360. pdata->supplies[1].supply = "vddvario";
  361. ret = regulator_bulk_get(&pdev->dev,
  362. ARRAY_SIZE(pdata->supplies),
  363. pdata->supplies);
  364. if (ret) {
  365. /*
  366. * Retry on deferrals, else just report the error
  367. * and try to continue.
  368. */
  369. if (ret == -EPROBE_DEFER)
  370. return ret;
  371. netdev_err(ndev, "couldn't get regulators %d\n",
  372. ret);
  373. }
  374. /* Request optional RESET GPIO */
  375. pdata->reset_gpiod = devm_gpiod_get_optional(&pdev->dev,
  376. "reset",
  377. GPIOD_OUT_LOW);
  378. /* Request clock */
  379. pdata->clk = clk_get(&pdev->dev, NULL);
  380. if (IS_ERR(pdata->clk))
  381. dev_dbg(&pdev->dev, "couldn't get clock %li\n",
  382. PTR_ERR(pdata->clk));
  383. return ret;
  384. }
  385. /*
  386. * Free resources, currently just regulators.
  387. *
  388. */
  389. static void smsc911x_free_resources(struct platform_device *pdev)
  390. {
  391. struct net_device *ndev = platform_get_drvdata(pdev);
  392. struct smsc911x_data *pdata = netdev_priv(ndev);
  393. /* Free regulators */
  394. regulator_bulk_free(ARRAY_SIZE(pdata->supplies),
  395. pdata->supplies);
  396. /* Free clock */
  397. if (!IS_ERR(pdata->clk)) {
  398. clk_put(pdata->clk);
  399. pdata->clk = NULL;
  400. }
  401. }
  402. /* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
  403. * and smsc911x_mac_write, so assumes mac_lock is held */
  404. static int smsc911x_mac_complete(struct smsc911x_data *pdata)
  405. {
  406. int i;
  407. u32 val;
  408. SMSC_ASSERT_MAC_LOCK(pdata);
  409. for (i = 0; i < 40; i++) {
  410. val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  411. if (!(val & MAC_CSR_CMD_CSR_BUSY_))
  412. return 0;
  413. }
  414. SMSC_WARN(pdata, hw, "Timed out waiting for MAC not BUSY. "
  415. "MAC_CSR_CMD: 0x%08X", val);
  416. return -EIO;
  417. }
  418. /* Fetches a MAC register value. Assumes mac_lock is acquired */
  419. static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
  420. {
  421. unsigned int temp;
  422. SMSC_ASSERT_MAC_LOCK(pdata);
  423. temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  424. if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
  425. SMSC_WARN(pdata, hw, "MAC busy at entry");
  426. return 0xFFFFFFFF;
  427. }
  428. /* Send the MAC cmd */
  429. smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
  430. MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
  431. /* Workaround for hardware read-after-write restriction */
  432. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  433. /* Wait for the read to complete */
  434. if (likely(smsc911x_mac_complete(pdata) == 0))
  435. return smsc911x_reg_read(pdata, MAC_CSR_DATA);
  436. SMSC_WARN(pdata, hw, "MAC busy after read");
  437. return 0xFFFFFFFF;
  438. }
  439. /* Set a mac register, mac_lock must be acquired before calling */
  440. static void smsc911x_mac_write(struct smsc911x_data *pdata,
  441. unsigned int offset, u32 val)
  442. {
  443. unsigned int temp;
  444. SMSC_ASSERT_MAC_LOCK(pdata);
  445. temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  446. if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
  447. SMSC_WARN(pdata, hw,
  448. "smsc911x_mac_write failed, MAC busy at entry");
  449. return;
  450. }
  451. /* Send data to write */
  452. smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
  453. /* Write the actual data */
  454. smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
  455. MAC_CSR_CMD_CSR_BUSY_));
  456. /* Workaround for hardware read-after-write restriction */
  457. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  458. /* Wait for the write to complete */
  459. if (likely(smsc911x_mac_complete(pdata) == 0))
  460. return;
  461. SMSC_WARN(pdata, hw, "smsc911x_mac_write failed, MAC busy after write");
  462. }
  463. /* Get a phy register */
  464. static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
  465. {
  466. struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
  467. unsigned long flags;
  468. unsigned int addr;
  469. int i, reg;
  470. spin_lock_irqsave(&pdata->mac_lock, flags);
  471. /* Confirm MII not busy */
  472. if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  473. SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_read???");
  474. reg = -EIO;
  475. goto out;
  476. }
  477. /* Set the address, index & direction (read from PHY) */
  478. addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
  479. smsc911x_mac_write(pdata, MII_ACC, addr);
  480. /* Wait for read to complete w/ timeout */
  481. for (i = 0; i < 100; i++)
  482. if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  483. reg = smsc911x_mac_read(pdata, MII_DATA);
  484. goto out;
  485. }
  486. SMSC_WARN(pdata, hw, "Timed out waiting for MII read to finish");
  487. reg = -EIO;
  488. out:
  489. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  490. return reg;
  491. }
  492. /* Set a phy register */
  493. static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
  494. u16 val)
  495. {
  496. struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
  497. unsigned long flags;
  498. unsigned int addr;
  499. int i, reg;
  500. spin_lock_irqsave(&pdata->mac_lock, flags);
  501. /* Confirm MII not busy */
  502. if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  503. SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_write???");
  504. reg = -EIO;
  505. goto out;
  506. }
  507. /* Put the data to write in the MAC */
  508. smsc911x_mac_write(pdata, MII_DATA, val);
  509. /* Set the address, index & direction (write to PHY) */
  510. addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
  511. MII_ACC_MII_WRITE_;
  512. smsc911x_mac_write(pdata, MII_ACC, addr);
  513. /* Wait for write to complete w/ timeout */
  514. for (i = 0; i < 100; i++)
  515. if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  516. reg = 0;
  517. goto out;
  518. }
  519. SMSC_WARN(pdata, hw, "Timed out waiting for MII write to finish");
  520. reg = -EIO;
  521. out:
  522. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  523. return reg;
  524. }
  525. /* Switch to external phy. Assumes tx and rx are stopped. */
  526. static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
  527. {
  528. unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
  529. /* Disable phy clocks to the MAC */
  530. hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
  531. hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
  532. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  533. udelay(10); /* Enough time for clocks to stop */
  534. /* Switch to external phy */
  535. hwcfg |= HW_CFG_EXT_PHY_EN_;
  536. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  537. /* Enable phy clocks to the MAC */
  538. hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
  539. hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
  540. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  541. udelay(10); /* Enough time for clocks to restart */
  542. hwcfg |= HW_CFG_SMI_SEL_;
  543. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  544. }
  545. /* Autodetects and enables external phy if present on supported chips.
  546. * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
  547. * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
  548. static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
  549. {
  550. unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
  551. if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
  552. SMSC_TRACE(pdata, hw, "Forcing internal PHY");
  553. pdata->using_extphy = 0;
  554. } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
  555. SMSC_TRACE(pdata, hw, "Forcing external PHY");
  556. smsc911x_phy_enable_external(pdata);
  557. pdata->using_extphy = 1;
  558. } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
  559. SMSC_TRACE(pdata, hw,
  560. "HW_CFG EXT_PHY_DET set, using external PHY");
  561. smsc911x_phy_enable_external(pdata);
  562. pdata->using_extphy = 1;
  563. } else {
  564. SMSC_TRACE(pdata, hw,
  565. "HW_CFG EXT_PHY_DET clear, using internal PHY");
  566. pdata->using_extphy = 0;
  567. }
  568. }
  569. /* Fetches a tx status out of the status fifo */
  570. static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
  571. {
  572. unsigned int result =
  573. smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
  574. if (result != 0)
  575. result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
  576. return result;
  577. }
  578. /* Fetches the next rx status */
  579. static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
  580. {
  581. unsigned int result =
  582. smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
  583. if (result != 0)
  584. result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
  585. return result;
  586. }
  587. #ifdef USE_PHY_WORK_AROUND
  588. static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
  589. {
  590. unsigned int tries;
  591. u32 wrsz;
  592. u32 rdsz;
  593. ulong bufp;
  594. for (tries = 0; tries < 10; tries++) {
  595. unsigned int txcmd_a;
  596. unsigned int txcmd_b;
  597. unsigned int status;
  598. unsigned int pktlength;
  599. unsigned int i;
  600. /* Zero-out rx packet memory */
  601. memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
  602. /* Write tx packet to 118 */
  603. txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
  604. txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  605. txcmd_a |= MIN_PACKET_SIZE;
  606. txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
  607. smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
  608. smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
  609. bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
  610. wrsz = MIN_PACKET_SIZE + 3;
  611. wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
  612. wrsz >>= 2;
  613. pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
  614. /* Wait till transmit is done */
  615. i = 60;
  616. do {
  617. udelay(5);
  618. status = smsc911x_tx_get_txstatus(pdata);
  619. } while ((i--) && (!status));
  620. if (!status) {
  621. SMSC_WARN(pdata, hw,
  622. "Failed to transmit during loopback test");
  623. continue;
  624. }
  625. if (status & TX_STS_ES_) {
  626. SMSC_WARN(pdata, hw,
  627. "Transmit encountered errors during loopback test");
  628. continue;
  629. }
  630. /* Wait till receive is done */
  631. i = 60;
  632. do {
  633. udelay(5);
  634. status = smsc911x_rx_get_rxstatus(pdata);
  635. } while ((i--) && (!status));
  636. if (!status) {
  637. SMSC_WARN(pdata, hw,
  638. "Failed to receive during loopback test");
  639. continue;
  640. }
  641. if (status & RX_STS_ES_) {
  642. SMSC_WARN(pdata, hw,
  643. "Receive encountered errors during loopback test");
  644. continue;
  645. }
  646. pktlength = ((status & 0x3FFF0000UL) >> 16);
  647. bufp = (ulong)pdata->loopback_rx_pkt;
  648. rdsz = pktlength + 3;
  649. rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
  650. rdsz >>= 2;
  651. pdata->ops->rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
  652. if (pktlength != (MIN_PACKET_SIZE + 4)) {
  653. SMSC_WARN(pdata, hw, "Unexpected packet size "
  654. "during loop back test, size=%d, will retry",
  655. pktlength);
  656. } else {
  657. unsigned int j;
  658. int mismatch = 0;
  659. for (j = 0; j < MIN_PACKET_SIZE; j++) {
  660. if (pdata->loopback_tx_pkt[j]
  661. != pdata->loopback_rx_pkt[j]) {
  662. mismatch = 1;
  663. break;
  664. }
  665. }
  666. if (!mismatch) {
  667. SMSC_TRACE(pdata, hw, "Successfully verified "
  668. "loopback packet");
  669. return 0;
  670. } else {
  671. SMSC_WARN(pdata, hw, "Data mismatch "
  672. "during loop back test, will retry");
  673. }
  674. }
  675. }
  676. return -EIO;
  677. }
  678. static int smsc911x_phy_reset(struct smsc911x_data *pdata)
  679. {
  680. unsigned int temp;
  681. unsigned int i = 100000;
  682. temp = smsc911x_reg_read(pdata, PMT_CTRL);
  683. smsc911x_reg_write(pdata, PMT_CTRL, temp | PMT_CTRL_PHY_RST_);
  684. do {
  685. msleep(1);
  686. temp = smsc911x_reg_read(pdata, PMT_CTRL);
  687. } while ((i--) && (temp & PMT_CTRL_PHY_RST_));
  688. if (unlikely(temp & PMT_CTRL_PHY_RST_)) {
  689. SMSC_WARN(pdata, hw, "PHY reset failed to complete");
  690. return -EIO;
  691. }
  692. /* Extra delay required because the phy may not be completed with
  693. * its reset when BMCR_RESET is cleared. Specs say 256 uS is
  694. * enough delay but using 1ms here to be safe */
  695. msleep(1);
  696. return 0;
  697. }
  698. static int smsc911x_phy_loopbacktest(struct net_device *dev)
  699. {
  700. struct smsc911x_data *pdata = netdev_priv(dev);
  701. struct phy_device *phy_dev = dev->phydev;
  702. int result = -EIO;
  703. unsigned int i, val;
  704. unsigned long flags;
  705. /* Initialise tx packet using broadcast destination address */
  706. eth_broadcast_addr(pdata->loopback_tx_pkt);
  707. /* Use incrementing source address */
  708. for (i = 6; i < 12; i++)
  709. pdata->loopback_tx_pkt[i] = (char)i;
  710. /* Set length type field */
  711. pdata->loopback_tx_pkt[12] = 0x00;
  712. pdata->loopback_tx_pkt[13] = 0x00;
  713. for (i = 14; i < MIN_PACKET_SIZE; i++)
  714. pdata->loopback_tx_pkt[i] = (char)i;
  715. val = smsc911x_reg_read(pdata, HW_CFG);
  716. val &= HW_CFG_TX_FIF_SZ_;
  717. val |= HW_CFG_SF_;
  718. smsc911x_reg_write(pdata, HW_CFG, val);
  719. smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
  720. smsc911x_reg_write(pdata, RX_CFG,
  721. (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
  722. for (i = 0; i < 10; i++) {
  723. /* Set PHY to 10/FD, no ANEG, and loopback mode */
  724. smsc911x_mii_write(phy_dev->mdio.bus, phy_dev->mdio.addr,
  725. MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX);
  726. /* Enable MAC tx/rx, FD */
  727. spin_lock_irqsave(&pdata->mac_lock, flags);
  728. smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
  729. | MAC_CR_TXEN_ | MAC_CR_RXEN_);
  730. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  731. if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
  732. result = 0;
  733. break;
  734. }
  735. pdata->resetcount++;
  736. /* Disable MAC rx */
  737. spin_lock_irqsave(&pdata->mac_lock, flags);
  738. smsc911x_mac_write(pdata, MAC_CR, 0);
  739. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  740. smsc911x_phy_reset(pdata);
  741. }
  742. /* Disable MAC */
  743. spin_lock_irqsave(&pdata->mac_lock, flags);
  744. smsc911x_mac_write(pdata, MAC_CR, 0);
  745. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  746. /* Cancel PHY loopback mode */
  747. smsc911x_mii_write(phy_dev->mdio.bus, phy_dev->mdio.addr, MII_BMCR, 0);
  748. smsc911x_reg_write(pdata, TX_CFG, 0);
  749. smsc911x_reg_write(pdata, RX_CFG, 0);
  750. return result;
  751. }
  752. #endif /* USE_PHY_WORK_AROUND */
  753. static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
  754. {
  755. struct net_device *ndev = pdata->dev;
  756. struct phy_device *phy_dev = ndev->phydev;
  757. u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
  758. u32 flow;
  759. unsigned long flags;
  760. if (phy_dev->duplex == DUPLEX_FULL) {
  761. u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
  762. u16 rmtadv = phy_read(phy_dev, MII_LPA);
  763. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  764. if (cap & FLOW_CTRL_RX)
  765. flow = 0xFFFF0002;
  766. else
  767. flow = 0;
  768. if (cap & FLOW_CTRL_TX)
  769. afc |= 0xF;
  770. else
  771. afc &= ~0xF;
  772. SMSC_TRACE(pdata, hw, "rx pause %s, tx pause %s",
  773. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  774. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  775. } else {
  776. SMSC_TRACE(pdata, hw, "half duplex");
  777. flow = 0;
  778. afc |= 0xF;
  779. }
  780. spin_lock_irqsave(&pdata->mac_lock, flags);
  781. smsc911x_mac_write(pdata, FLOW, flow);
  782. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  783. smsc911x_reg_write(pdata, AFC_CFG, afc);
  784. }
  785. /* Update link mode if anything has changed. Called periodically when the
  786. * PHY is in polling mode, even if nothing has changed. */
  787. static void smsc911x_phy_adjust_link(struct net_device *dev)
  788. {
  789. struct smsc911x_data *pdata = netdev_priv(dev);
  790. struct phy_device *phy_dev = dev->phydev;
  791. unsigned long flags;
  792. int carrier;
  793. if (phy_dev->duplex != pdata->last_duplex) {
  794. unsigned int mac_cr;
  795. SMSC_TRACE(pdata, hw, "duplex state has changed");
  796. spin_lock_irqsave(&pdata->mac_lock, flags);
  797. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  798. if (phy_dev->duplex) {
  799. SMSC_TRACE(pdata, hw,
  800. "configuring for full duplex mode");
  801. mac_cr |= MAC_CR_FDPX_;
  802. } else {
  803. SMSC_TRACE(pdata, hw,
  804. "configuring for half duplex mode");
  805. mac_cr &= ~MAC_CR_FDPX_;
  806. }
  807. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  808. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  809. smsc911x_phy_update_flowcontrol(pdata);
  810. pdata->last_duplex = phy_dev->duplex;
  811. }
  812. carrier = netif_carrier_ok(dev);
  813. if (carrier != pdata->last_carrier) {
  814. SMSC_TRACE(pdata, hw, "carrier state has changed");
  815. if (carrier) {
  816. SMSC_TRACE(pdata, hw, "configuring for carrier OK");
  817. if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
  818. (!pdata->using_extphy)) {
  819. /* Restore original GPIO configuration */
  820. pdata->gpio_setting = pdata->gpio_orig_setting;
  821. smsc911x_reg_write(pdata, GPIO_CFG,
  822. pdata->gpio_setting);
  823. }
  824. } else {
  825. SMSC_TRACE(pdata, hw, "configuring for no carrier");
  826. /* Check global setting that LED1
  827. * usage is 10/100 indicator */
  828. pdata->gpio_setting = smsc911x_reg_read(pdata,
  829. GPIO_CFG);
  830. if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) &&
  831. (!pdata->using_extphy)) {
  832. /* Force 10/100 LED off, after saving
  833. * original GPIO configuration */
  834. pdata->gpio_orig_setting = pdata->gpio_setting;
  835. pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
  836. pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
  837. | GPIO_CFG_GPIODIR0_
  838. | GPIO_CFG_GPIOD0_);
  839. smsc911x_reg_write(pdata, GPIO_CFG,
  840. pdata->gpio_setting);
  841. }
  842. }
  843. pdata->last_carrier = carrier;
  844. }
  845. }
  846. static int smsc911x_mii_probe(struct net_device *dev)
  847. {
  848. struct smsc911x_data *pdata = netdev_priv(dev);
  849. struct phy_device *phydev = NULL;
  850. int ret;
  851. /* find the first phy */
  852. phydev = phy_find_first(pdata->mii_bus);
  853. if (!phydev) {
  854. netdev_err(dev, "no PHY found\n");
  855. return -ENODEV;
  856. }
  857. SMSC_TRACE(pdata, probe, "PHY: addr %d, phy_id 0x%08X",
  858. phydev->mdio.addr, phydev->phy_id);
  859. ret = phy_connect_direct(dev, phydev, &smsc911x_phy_adjust_link,
  860. pdata->config.phy_interface);
  861. if (ret) {
  862. netdev_err(dev, "Could not attach to PHY\n");
  863. return ret;
  864. }
  865. phy_attached_info(phydev);
  866. /* mask with MAC supported features */
  867. phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
  868. SUPPORTED_Asym_Pause);
  869. phydev->advertising = phydev->supported;
  870. pdata->last_duplex = -1;
  871. pdata->last_carrier = -1;
  872. #ifdef USE_PHY_WORK_AROUND
  873. if (smsc911x_phy_loopbacktest(dev) < 0) {
  874. SMSC_WARN(pdata, hw, "Failed Loop Back Test");
  875. phy_disconnect(phydev);
  876. return -ENODEV;
  877. }
  878. SMSC_TRACE(pdata, hw, "Passed Loop Back Test");
  879. #endif /* USE_PHY_WORK_AROUND */
  880. SMSC_TRACE(pdata, hw, "phy initialised successfully");
  881. return 0;
  882. }
  883. static int smsc911x_mii_init(struct platform_device *pdev,
  884. struct net_device *dev)
  885. {
  886. struct smsc911x_data *pdata = netdev_priv(dev);
  887. int err = -ENXIO;
  888. pdata->mii_bus = mdiobus_alloc();
  889. if (!pdata->mii_bus) {
  890. err = -ENOMEM;
  891. goto err_out_1;
  892. }
  893. pdata->mii_bus->name = SMSC_MDIONAME;
  894. snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
  895. pdev->name, pdev->id);
  896. pdata->mii_bus->priv = pdata;
  897. pdata->mii_bus->read = smsc911x_mii_read;
  898. pdata->mii_bus->write = smsc911x_mii_write;
  899. pdata->mii_bus->parent = &pdev->dev;
  900. switch (pdata->idrev & 0xFFFF0000) {
  901. case 0x01170000:
  902. case 0x01150000:
  903. case 0x117A0000:
  904. case 0x115A0000:
  905. /* External PHY supported, try to autodetect */
  906. smsc911x_phy_initialise_external(pdata);
  907. break;
  908. default:
  909. SMSC_TRACE(pdata, hw, "External PHY is not supported, "
  910. "using internal PHY");
  911. pdata->using_extphy = 0;
  912. break;
  913. }
  914. if (!pdata->using_extphy) {
  915. /* Mask all PHYs except ID 1 (internal) */
  916. pdata->mii_bus->phy_mask = ~(1 << 1);
  917. }
  918. if (mdiobus_register(pdata->mii_bus)) {
  919. SMSC_WARN(pdata, probe, "Error registering mii bus");
  920. goto err_out_free_bus_2;
  921. }
  922. return 0;
  923. err_out_free_bus_2:
  924. mdiobus_free(pdata->mii_bus);
  925. err_out_1:
  926. return err;
  927. }
  928. /* Gets the number of tx statuses in the fifo */
  929. static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
  930. {
  931. return (smsc911x_reg_read(pdata, TX_FIFO_INF)
  932. & TX_FIFO_INF_TSUSED_) >> 16;
  933. }
  934. /* Reads tx statuses and increments counters where necessary */
  935. static void smsc911x_tx_update_txcounters(struct net_device *dev)
  936. {
  937. struct smsc911x_data *pdata = netdev_priv(dev);
  938. unsigned int tx_stat;
  939. while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
  940. if (unlikely(tx_stat & 0x80000000)) {
  941. /* In this driver the packet tag is used as the packet
  942. * length. Since a packet length can never reach the
  943. * size of 0x8000, this bit is reserved. It is worth
  944. * noting that the "reserved bit" in the warning above
  945. * does not reference a hardware defined reserved bit
  946. * but rather a driver defined one.
  947. */
  948. SMSC_WARN(pdata, hw, "Packet tag reserved bit is high");
  949. } else {
  950. if (unlikely(tx_stat & TX_STS_ES_)) {
  951. dev->stats.tx_errors++;
  952. } else {
  953. dev->stats.tx_packets++;
  954. dev->stats.tx_bytes += (tx_stat >> 16);
  955. }
  956. if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
  957. dev->stats.collisions += 16;
  958. dev->stats.tx_aborted_errors += 1;
  959. } else {
  960. dev->stats.collisions +=
  961. ((tx_stat >> 3) & 0xF);
  962. }
  963. if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
  964. dev->stats.tx_carrier_errors += 1;
  965. if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
  966. dev->stats.collisions++;
  967. dev->stats.tx_aborted_errors++;
  968. }
  969. }
  970. }
  971. }
  972. /* Increments the Rx error counters */
  973. static void
  974. smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
  975. {
  976. int crc_err = 0;
  977. if (unlikely(rxstat & RX_STS_ES_)) {
  978. dev->stats.rx_errors++;
  979. if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
  980. dev->stats.rx_crc_errors++;
  981. crc_err = 1;
  982. }
  983. }
  984. if (likely(!crc_err)) {
  985. if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
  986. (rxstat & RX_STS_LENGTH_ERR_)))
  987. dev->stats.rx_length_errors++;
  988. if (rxstat & RX_STS_MCAST_)
  989. dev->stats.multicast++;
  990. }
  991. }
  992. /* Quickly dumps bad packets */
  993. static void
  994. smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktwords)
  995. {
  996. if (likely(pktwords >= 4)) {
  997. unsigned int timeout = 500;
  998. unsigned int val;
  999. smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
  1000. do {
  1001. udelay(1);
  1002. val = smsc911x_reg_read(pdata, RX_DP_CTRL);
  1003. } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
  1004. if (unlikely(timeout == 0))
  1005. SMSC_WARN(pdata, hw, "Timed out waiting for "
  1006. "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
  1007. } else {
  1008. unsigned int temp;
  1009. while (pktwords--)
  1010. temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
  1011. }
  1012. }
  1013. /* NAPI poll function */
  1014. static int smsc911x_poll(struct napi_struct *napi, int budget)
  1015. {
  1016. struct smsc911x_data *pdata =
  1017. container_of(napi, struct smsc911x_data, napi);
  1018. struct net_device *dev = pdata->dev;
  1019. int npackets = 0;
  1020. while (npackets < budget) {
  1021. unsigned int pktlength;
  1022. unsigned int pktwords;
  1023. struct sk_buff *skb;
  1024. unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
  1025. if (!rxstat) {
  1026. unsigned int temp;
  1027. /* We processed all packets available. Tell NAPI it can
  1028. * stop polling then re-enable rx interrupts */
  1029. smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
  1030. napi_complete(napi);
  1031. temp = smsc911x_reg_read(pdata, INT_EN);
  1032. temp |= INT_EN_RSFL_EN_;
  1033. smsc911x_reg_write(pdata, INT_EN, temp);
  1034. break;
  1035. }
  1036. /* Count packet for NAPI scheduling, even if it has an error.
  1037. * Error packets still require cycles to discard */
  1038. npackets++;
  1039. pktlength = ((rxstat & 0x3FFF0000) >> 16);
  1040. pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
  1041. smsc911x_rx_counterrors(dev, rxstat);
  1042. if (unlikely(rxstat & RX_STS_ES_)) {
  1043. SMSC_WARN(pdata, rx_err,
  1044. "Discarding packet with error bit set");
  1045. /* Packet has an error, discard it and continue with
  1046. * the next */
  1047. smsc911x_rx_fastforward(pdata, pktwords);
  1048. dev->stats.rx_dropped++;
  1049. continue;
  1050. }
  1051. skb = netdev_alloc_skb(dev, pktwords << 2);
  1052. if (unlikely(!skb)) {
  1053. SMSC_WARN(pdata, rx_err,
  1054. "Unable to allocate skb for rx packet");
  1055. /* Drop the packet and stop this polling iteration */
  1056. smsc911x_rx_fastforward(pdata, pktwords);
  1057. dev->stats.rx_dropped++;
  1058. break;
  1059. }
  1060. pdata->ops->rx_readfifo(pdata,
  1061. (unsigned int *)skb->data, pktwords);
  1062. /* Align IP on 16B boundary */
  1063. skb_reserve(skb, NET_IP_ALIGN);
  1064. skb_put(skb, pktlength - 4);
  1065. skb->protocol = eth_type_trans(skb, dev);
  1066. skb_checksum_none_assert(skb);
  1067. netif_receive_skb(skb);
  1068. /* Update counters */
  1069. dev->stats.rx_packets++;
  1070. dev->stats.rx_bytes += (pktlength - 4);
  1071. }
  1072. /* Return total received packets */
  1073. return npackets;
  1074. }
  1075. /* Returns hash bit number for given MAC address
  1076. * Example:
  1077. * 01 00 5E 00 00 01 -> returns bit number 31 */
  1078. static unsigned int smsc911x_hash(char addr[ETH_ALEN])
  1079. {
  1080. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  1081. }
  1082. static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
  1083. {
  1084. /* Performs the multicast & mac_cr update. This is called when
  1085. * safe on the current hardware, and with the mac_lock held */
  1086. unsigned int mac_cr;
  1087. SMSC_ASSERT_MAC_LOCK(pdata);
  1088. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  1089. mac_cr |= pdata->set_bits_mask;
  1090. mac_cr &= ~(pdata->clear_bits_mask);
  1091. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  1092. smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
  1093. smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
  1094. SMSC_TRACE(pdata, hw, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
  1095. mac_cr, pdata->hashhi, pdata->hashlo);
  1096. }
  1097. static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
  1098. {
  1099. unsigned int mac_cr;
  1100. /* This function is only called for older LAN911x devices
  1101. * (revA or revB), where MAC_CR, HASHH and HASHL should not
  1102. * be modified during Rx - newer devices immediately update the
  1103. * registers.
  1104. *
  1105. * This is called from interrupt context */
  1106. spin_lock(&pdata->mac_lock);
  1107. /* Check Rx has stopped */
  1108. if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
  1109. SMSC_WARN(pdata, drv, "Rx not stopped");
  1110. /* Perform the update - safe to do now Rx has stopped */
  1111. smsc911x_rx_multicast_update(pdata);
  1112. /* Re-enable Rx */
  1113. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  1114. mac_cr |= MAC_CR_RXEN_;
  1115. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  1116. pdata->multicast_update_pending = 0;
  1117. spin_unlock(&pdata->mac_lock);
  1118. }
  1119. static int smsc911x_phy_general_power_up(struct smsc911x_data *pdata)
  1120. {
  1121. struct net_device *ndev = pdata->dev;
  1122. struct phy_device *phy_dev = ndev->phydev;
  1123. int rc = 0;
  1124. if (!phy_dev)
  1125. return rc;
  1126. /* If the internal PHY is in General Power-Down mode, all, except the
  1127. * management interface, is powered-down and stays in that condition as
  1128. * long as Phy register bit 0.11 is HIGH.
  1129. *
  1130. * In that case, clear the bit 0.11, so the PHY powers up and we can
  1131. * access to the phy registers.
  1132. */
  1133. rc = phy_read(phy_dev, MII_BMCR);
  1134. if (rc < 0) {
  1135. SMSC_WARN(pdata, drv, "Failed reading PHY control reg");
  1136. return rc;
  1137. }
  1138. /* If the PHY general power-down bit is not set is not necessary to
  1139. * disable the general power down-mode.
  1140. */
  1141. if (rc & BMCR_PDOWN) {
  1142. rc = phy_write(phy_dev, MII_BMCR, rc & ~BMCR_PDOWN);
  1143. if (rc < 0) {
  1144. SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
  1145. return rc;
  1146. }
  1147. usleep_range(1000, 1500);
  1148. }
  1149. return 0;
  1150. }
  1151. static int smsc911x_phy_disable_energy_detect(struct smsc911x_data *pdata)
  1152. {
  1153. struct net_device *ndev = pdata->dev;
  1154. struct phy_device *phy_dev = ndev->phydev;
  1155. int rc = 0;
  1156. if (!phy_dev)
  1157. return rc;
  1158. rc = phy_read(phy_dev, MII_LAN83C185_CTRL_STATUS);
  1159. if (rc < 0) {
  1160. SMSC_WARN(pdata, drv, "Failed reading PHY control reg");
  1161. return rc;
  1162. }
  1163. /* Only disable if energy detect mode is already enabled */
  1164. if (rc & MII_LAN83C185_EDPWRDOWN) {
  1165. /* Disable energy detect mode for this SMSC Transceivers */
  1166. rc = phy_write(phy_dev, MII_LAN83C185_CTRL_STATUS,
  1167. rc & (~MII_LAN83C185_EDPWRDOWN));
  1168. if (rc < 0) {
  1169. SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
  1170. return rc;
  1171. }
  1172. /* Allow PHY to wakeup */
  1173. mdelay(2);
  1174. }
  1175. return 0;
  1176. }
  1177. static int smsc911x_phy_enable_energy_detect(struct smsc911x_data *pdata)
  1178. {
  1179. struct net_device *ndev = pdata->dev;
  1180. struct phy_device *phy_dev = ndev->phydev;
  1181. int rc = 0;
  1182. if (!phy_dev)
  1183. return rc;
  1184. rc = phy_read(phy_dev, MII_LAN83C185_CTRL_STATUS);
  1185. if (rc < 0) {
  1186. SMSC_WARN(pdata, drv, "Failed reading PHY control reg");
  1187. return rc;
  1188. }
  1189. /* Only enable if energy detect mode is already disabled */
  1190. if (!(rc & MII_LAN83C185_EDPWRDOWN)) {
  1191. /* Enable energy detect mode for this SMSC Transceivers */
  1192. rc = phy_write(phy_dev, MII_LAN83C185_CTRL_STATUS,
  1193. rc | MII_LAN83C185_EDPWRDOWN);
  1194. if (rc < 0) {
  1195. SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
  1196. return rc;
  1197. }
  1198. }
  1199. return 0;
  1200. }
  1201. static int smsc911x_soft_reset(struct smsc911x_data *pdata)
  1202. {
  1203. unsigned int timeout;
  1204. unsigned int temp;
  1205. int ret;
  1206. /*
  1207. * Make sure to power-up the PHY chip before doing a reset, otherwise
  1208. * the reset fails.
  1209. */
  1210. ret = smsc911x_phy_general_power_up(pdata);
  1211. if (ret) {
  1212. SMSC_WARN(pdata, drv, "Failed to power-up the PHY chip");
  1213. return ret;
  1214. }
  1215. /*
  1216. * LAN9210/LAN9211/LAN9220/LAN9221 chips have an internal PHY that
  1217. * are initialized in a Energy Detect Power-Down mode that prevents
  1218. * the MAC chip to be software reseted. So we have to wakeup the PHY
  1219. * before.
  1220. */
  1221. if (pdata->generation == 4) {
  1222. ret = smsc911x_phy_disable_energy_detect(pdata);
  1223. if (ret) {
  1224. SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip");
  1225. return ret;
  1226. }
  1227. }
  1228. /* Reset the LAN911x */
  1229. smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
  1230. timeout = 10;
  1231. do {
  1232. udelay(10);
  1233. temp = smsc911x_reg_read(pdata, HW_CFG);
  1234. } while ((--timeout) && (temp & HW_CFG_SRST_));
  1235. if (unlikely(temp & HW_CFG_SRST_)) {
  1236. SMSC_WARN(pdata, drv, "Failed to complete reset");
  1237. return -EIO;
  1238. }
  1239. if (pdata->generation == 4) {
  1240. ret = smsc911x_phy_enable_energy_detect(pdata);
  1241. if (ret) {
  1242. SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip");
  1243. return ret;
  1244. }
  1245. }
  1246. return 0;
  1247. }
  1248. /* Sets the device MAC address to dev_addr, called with mac_lock held */
  1249. static void
  1250. smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
  1251. {
  1252. u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
  1253. u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
  1254. (dev_addr[1] << 8) | dev_addr[0];
  1255. SMSC_ASSERT_MAC_LOCK(pdata);
  1256. smsc911x_mac_write(pdata, ADDRH, mac_high16);
  1257. smsc911x_mac_write(pdata, ADDRL, mac_low32);
  1258. }
  1259. static void smsc911x_disable_irq_chip(struct net_device *dev)
  1260. {
  1261. struct smsc911x_data *pdata = netdev_priv(dev);
  1262. smsc911x_reg_write(pdata, INT_EN, 0);
  1263. smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
  1264. }
  1265. static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
  1266. {
  1267. struct net_device *dev = dev_id;
  1268. struct smsc911x_data *pdata = netdev_priv(dev);
  1269. u32 intsts = smsc911x_reg_read(pdata, INT_STS);
  1270. u32 inten = smsc911x_reg_read(pdata, INT_EN);
  1271. int serviced = IRQ_NONE;
  1272. u32 temp;
  1273. if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
  1274. temp = smsc911x_reg_read(pdata, INT_EN);
  1275. temp &= (~INT_EN_SW_INT_EN_);
  1276. smsc911x_reg_write(pdata, INT_EN, temp);
  1277. smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
  1278. pdata->software_irq_signal = 1;
  1279. smp_wmb();
  1280. serviced = IRQ_HANDLED;
  1281. }
  1282. if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
  1283. /* Called when there is a multicast update scheduled and
  1284. * it is now safe to complete the update */
  1285. SMSC_TRACE(pdata, intr, "RX Stop interrupt");
  1286. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
  1287. if (pdata->multicast_update_pending)
  1288. smsc911x_rx_multicast_update_workaround(pdata);
  1289. serviced = IRQ_HANDLED;
  1290. }
  1291. if (intsts & inten & INT_STS_TDFA_) {
  1292. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1293. temp |= FIFO_INT_TX_AVAIL_LEVEL_;
  1294. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1295. smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
  1296. netif_wake_queue(dev);
  1297. serviced = IRQ_HANDLED;
  1298. }
  1299. if (unlikely(intsts & inten & INT_STS_RXE_)) {
  1300. SMSC_TRACE(pdata, intr, "RX Error interrupt");
  1301. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
  1302. serviced = IRQ_HANDLED;
  1303. }
  1304. if (likely(intsts & inten & INT_STS_RSFL_)) {
  1305. if (likely(napi_schedule_prep(&pdata->napi))) {
  1306. /* Disable Rx interrupts */
  1307. temp = smsc911x_reg_read(pdata, INT_EN);
  1308. temp &= (~INT_EN_RSFL_EN_);
  1309. smsc911x_reg_write(pdata, INT_EN, temp);
  1310. /* Schedule a NAPI poll */
  1311. __napi_schedule(&pdata->napi);
  1312. } else {
  1313. SMSC_WARN(pdata, rx_err, "napi_schedule_prep failed");
  1314. }
  1315. serviced = IRQ_HANDLED;
  1316. }
  1317. return serviced;
  1318. }
  1319. static int smsc911x_open(struct net_device *dev)
  1320. {
  1321. struct smsc911x_data *pdata = netdev_priv(dev);
  1322. unsigned int timeout;
  1323. unsigned int temp;
  1324. unsigned int intcfg;
  1325. int retval;
  1326. int irq_flags;
  1327. /* find and start the given phy */
  1328. if (!dev->phydev) {
  1329. retval = smsc911x_mii_probe(dev);
  1330. if (retval < 0) {
  1331. SMSC_WARN(pdata, probe, "Error starting phy");
  1332. goto out;
  1333. }
  1334. }
  1335. /* Reset the LAN911x */
  1336. retval = smsc911x_soft_reset(pdata);
  1337. if (retval) {
  1338. SMSC_WARN(pdata, hw, "soft reset failed");
  1339. goto mii_free_out;
  1340. }
  1341. smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
  1342. smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
  1343. /* Increase the legal frame size of VLAN tagged frames to 1522 bytes */
  1344. spin_lock_irq(&pdata->mac_lock);
  1345. smsc911x_mac_write(pdata, VLAN1, ETH_P_8021Q);
  1346. spin_unlock_irq(&pdata->mac_lock);
  1347. /* Make sure EEPROM has finished loading before setting GPIO_CFG */
  1348. timeout = 50;
  1349. while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
  1350. --timeout) {
  1351. udelay(10);
  1352. }
  1353. if (unlikely(timeout == 0))
  1354. SMSC_WARN(pdata, ifup,
  1355. "Timed out waiting for EEPROM busy bit to clear");
  1356. smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
  1357. /* The soft reset above cleared the device's MAC address,
  1358. * restore it from local copy (set in probe) */
  1359. spin_lock_irq(&pdata->mac_lock);
  1360. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1361. spin_unlock_irq(&pdata->mac_lock);
  1362. /* Initialise irqs, but leave all sources disabled */
  1363. smsc911x_disable_irq_chip(dev);
  1364. /* Set interrupt deassertion to 100uS */
  1365. intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
  1366. if (pdata->config.irq_polarity) {
  1367. SMSC_TRACE(pdata, ifup, "irq polarity: active high");
  1368. intcfg |= INT_CFG_IRQ_POL_;
  1369. } else {
  1370. SMSC_TRACE(pdata, ifup, "irq polarity: active low");
  1371. }
  1372. if (pdata->config.irq_type) {
  1373. SMSC_TRACE(pdata, ifup, "irq type: push-pull");
  1374. intcfg |= INT_CFG_IRQ_TYPE_;
  1375. } else {
  1376. SMSC_TRACE(pdata, ifup, "irq type: open drain");
  1377. }
  1378. smsc911x_reg_write(pdata, INT_CFG, intcfg);
  1379. SMSC_TRACE(pdata, ifup, "Testing irq handler using IRQ %d", dev->irq);
  1380. pdata->software_irq_signal = 0;
  1381. smp_wmb();
  1382. irq_flags = irq_get_trigger_type(dev->irq);
  1383. retval = request_irq(dev->irq, smsc911x_irqhandler,
  1384. irq_flags | IRQF_SHARED, dev->name, dev);
  1385. if (retval) {
  1386. SMSC_WARN(pdata, probe,
  1387. "Unable to claim requested irq: %d", dev->irq);
  1388. goto mii_free_out;
  1389. }
  1390. temp = smsc911x_reg_read(pdata, INT_EN);
  1391. temp |= INT_EN_SW_INT_EN_;
  1392. smsc911x_reg_write(pdata, INT_EN, temp);
  1393. timeout = 1000;
  1394. while (timeout--) {
  1395. if (pdata->software_irq_signal)
  1396. break;
  1397. msleep(1);
  1398. }
  1399. if (!pdata->software_irq_signal) {
  1400. netdev_warn(dev, "ISR failed signaling test (IRQ %d)\n",
  1401. dev->irq);
  1402. retval = -ENODEV;
  1403. goto irq_stop_out;
  1404. }
  1405. SMSC_TRACE(pdata, ifup, "IRQ handler passed test using IRQ %d",
  1406. dev->irq);
  1407. netdev_info(dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
  1408. (unsigned long)pdata->ioaddr, dev->irq);
  1409. /* Reset the last known duplex and carrier */
  1410. pdata->last_duplex = -1;
  1411. pdata->last_carrier = -1;
  1412. /* Bring the PHY up */
  1413. phy_start(dev->phydev);
  1414. temp = smsc911x_reg_read(pdata, HW_CFG);
  1415. /* Preserve TX FIFO size and external PHY configuration */
  1416. temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
  1417. temp |= HW_CFG_SF_;
  1418. smsc911x_reg_write(pdata, HW_CFG, temp);
  1419. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1420. temp |= FIFO_INT_TX_AVAIL_LEVEL_;
  1421. temp &= ~(FIFO_INT_RX_STS_LEVEL_);
  1422. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1423. /* set RX Data offset to 2 bytes for alignment */
  1424. smsc911x_reg_write(pdata, RX_CFG, (NET_IP_ALIGN << 8));
  1425. /* enable NAPI polling before enabling RX interrupts */
  1426. napi_enable(&pdata->napi);
  1427. temp = smsc911x_reg_read(pdata, INT_EN);
  1428. temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
  1429. smsc911x_reg_write(pdata, INT_EN, temp);
  1430. spin_lock_irq(&pdata->mac_lock);
  1431. temp = smsc911x_mac_read(pdata, MAC_CR);
  1432. temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
  1433. smsc911x_mac_write(pdata, MAC_CR, temp);
  1434. spin_unlock_irq(&pdata->mac_lock);
  1435. smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
  1436. netif_start_queue(dev);
  1437. return 0;
  1438. irq_stop_out:
  1439. free_irq(dev->irq, dev);
  1440. mii_free_out:
  1441. phy_disconnect(dev->phydev);
  1442. dev->phydev = NULL;
  1443. out:
  1444. return retval;
  1445. }
  1446. /* Entry point for stopping the interface */
  1447. static int smsc911x_stop(struct net_device *dev)
  1448. {
  1449. struct smsc911x_data *pdata = netdev_priv(dev);
  1450. unsigned int temp;
  1451. /* Disable all device interrupts */
  1452. temp = smsc911x_reg_read(pdata, INT_CFG);
  1453. temp &= ~INT_CFG_IRQ_EN_;
  1454. smsc911x_reg_write(pdata, INT_CFG, temp);
  1455. /* Stop Tx and Rx polling */
  1456. netif_stop_queue(dev);
  1457. napi_disable(&pdata->napi);
  1458. /* At this point all Rx and Tx activity is stopped */
  1459. dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
  1460. smsc911x_tx_update_txcounters(dev);
  1461. free_irq(dev->irq, dev);
  1462. /* Bring the PHY down */
  1463. if (dev->phydev) {
  1464. phy_stop(dev->phydev);
  1465. phy_disconnect(dev->phydev);
  1466. dev->phydev = NULL;
  1467. }
  1468. netif_carrier_off(dev);
  1469. SMSC_TRACE(pdata, ifdown, "Interface stopped");
  1470. return 0;
  1471. }
  1472. /* Entry point for transmitting a packet */
  1473. static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1474. {
  1475. struct smsc911x_data *pdata = netdev_priv(dev);
  1476. unsigned int freespace;
  1477. unsigned int tx_cmd_a;
  1478. unsigned int tx_cmd_b;
  1479. unsigned int temp;
  1480. u32 wrsz;
  1481. ulong bufp;
  1482. freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
  1483. if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
  1484. SMSC_WARN(pdata, tx_err,
  1485. "Tx data fifo low, space available: %d", freespace);
  1486. /* Word alignment adjustment */
  1487. tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
  1488. tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  1489. tx_cmd_a |= (unsigned int)skb->len;
  1490. tx_cmd_b = ((unsigned int)skb->len) << 16;
  1491. tx_cmd_b |= (unsigned int)skb->len;
  1492. smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
  1493. smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
  1494. bufp = (ulong)skb->data & (~0x3);
  1495. wrsz = (u32)skb->len + 3;
  1496. wrsz += (u32)((ulong)skb->data & 0x3);
  1497. wrsz >>= 2;
  1498. pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
  1499. freespace -= (skb->len + 32);
  1500. skb_tx_timestamp(skb);
  1501. dev_consume_skb_any(skb);
  1502. if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
  1503. smsc911x_tx_update_txcounters(dev);
  1504. if (freespace < TX_FIFO_LOW_THRESHOLD) {
  1505. netif_stop_queue(dev);
  1506. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1507. temp &= 0x00FFFFFF;
  1508. temp |= 0x32000000;
  1509. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1510. }
  1511. return NETDEV_TX_OK;
  1512. }
  1513. /* Entry point for getting status counters */
  1514. static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
  1515. {
  1516. struct smsc911x_data *pdata = netdev_priv(dev);
  1517. smsc911x_tx_update_txcounters(dev);
  1518. dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
  1519. return &dev->stats;
  1520. }
  1521. /* Entry point for setting addressing modes */
  1522. static void smsc911x_set_multicast_list(struct net_device *dev)
  1523. {
  1524. struct smsc911x_data *pdata = netdev_priv(dev);
  1525. unsigned long flags;
  1526. if (dev->flags & IFF_PROMISC) {
  1527. /* Enabling promiscuous mode */
  1528. pdata->set_bits_mask = MAC_CR_PRMS_;
  1529. pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  1530. pdata->hashhi = 0;
  1531. pdata->hashlo = 0;
  1532. } else if (dev->flags & IFF_ALLMULTI) {
  1533. /* Enabling all multicast mode */
  1534. pdata->set_bits_mask = MAC_CR_MCPAS_;
  1535. pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  1536. pdata->hashhi = 0;
  1537. pdata->hashlo = 0;
  1538. } else if (!netdev_mc_empty(dev)) {
  1539. /* Enabling specific multicast addresses */
  1540. unsigned int hash_high = 0;
  1541. unsigned int hash_low = 0;
  1542. struct netdev_hw_addr *ha;
  1543. pdata->set_bits_mask = MAC_CR_HPFILT_;
  1544. pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  1545. netdev_for_each_mc_addr(ha, dev) {
  1546. unsigned int bitnum = smsc911x_hash(ha->addr);
  1547. unsigned int mask = 0x01 << (bitnum & 0x1F);
  1548. if (bitnum & 0x20)
  1549. hash_high |= mask;
  1550. else
  1551. hash_low |= mask;
  1552. }
  1553. pdata->hashhi = hash_high;
  1554. pdata->hashlo = hash_low;
  1555. } else {
  1556. /* Enabling local MAC address only */
  1557. pdata->set_bits_mask = 0;
  1558. pdata->clear_bits_mask =
  1559. (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  1560. pdata->hashhi = 0;
  1561. pdata->hashlo = 0;
  1562. }
  1563. spin_lock_irqsave(&pdata->mac_lock, flags);
  1564. if (pdata->generation <= 1) {
  1565. /* Older hardware revision - cannot change these flags while
  1566. * receiving data */
  1567. if (!pdata->multicast_update_pending) {
  1568. unsigned int temp;
  1569. SMSC_TRACE(pdata, hw, "scheduling mcast update");
  1570. pdata->multicast_update_pending = 1;
  1571. /* Request the hardware to stop, then perform the
  1572. * update when we get an RX_STOP interrupt */
  1573. temp = smsc911x_mac_read(pdata, MAC_CR);
  1574. temp &= ~(MAC_CR_RXEN_);
  1575. smsc911x_mac_write(pdata, MAC_CR, temp);
  1576. } else {
  1577. /* There is another update pending, this should now
  1578. * use the newer values */
  1579. }
  1580. } else {
  1581. /* Newer hardware revision - can write immediately */
  1582. smsc911x_rx_multicast_update(pdata);
  1583. }
  1584. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  1585. }
  1586. #ifdef CONFIG_NET_POLL_CONTROLLER
  1587. static void smsc911x_poll_controller(struct net_device *dev)
  1588. {
  1589. disable_irq(dev->irq);
  1590. smsc911x_irqhandler(0, dev);
  1591. enable_irq(dev->irq);
  1592. }
  1593. #endif /* CONFIG_NET_POLL_CONTROLLER */
  1594. static int smsc911x_set_mac_address(struct net_device *dev, void *p)
  1595. {
  1596. struct smsc911x_data *pdata = netdev_priv(dev);
  1597. struct sockaddr *addr = p;
  1598. /* On older hardware revisions we cannot change the mac address
  1599. * registers while receiving data. Newer devices can safely change
  1600. * this at any time. */
  1601. if (pdata->generation <= 1 && netif_running(dev))
  1602. return -EBUSY;
  1603. if (!is_valid_ether_addr(addr->sa_data))
  1604. return -EADDRNOTAVAIL;
  1605. memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
  1606. spin_lock_irq(&pdata->mac_lock);
  1607. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1608. spin_unlock_irq(&pdata->mac_lock);
  1609. netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
  1610. return 0;
  1611. }
  1612. /* Standard ioctls for mii-tool */
  1613. static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1614. {
  1615. if (!netif_running(dev) || !dev->phydev)
  1616. return -EINVAL;
  1617. return phy_mii_ioctl(dev->phydev, ifr, cmd);
  1618. }
  1619. static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
  1620. struct ethtool_drvinfo *info)
  1621. {
  1622. strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
  1623. strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
  1624. strlcpy(info->bus_info, dev_name(dev->dev.parent),
  1625. sizeof(info->bus_info));
  1626. }
  1627. static int smsc911x_ethtool_nwayreset(struct net_device *dev)
  1628. {
  1629. return phy_start_aneg(dev->phydev);
  1630. }
  1631. static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
  1632. {
  1633. struct smsc911x_data *pdata = netdev_priv(dev);
  1634. return pdata->msg_enable;
  1635. }
  1636. static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
  1637. {
  1638. struct smsc911x_data *pdata = netdev_priv(dev);
  1639. pdata->msg_enable = level;
  1640. }
  1641. static int smsc911x_ethtool_getregslen(struct net_device *dev)
  1642. {
  1643. return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
  1644. sizeof(u32);
  1645. }
  1646. static void
  1647. smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
  1648. void *buf)
  1649. {
  1650. struct smsc911x_data *pdata = netdev_priv(dev);
  1651. struct phy_device *phy_dev = dev->phydev;
  1652. unsigned long flags;
  1653. unsigned int i;
  1654. unsigned int j = 0;
  1655. u32 *data = buf;
  1656. regs->version = pdata->idrev;
  1657. for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
  1658. data[j++] = smsc911x_reg_read(pdata, i);
  1659. for (i = MAC_CR; i <= WUCSR; i++) {
  1660. spin_lock_irqsave(&pdata->mac_lock, flags);
  1661. data[j++] = smsc911x_mac_read(pdata, i);
  1662. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  1663. }
  1664. for (i = 0; i <= 31; i++)
  1665. data[j++] = smsc911x_mii_read(phy_dev->mdio.bus,
  1666. phy_dev->mdio.addr, i);
  1667. }
  1668. static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
  1669. {
  1670. unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
  1671. temp &= ~GPIO_CFG_EEPR_EN_;
  1672. smsc911x_reg_write(pdata, GPIO_CFG, temp);
  1673. msleep(1);
  1674. }
  1675. static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
  1676. {
  1677. int timeout = 100;
  1678. u32 e2cmd;
  1679. SMSC_TRACE(pdata, drv, "op 0x%08x", op);
  1680. if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
  1681. SMSC_WARN(pdata, drv, "Busy at start");
  1682. return -EBUSY;
  1683. }
  1684. e2cmd = op | E2P_CMD_EPC_BUSY_;
  1685. smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
  1686. do {
  1687. msleep(1);
  1688. e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
  1689. } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
  1690. if (!timeout) {
  1691. SMSC_TRACE(pdata, drv, "TIMED OUT");
  1692. return -EAGAIN;
  1693. }
  1694. if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
  1695. SMSC_TRACE(pdata, drv, "Error occurred during eeprom operation");
  1696. return -EINVAL;
  1697. }
  1698. return 0;
  1699. }
  1700. static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
  1701. u8 address, u8 *data)
  1702. {
  1703. u32 op = E2P_CMD_EPC_CMD_READ_ | address;
  1704. int ret;
  1705. SMSC_TRACE(pdata, drv, "address 0x%x", address);
  1706. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1707. if (!ret)
  1708. data[address] = smsc911x_reg_read(pdata, E2P_DATA);
  1709. return ret;
  1710. }
  1711. static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
  1712. u8 address, u8 data)
  1713. {
  1714. u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
  1715. u32 temp;
  1716. int ret;
  1717. SMSC_TRACE(pdata, drv, "address 0x%x, data 0x%x", address, data);
  1718. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1719. if (!ret) {
  1720. op = E2P_CMD_EPC_CMD_WRITE_ | address;
  1721. smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
  1722. /* Workaround for hardware read-after-write restriction */
  1723. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  1724. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1725. }
  1726. return ret;
  1727. }
  1728. static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
  1729. {
  1730. return SMSC911X_EEPROM_SIZE;
  1731. }
  1732. static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
  1733. struct ethtool_eeprom *eeprom, u8 *data)
  1734. {
  1735. struct smsc911x_data *pdata = netdev_priv(dev);
  1736. u8 eeprom_data[SMSC911X_EEPROM_SIZE];
  1737. int len;
  1738. int i;
  1739. smsc911x_eeprom_enable_access(pdata);
  1740. len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
  1741. for (i = 0; i < len; i++) {
  1742. int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
  1743. if (ret < 0) {
  1744. eeprom->len = 0;
  1745. return ret;
  1746. }
  1747. }
  1748. memcpy(data, &eeprom_data[eeprom->offset], len);
  1749. eeprom->len = len;
  1750. return 0;
  1751. }
  1752. static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
  1753. struct ethtool_eeprom *eeprom, u8 *data)
  1754. {
  1755. int ret;
  1756. struct smsc911x_data *pdata = netdev_priv(dev);
  1757. smsc911x_eeprom_enable_access(pdata);
  1758. smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
  1759. ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
  1760. smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
  1761. /* Single byte write, according to man page */
  1762. eeprom->len = 1;
  1763. return ret;
  1764. }
  1765. static const struct ethtool_ops smsc911x_ethtool_ops = {
  1766. .get_link = ethtool_op_get_link,
  1767. .get_drvinfo = smsc911x_ethtool_getdrvinfo,
  1768. .nway_reset = smsc911x_ethtool_nwayreset,
  1769. .get_msglevel = smsc911x_ethtool_getmsglevel,
  1770. .set_msglevel = smsc911x_ethtool_setmsglevel,
  1771. .get_regs_len = smsc911x_ethtool_getregslen,
  1772. .get_regs = smsc911x_ethtool_getregs,
  1773. .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
  1774. .get_eeprom = smsc911x_ethtool_get_eeprom,
  1775. .set_eeprom = smsc911x_ethtool_set_eeprom,
  1776. .get_ts_info = ethtool_op_get_ts_info,
  1777. .get_link_ksettings = phy_ethtool_get_link_ksettings,
  1778. .set_link_ksettings = phy_ethtool_set_link_ksettings,
  1779. };
  1780. static const struct net_device_ops smsc911x_netdev_ops = {
  1781. .ndo_open = smsc911x_open,
  1782. .ndo_stop = smsc911x_stop,
  1783. .ndo_start_xmit = smsc911x_hard_start_xmit,
  1784. .ndo_get_stats = smsc911x_get_stats,
  1785. .ndo_set_rx_mode = smsc911x_set_multicast_list,
  1786. .ndo_do_ioctl = smsc911x_do_ioctl,
  1787. .ndo_change_mtu = eth_change_mtu,
  1788. .ndo_validate_addr = eth_validate_addr,
  1789. .ndo_set_mac_address = smsc911x_set_mac_address,
  1790. #ifdef CONFIG_NET_POLL_CONTROLLER
  1791. .ndo_poll_controller = smsc911x_poll_controller,
  1792. #endif
  1793. };
  1794. /* copies the current mac address from hardware to dev->dev_addr */
  1795. static void smsc911x_read_mac_address(struct net_device *dev)
  1796. {
  1797. struct smsc911x_data *pdata = netdev_priv(dev);
  1798. u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
  1799. u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
  1800. dev->dev_addr[0] = (u8)(mac_low32);
  1801. dev->dev_addr[1] = (u8)(mac_low32 >> 8);
  1802. dev->dev_addr[2] = (u8)(mac_low32 >> 16);
  1803. dev->dev_addr[3] = (u8)(mac_low32 >> 24);
  1804. dev->dev_addr[4] = (u8)(mac_high16);
  1805. dev->dev_addr[5] = (u8)(mac_high16 >> 8);
  1806. }
  1807. /* Initializing private device structures, only called from probe */
  1808. static int smsc911x_init(struct net_device *dev)
  1809. {
  1810. struct smsc911x_data *pdata = netdev_priv(dev);
  1811. unsigned int byte_test, mask;
  1812. unsigned int to = 100;
  1813. SMSC_TRACE(pdata, probe, "Driver Parameters:");
  1814. SMSC_TRACE(pdata, probe, "LAN base: 0x%08lX",
  1815. (unsigned long)pdata->ioaddr);
  1816. SMSC_TRACE(pdata, probe, "IRQ: %d", dev->irq);
  1817. SMSC_TRACE(pdata, probe, "PHY will be autodetected.");
  1818. spin_lock_init(&pdata->dev_lock);
  1819. spin_lock_init(&pdata->mac_lock);
  1820. if (pdata->ioaddr == NULL) {
  1821. SMSC_WARN(pdata, probe, "pdata->ioaddr: 0x00000000");
  1822. return -ENODEV;
  1823. }
  1824. /*
  1825. * poll the READY bit in PMT_CTRL. Any other access to the device is
  1826. * forbidden while this bit isn't set. Try for 100ms
  1827. *
  1828. * Note that this test is done before the WORD_SWAP register is
  1829. * programmed. So in some configurations the READY bit is at 16 before
  1830. * WORD_SWAP is written to. This issue is worked around by waiting
  1831. * until either bit 0 or bit 16 gets set in PMT_CTRL.
  1832. *
  1833. * SMSC has confirmed that checking bit 16 (marked as reserved in
  1834. * the datasheet) is fine since these bits "will either never be set
  1835. * or can only go high after READY does (so also indicate the device
  1836. * is ready)".
  1837. */
  1838. mask = PMT_CTRL_READY_ | swahw32(PMT_CTRL_READY_);
  1839. while (!(smsc911x_reg_read(pdata, PMT_CTRL) & mask) && --to)
  1840. udelay(1000);
  1841. if (to == 0) {
  1842. netdev_err(dev, "Device not READY in 100ms aborting\n");
  1843. return -ENODEV;
  1844. }
  1845. /* Check byte ordering */
  1846. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1847. SMSC_TRACE(pdata, probe, "BYTE_TEST: 0x%08X", byte_test);
  1848. if (byte_test == 0x43218765) {
  1849. SMSC_TRACE(pdata, probe, "BYTE_TEST looks swapped, "
  1850. "applying WORD_SWAP");
  1851. smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
  1852. /* 1 dummy read of BYTE_TEST is needed after a write to
  1853. * WORD_SWAP before its contents are valid */
  1854. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1855. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1856. }
  1857. if (byte_test != 0x87654321) {
  1858. SMSC_WARN(pdata, drv, "BYTE_TEST: 0x%08X", byte_test);
  1859. if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
  1860. SMSC_WARN(pdata, probe,
  1861. "top 16 bits equal to bottom 16 bits");
  1862. SMSC_TRACE(pdata, probe,
  1863. "This may mean the chip is set "
  1864. "for 32 bit while the bus is reading 16 bit");
  1865. }
  1866. return -ENODEV;
  1867. }
  1868. /* Default generation to zero (all workarounds apply) */
  1869. pdata->generation = 0;
  1870. pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
  1871. switch (pdata->idrev & 0xFFFF0000) {
  1872. case 0x01180000:
  1873. case 0x01170000:
  1874. case 0x01160000:
  1875. case 0x01150000:
  1876. case 0x218A0000:
  1877. /* LAN911[5678] family */
  1878. pdata->generation = pdata->idrev & 0x0000FFFF;
  1879. break;
  1880. case 0x118A0000:
  1881. case 0x117A0000:
  1882. case 0x116A0000:
  1883. case 0x115A0000:
  1884. /* LAN921[5678] family */
  1885. pdata->generation = 3;
  1886. break;
  1887. case 0x92100000:
  1888. case 0x92110000:
  1889. case 0x92200000:
  1890. case 0x92210000:
  1891. /* LAN9210/LAN9211/LAN9220/LAN9221 */
  1892. pdata->generation = 4;
  1893. break;
  1894. default:
  1895. SMSC_WARN(pdata, probe, "LAN911x not identified, idrev: 0x%08X",
  1896. pdata->idrev);
  1897. return -ENODEV;
  1898. }
  1899. SMSC_TRACE(pdata, probe,
  1900. "LAN911x identified, idrev: 0x%08X, generation: %d",
  1901. pdata->idrev, pdata->generation);
  1902. if (pdata->generation == 0)
  1903. SMSC_WARN(pdata, probe,
  1904. "This driver is not intended for this chip revision");
  1905. /* workaround for platforms without an eeprom, where the mac address
  1906. * is stored elsewhere and set by the bootloader. This saves the
  1907. * mac address before resetting the device */
  1908. if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS) {
  1909. spin_lock_irq(&pdata->mac_lock);
  1910. smsc911x_read_mac_address(dev);
  1911. spin_unlock_irq(&pdata->mac_lock);
  1912. }
  1913. /* Reset the LAN911x */
  1914. if (smsc911x_phy_reset(pdata) || smsc911x_soft_reset(pdata))
  1915. return -ENODEV;
  1916. dev->flags |= IFF_MULTICAST;
  1917. netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
  1918. dev->netdev_ops = &smsc911x_netdev_ops;
  1919. dev->ethtool_ops = &smsc911x_ethtool_ops;
  1920. return 0;
  1921. }
  1922. static int smsc911x_drv_remove(struct platform_device *pdev)
  1923. {
  1924. struct net_device *dev;
  1925. struct smsc911x_data *pdata;
  1926. struct resource *res;
  1927. dev = platform_get_drvdata(pdev);
  1928. BUG_ON(!dev);
  1929. pdata = netdev_priv(dev);
  1930. BUG_ON(!pdata);
  1931. BUG_ON(!pdata->ioaddr);
  1932. SMSC_TRACE(pdata, ifdown, "Stopping driver");
  1933. unregister_netdev(dev);
  1934. mdiobus_unregister(pdata->mii_bus);
  1935. mdiobus_free(pdata->mii_bus);
  1936. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1937. "smsc911x-memory");
  1938. if (!res)
  1939. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1940. release_mem_region(res->start, resource_size(res));
  1941. iounmap(pdata->ioaddr);
  1942. (void)smsc911x_disable_resources(pdev);
  1943. smsc911x_free_resources(pdev);
  1944. free_netdev(dev);
  1945. pm_runtime_put(&pdev->dev);
  1946. pm_runtime_disable(&pdev->dev);
  1947. return 0;
  1948. }
  1949. /* standard register acces */
  1950. static const struct smsc911x_ops standard_smsc911x_ops = {
  1951. .reg_read = __smsc911x_reg_read,
  1952. .reg_write = __smsc911x_reg_write,
  1953. .rx_readfifo = smsc911x_rx_readfifo,
  1954. .tx_writefifo = smsc911x_tx_writefifo,
  1955. };
  1956. /* shifted register access */
  1957. static const struct smsc911x_ops shifted_smsc911x_ops = {
  1958. .reg_read = __smsc911x_reg_read_shift,
  1959. .reg_write = __smsc911x_reg_write_shift,
  1960. .rx_readfifo = smsc911x_rx_readfifo_shift,
  1961. .tx_writefifo = smsc911x_tx_writefifo_shift,
  1962. };
  1963. static int smsc911x_probe_config(struct smsc911x_platform_config *config,
  1964. struct device *dev)
  1965. {
  1966. int phy_interface;
  1967. u32 width = 0;
  1968. int err;
  1969. phy_interface = device_get_phy_mode(dev);
  1970. if (phy_interface < 0)
  1971. phy_interface = PHY_INTERFACE_MODE_NA;
  1972. config->phy_interface = phy_interface;
  1973. device_get_mac_address(dev, config->mac, ETH_ALEN);
  1974. err = device_property_read_u32(dev, "reg-io-width", &width);
  1975. if (err == -ENXIO)
  1976. return err;
  1977. if (!err && width == 4)
  1978. config->flags |= SMSC911X_USE_32BIT;
  1979. else
  1980. config->flags |= SMSC911X_USE_16BIT;
  1981. device_property_read_u32(dev, "reg-shift", &config->shift);
  1982. if (device_property_present(dev, "smsc,irq-active-high"))
  1983. config->irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH;
  1984. if (device_property_present(dev, "smsc,irq-push-pull"))
  1985. config->irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL;
  1986. if (device_property_present(dev, "smsc,force-internal-phy"))
  1987. config->flags |= SMSC911X_FORCE_INTERNAL_PHY;
  1988. if (device_property_present(dev, "smsc,force-external-phy"))
  1989. config->flags |= SMSC911X_FORCE_EXTERNAL_PHY;
  1990. if (device_property_present(dev, "smsc,save-mac-address"))
  1991. config->flags |= SMSC911X_SAVE_MAC_ADDRESS;
  1992. return 0;
  1993. }
  1994. static int smsc911x_drv_probe(struct platform_device *pdev)
  1995. {
  1996. struct net_device *dev;
  1997. struct smsc911x_data *pdata;
  1998. struct smsc911x_platform_config *config = dev_get_platdata(&pdev->dev);
  1999. struct resource *res;
  2000. int res_size, irq;
  2001. int retval;
  2002. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  2003. "smsc911x-memory");
  2004. if (!res)
  2005. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2006. if (!res) {
  2007. pr_warn("Could not allocate resource\n");
  2008. retval = -ENODEV;
  2009. goto out_0;
  2010. }
  2011. res_size = resource_size(res);
  2012. irq = platform_get_irq(pdev, 0);
  2013. if (irq == -EPROBE_DEFER) {
  2014. retval = -EPROBE_DEFER;
  2015. goto out_0;
  2016. } else if (irq <= 0) {
  2017. pr_warn("Could not allocate irq resource\n");
  2018. retval = -ENODEV;
  2019. goto out_0;
  2020. }
  2021. if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
  2022. retval = -EBUSY;
  2023. goto out_0;
  2024. }
  2025. dev = alloc_etherdev(sizeof(struct smsc911x_data));
  2026. if (!dev) {
  2027. retval = -ENOMEM;
  2028. goto out_release_io_1;
  2029. }
  2030. SET_NETDEV_DEV(dev, &pdev->dev);
  2031. pdata = netdev_priv(dev);
  2032. dev->irq = irq;
  2033. pdata->ioaddr = ioremap_nocache(res->start, res_size);
  2034. pdata->dev = dev;
  2035. pdata->msg_enable = ((1 << debug) - 1);
  2036. platform_set_drvdata(pdev, dev);
  2037. retval = smsc911x_request_resources(pdev);
  2038. if (retval)
  2039. goto out_request_resources_fail;
  2040. retval = smsc911x_enable_resources(pdev);
  2041. if (retval)
  2042. goto out_enable_resources_fail;
  2043. if (pdata->ioaddr == NULL) {
  2044. SMSC_WARN(pdata, probe, "Error smsc911x base address invalid");
  2045. retval = -ENOMEM;
  2046. goto out_disable_resources;
  2047. }
  2048. retval = smsc911x_probe_config(&pdata->config, &pdev->dev);
  2049. if (retval && config) {
  2050. /* copy config parameters across to pdata */
  2051. memcpy(&pdata->config, config, sizeof(pdata->config));
  2052. retval = 0;
  2053. }
  2054. if (retval) {
  2055. SMSC_WARN(pdata, probe, "Error smsc911x config not found");
  2056. goto out_disable_resources;
  2057. }
  2058. /* assume standard, non-shifted, access to HW registers */
  2059. pdata->ops = &standard_smsc911x_ops;
  2060. /* apply the right access if shifting is needed */
  2061. if (pdata->config.shift)
  2062. pdata->ops = &shifted_smsc911x_ops;
  2063. pm_runtime_enable(&pdev->dev);
  2064. pm_runtime_get_sync(&pdev->dev);
  2065. retval = smsc911x_init(dev);
  2066. if (retval < 0)
  2067. goto out_disable_resources;
  2068. netif_carrier_off(dev);
  2069. retval = smsc911x_mii_init(pdev, dev);
  2070. if (retval) {
  2071. SMSC_WARN(pdata, probe, "Error %i initialising mii", retval);
  2072. goto out_disable_resources;
  2073. }
  2074. retval = register_netdev(dev);
  2075. if (retval) {
  2076. SMSC_WARN(pdata, probe, "Error %i registering device", retval);
  2077. goto out_disable_resources;
  2078. } else {
  2079. SMSC_TRACE(pdata, probe,
  2080. "Network interface: \"%s\"", dev->name);
  2081. }
  2082. spin_lock_irq(&pdata->mac_lock);
  2083. /* Check if mac address has been specified when bringing interface up */
  2084. if (is_valid_ether_addr(dev->dev_addr)) {
  2085. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  2086. SMSC_TRACE(pdata, probe,
  2087. "MAC Address is specified by configuration");
  2088. } else if (is_valid_ether_addr(pdata->config.mac)) {
  2089. memcpy(dev->dev_addr, pdata->config.mac, ETH_ALEN);
  2090. SMSC_TRACE(pdata, probe,
  2091. "MAC Address specified by platform data");
  2092. } else {
  2093. /* Try reading mac address from device. if EEPROM is present
  2094. * it will already have been set */
  2095. smsc_get_mac(dev);
  2096. if (is_valid_ether_addr(dev->dev_addr)) {
  2097. /* eeprom values are valid so use them */
  2098. SMSC_TRACE(pdata, probe,
  2099. "Mac Address is read from LAN911x EEPROM");
  2100. } else {
  2101. /* eeprom values are invalid, generate random MAC */
  2102. eth_hw_addr_random(dev);
  2103. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  2104. SMSC_TRACE(pdata, probe,
  2105. "MAC Address is set to eth_random_addr");
  2106. }
  2107. }
  2108. spin_unlock_irq(&pdata->mac_lock);
  2109. netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
  2110. return 0;
  2111. out_disable_resources:
  2112. pm_runtime_put(&pdev->dev);
  2113. pm_runtime_disable(&pdev->dev);
  2114. (void)smsc911x_disable_resources(pdev);
  2115. out_enable_resources_fail:
  2116. smsc911x_free_resources(pdev);
  2117. out_request_resources_fail:
  2118. iounmap(pdata->ioaddr);
  2119. free_netdev(dev);
  2120. out_release_io_1:
  2121. release_mem_region(res->start, resource_size(res));
  2122. out_0:
  2123. return retval;
  2124. }
  2125. #ifdef CONFIG_PM
  2126. /* This implementation assumes the devices remains powered on its VDDVARIO
  2127. * pins during suspend. */
  2128. /* TODO: implement freeze/thaw callbacks for hibernation.*/
  2129. static int smsc911x_suspend(struct device *dev)
  2130. {
  2131. struct net_device *ndev = dev_get_drvdata(dev);
  2132. struct smsc911x_data *pdata = netdev_priv(ndev);
  2133. /* enable wake on LAN, energy detection and the external PME
  2134. * signal. */
  2135. smsc911x_reg_write(pdata, PMT_CTRL,
  2136. PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ |
  2137. PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_);
  2138. return 0;
  2139. }
  2140. static int smsc911x_resume(struct device *dev)
  2141. {
  2142. struct net_device *ndev = dev_get_drvdata(dev);
  2143. struct smsc911x_data *pdata = netdev_priv(ndev);
  2144. unsigned int to = 100;
  2145. /* Note 3.11 from the datasheet:
  2146. * "When the LAN9220 is in a power saving state, a write of any
  2147. * data to the BYTE_TEST register will wake-up the device."
  2148. */
  2149. smsc911x_reg_write(pdata, BYTE_TEST, 0);
  2150. /* poll the READY bit in PMT_CTRL. Any other access to the device is
  2151. * forbidden while this bit isn't set. Try for 100ms and return -EIO
  2152. * if it failed. */
  2153. while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
  2154. udelay(1000);
  2155. return (to == 0) ? -EIO : 0;
  2156. }
  2157. static const struct dev_pm_ops smsc911x_pm_ops = {
  2158. .suspend = smsc911x_suspend,
  2159. .resume = smsc911x_resume,
  2160. };
  2161. #define SMSC911X_PM_OPS (&smsc911x_pm_ops)
  2162. #else
  2163. #define SMSC911X_PM_OPS NULL
  2164. #endif
  2165. #ifdef CONFIG_OF
  2166. static const struct of_device_id smsc911x_dt_ids[] = {
  2167. { .compatible = "smsc,lan9115", },
  2168. { /* sentinel */ }
  2169. };
  2170. MODULE_DEVICE_TABLE(of, smsc911x_dt_ids);
  2171. #endif
  2172. static const struct acpi_device_id smsc911x_acpi_match[] = {
  2173. { "ARMH9118", 0 },
  2174. { }
  2175. };
  2176. MODULE_DEVICE_TABLE(acpi, smsc911x_acpi_match);
  2177. static struct platform_driver smsc911x_driver = {
  2178. .probe = smsc911x_drv_probe,
  2179. .remove = smsc911x_drv_remove,
  2180. .driver = {
  2181. .name = SMSC_CHIPNAME,
  2182. .pm = SMSC911X_PM_OPS,
  2183. .of_match_table = of_match_ptr(smsc911x_dt_ids),
  2184. .acpi_match_table = ACPI_PTR(smsc911x_acpi_match),
  2185. },
  2186. };
  2187. /* Entry point for loading the module */
  2188. static int __init smsc911x_init_module(void)
  2189. {
  2190. SMSC_INITIALIZE();
  2191. return platform_driver_register(&smsc911x_driver);
  2192. }
  2193. /* entry point for unloading the module */
  2194. static void __exit smsc911x_cleanup_module(void)
  2195. {
  2196. platform_driver_unregister(&smsc911x_driver);
  2197. }
  2198. module_init(smsc911x_init_module);
  2199. module_exit(smsc911x_cleanup_module);