dl2k.c 48 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896
  1. /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
  2. /*
  3. Copyright (c) 2001, 2002 by D-Link Corporation
  4. Written by Edward Peng.<edward_peng@dlink.com.tw>
  5. Created 03-May-2001, base on Linux' sundance.c.
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; either version 2 of the License, or
  9. (at your option) any later version.
  10. */
  11. #define DRV_NAME "DL2000/TC902x-based linux driver"
  12. #define DRV_VERSION "v1.19"
  13. #define DRV_RELDATE "2007/08/12"
  14. #include "dl2k.h"
  15. #include <linux/dma-mapping.h>
  16. #define dw32(reg, val) iowrite32(val, ioaddr + (reg))
  17. #define dw16(reg, val) iowrite16(val, ioaddr + (reg))
  18. #define dw8(reg, val) iowrite8(val, ioaddr + (reg))
  19. #define dr32(reg) ioread32(ioaddr + (reg))
  20. #define dr16(reg) ioread16(ioaddr + (reg))
  21. #define dr8(reg) ioread8(ioaddr + (reg))
  22. static char version[] =
  23. KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
  24. #define MAX_UNITS 8
  25. static int mtu[MAX_UNITS];
  26. static int vlan[MAX_UNITS];
  27. static int jumbo[MAX_UNITS];
  28. static char *media[MAX_UNITS];
  29. static int tx_flow=-1;
  30. static int rx_flow=-1;
  31. static int copy_thresh;
  32. static int rx_coalesce=10; /* Rx frame count each interrupt */
  33. static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
  34. static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
  35. MODULE_AUTHOR ("Edward Peng");
  36. MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
  37. MODULE_LICENSE("GPL");
  38. module_param_array(mtu, int, NULL, 0);
  39. module_param_array(media, charp, NULL, 0);
  40. module_param_array(vlan, int, NULL, 0);
  41. module_param_array(jumbo, int, NULL, 0);
  42. module_param(tx_flow, int, 0);
  43. module_param(rx_flow, int, 0);
  44. module_param(copy_thresh, int, 0);
  45. module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
  46. module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
  47. module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
  48. /* Enable the default interrupts */
  49. #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
  50. UpdateStats | LinkEvent)
  51. static void dl2k_enable_int(struct netdev_private *np)
  52. {
  53. void __iomem *ioaddr = np->ioaddr;
  54. dw16(IntEnable, DEFAULT_INTR);
  55. }
  56. static const int max_intrloop = 50;
  57. static const int multicast_filter_limit = 0x40;
  58. static int rio_open (struct net_device *dev);
  59. static void rio_timer (unsigned long data);
  60. static void rio_tx_timeout (struct net_device *dev);
  61. static netdev_tx_t start_xmit (struct sk_buff *skb, struct net_device *dev);
  62. static irqreturn_t rio_interrupt (int irq, void *dev_instance);
  63. static void rio_free_tx (struct net_device *dev, int irq);
  64. static void tx_error (struct net_device *dev, int tx_status);
  65. static int receive_packet (struct net_device *dev);
  66. static void rio_error (struct net_device *dev, int int_status);
  67. static int change_mtu (struct net_device *dev, int new_mtu);
  68. static void set_multicast (struct net_device *dev);
  69. static struct net_device_stats *get_stats (struct net_device *dev);
  70. static int clear_stats (struct net_device *dev);
  71. static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
  72. static int rio_close (struct net_device *dev);
  73. static int find_miiphy (struct net_device *dev);
  74. static int parse_eeprom (struct net_device *dev);
  75. static int read_eeprom (struct netdev_private *, int eep_addr);
  76. static int mii_wait_link (struct net_device *dev, int wait);
  77. static int mii_set_media (struct net_device *dev);
  78. static int mii_get_media (struct net_device *dev);
  79. static int mii_set_media_pcs (struct net_device *dev);
  80. static int mii_get_media_pcs (struct net_device *dev);
  81. static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
  82. static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
  83. u16 data);
  84. static const struct ethtool_ops ethtool_ops;
  85. static const struct net_device_ops netdev_ops = {
  86. .ndo_open = rio_open,
  87. .ndo_start_xmit = start_xmit,
  88. .ndo_stop = rio_close,
  89. .ndo_get_stats = get_stats,
  90. .ndo_validate_addr = eth_validate_addr,
  91. .ndo_set_mac_address = eth_mac_addr,
  92. .ndo_set_rx_mode = set_multicast,
  93. .ndo_do_ioctl = rio_ioctl,
  94. .ndo_tx_timeout = rio_tx_timeout,
  95. .ndo_change_mtu = change_mtu,
  96. };
  97. static int
  98. rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
  99. {
  100. struct net_device *dev;
  101. struct netdev_private *np;
  102. static int card_idx;
  103. int chip_idx = ent->driver_data;
  104. int err, irq;
  105. void __iomem *ioaddr;
  106. static int version_printed;
  107. void *ring_space;
  108. dma_addr_t ring_dma;
  109. if (!version_printed++)
  110. printk ("%s", version);
  111. err = pci_enable_device (pdev);
  112. if (err)
  113. return err;
  114. irq = pdev->irq;
  115. err = pci_request_regions (pdev, "dl2k");
  116. if (err)
  117. goto err_out_disable;
  118. pci_set_master (pdev);
  119. err = -ENOMEM;
  120. dev = alloc_etherdev (sizeof (*np));
  121. if (!dev)
  122. goto err_out_res;
  123. SET_NETDEV_DEV(dev, &pdev->dev);
  124. np = netdev_priv(dev);
  125. /* IO registers range. */
  126. ioaddr = pci_iomap(pdev, 0, 0);
  127. if (!ioaddr)
  128. goto err_out_dev;
  129. np->eeprom_addr = ioaddr;
  130. #ifdef MEM_MAPPING
  131. /* MM registers range. */
  132. ioaddr = pci_iomap(pdev, 1, 0);
  133. if (!ioaddr)
  134. goto err_out_iounmap;
  135. #endif
  136. np->ioaddr = ioaddr;
  137. np->chip_id = chip_idx;
  138. np->pdev = pdev;
  139. spin_lock_init (&np->tx_lock);
  140. spin_lock_init (&np->rx_lock);
  141. /* Parse manual configuration */
  142. np->an_enable = 1;
  143. np->tx_coalesce = 1;
  144. if (card_idx < MAX_UNITS) {
  145. if (media[card_idx] != NULL) {
  146. np->an_enable = 0;
  147. if (strcmp (media[card_idx], "auto") == 0 ||
  148. strcmp (media[card_idx], "autosense") == 0 ||
  149. strcmp (media[card_idx], "0") == 0 ) {
  150. np->an_enable = 2;
  151. } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
  152. strcmp (media[card_idx], "4") == 0) {
  153. np->speed = 100;
  154. np->full_duplex = 1;
  155. } else if (strcmp (media[card_idx], "100mbps_hd") == 0 ||
  156. strcmp (media[card_idx], "3") == 0) {
  157. np->speed = 100;
  158. np->full_duplex = 0;
  159. } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
  160. strcmp (media[card_idx], "2") == 0) {
  161. np->speed = 10;
  162. np->full_duplex = 1;
  163. } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
  164. strcmp (media[card_idx], "1") == 0) {
  165. np->speed = 10;
  166. np->full_duplex = 0;
  167. } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
  168. strcmp (media[card_idx], "6") == 0) {
  169. np->speed=1000;
  170. np->full_duplex=1;
  171. } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
  172. strcmp (media[card_idx], "5") == 0) {
  173. np->speed = 1000;
  174. np->full_duplex = 0;
  175. } else {
  176. np->an_enable = 1;
  177. }
  178. }
  179. if (jumbo[card_idx] != 0) {
  180. np->jumbo = 1;
  181. dev->mtu = MAX_JUMBO;
  182. } else {
  183. np->jumbo = 0;
  184. if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
  185. dev->mtu = mtu[card_idx];
  186. }
  187. np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
  188. vlan[card_idx] : 0;
  189. if (rx_coalesce > 0 && rx_timeout > 0) {
  190. np->rx_coalesce = rx_coalesce;
  191. np->rx_timeout = rx_timeout;
  192. np->coalesce = 1;
  193. }
  194. np->tx_flow = (tx_flow == 0) ? 0 : 1;
  195. np->rx_flow = (rx_flow == 0) ? 0 : 1;
  196. if (tx_coalesce < 1)
  197. tx_coalesce = 1;
  198. else if (tx_coalesce > TX_RING_SIZE-1)
  199. tx_coalesce = TX_RING_SIZE - 1;
  200. }
  201. dev->netdev_ops = &netdev_ops;
  202. dev->watchdog_timeo = TX_TIMEOUT;
  203. dev->ethtool_ops = &ethtool_ops;
  204. #if 0
  205. dev->features = NETIF_F_IP_CSUM;
  206. #endif
  207. pci_set_drvdata (pdev, dev);
  208. ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
  209. if (!ring_space)
  210. goto err_out_iounmap;
  211. np->tx_ring = ring_space;
  212. np->tx_ring_dma = ring_dma;
  213. ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
  214. if (!ring_space)
  215. goto err_out_unmap_tx;
  216. np->rx_ring = ring_space;
  217. np->rx_ring_dma = ring_dma;
  218. /* Parse eeprom data */
  219. parse_eeprom (dev);
  220. /* Find PHY address */
  221. err = find_miiphy (dev);
  222. if (err)
  223. goto err_out_unmap_rx;
  224. /* Fiber device? */
  225. np->phy_media = (dr16(ASICCtrl) & PhyMedia) ? 1 : 0;
  226. np->link_status = 0;
  227. /* Set media and reset PHY */
  228. if (np->phy_media) {
  229. /* default Auto-Negotiation for fiber deivices */
  230. if (np->an_enable == 2) {
  231. np->an_enable = 1;
  232. }
  233. } else {
  234. /* Auto-Negotiation is mandatory for 1000BASE-T,
  235. IEEE 802.3ab Annex 28D page 14 */
  236. if (np->speed == 1000)
  237. np->an_enable = 1;
  238. }
  239. err = register_netdev (dev);
  240. if (err)
  241. goto err_out_unmap_rx;
  242. card_idx++;
  243. printk (KERN_INFO "%s: %s, %pM, IRQ %d\n",
  244. dev->name, np->name, dev->dev_addr, irq);
  245. if (tx_coalesce > 1)
  246. printk(KERN_INFO "tx_coalesce:\t%d packets\n",
  247. tx_coalesce);
  248. if (np->coalesce)
  249. printk(KERN_INFO
  250. "rx_coalesce:\t%d packets\n"
  251. "rx_timeout: \t%d ns\n",
  252. np->rx_coalesce, np->rx_timeout*640);
  253. if (np->vlan)
  254. printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
  255. return 0;
  256. err_out_unmap_rx:
  257. pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
  258. err_out_unmap_tx:
  259. pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
  260. err_out_iounmap:
  261. #ifdef MEM_MAPPING
  262. pci_iounmap(pdev, np->ioaddr);
  263. #endif
  264. pci_iounmap(pdev, np->eeprom_addr);
  265. err_out_dev:
  266. free_netdev (dev);
  267. err_out_res:
  268. pci_release_regions (pdev);
  269. err_out_disable:
  270. pci_disable_device (pdev);
  271. return err;
  272. }
  273. static int
  274. find_miiphy (struct net_device *dev)
  275. {
  276. struct netdev_private *np = netdev_priv(dev);
  277. int i, phy_found = 0;
  278. np = netdev_priv(dev);
  279. np->phy_addr = 1;
  280. for (i = 31; i >= 0; i--) {
  281. int mii_status = mii_read (dev, i, 1);
  282. if (mii_status != 0xffff && mii_status != 0x0000) {
  283. np->phy_addr = i;
  284. phy_found++;
  285. }
  286. }
  287. if (!phy_found) {
  288. printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
  289. return -ENODEV;
  290. }
  291. return 0;
  292. }
  293. static int
  294. parse_eeprom (struct net_device *dev)
  295. {
  296. struct netdev_private *np = netdev_priv(dev);
  297. void __iomem *ioaddr = np->ioaddr;
  298. int i, j;
  299. u8 sromdata[256];
  300. u8 *psib;
  301. u32 crc;
  302. PSROM_t psrom = (PSROM_t) sromdata;
  303. int cid, next;
  304. for (i = 0; i < 128; i++)
  305. ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom(np, i));
  306. if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
  307. /* Check CRC */
  308. crc = ~ether_crc_le (256 - 4, sromdata);
  309. if (psrom->crc != cpu_to_le32(crc)) {
  310. printk (KERN_ERR "%s: EEPROM data CRC error.\n",
  311. dev->name);
  312. return -1;
  313. }
  314. }
  315. /* Set MAC address */
  316. for (i = 0; i < 6; i++)
  317. dev->dev_addr[i] = psrom->mac_addr[i];
  318. if (np->chip_id == CHIP_IP1000A) {
  319. np->led_mode = psrom->led_mode;
  320. return 0;
  321. }
  322. if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
  323. return 0;
  324. }
  325. /* Parse Software Information Block */
  326. i = 0x30;
  327. psib = (u8 *) sromdata;
  328. do {
  329. cid = psib[i++];
  330. next = psib[i++];
  331. if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
  332. printk (KERN_ERR "Cell data error\n");
  333. return -1;
  334. }
  335. switch (cid) {
  336. case 0: /* Format version */
  337. break;
  338. case 1: /* End of cell */
  339. return 0;
  340. case 2: /* Duplex Polarity */
  341. np->duplex_polarity = psib[i];
  342. dw8(PhyCtrl, dr8(PhyCtrl) | psib[i]);
  343. break;
  344. case 3: /* Wake Polarity */
  345. np->wake_polarity = psib[i];
  346. break;
  347. case 9: /* Adapter description */
  348. j = (next - i > 255) ? 255 : next - i;
  349. memcpy (np->name, &(psib[i]), j);
  350. break;
  351. case 4:
  352. case 5:
  353. case 6:
  354. case 7:
  355. case 8: /* Reversed */
  356. break;
  357. default: /* Unknown cell */
  358. return -1;
  359. }
  360. i = next;
  361. } while (1);
  362. return 0;
  363. }
  364. static void rio_set_led_mode(struct net_device *dev)
  365. {
  366. struct netdev_private *np = netdev_priv(dev);
  367. void __iomem *ioaddr = np->ioaddr;
  368. u32 mode;
  369. if (np->chip_id != CHIP_IP1000A)
  370. return;
  371. mode = dr32(ASICCtrl);
  372. mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
  373. if (np->led_mode & 0x01)
  374. mode |= IPG_AC_LED_MODE;
  375. if (np->led_mode & 0x02)
  376. mode |= IPG_AC_LED_MODE_BIT_1;
  377. if (np->led_mode & 0x08)
  378. mode |= IPG_AC_LED_SPEED;
  379. dw32(ASICCtrl, mode);
  380. }
  381. static inline dma_addr_t desc_to_dma(struct netdev_desc *desc)
  382. {
  383. return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48);
  384. }
  385. static void free_list(struct net_device *dev)
  386. {
  387. struct netdev_private *np = netdev_priv(dev);
  388. struct sk_buff *skb;
  389. int i;
  390. /* Free all the skbuffs in the queue. */
  391. for (i = 0; i < RX_RING_SIZE; i++) {
  392. skb = np->rx_skbuff[i];
  393. if (skb) {
  394. pci_unmap_single(np->pdev, desc_to_dma(&np->rx_ring[i]),
  395. skb->len, PCI_DMA_FROMDEVICE);
  396. dev_kfree_skb(skb);
  397. np->rx_skbuff[i] = NULL;
  398. }
  399. np->rx_ring[i].status = 0;
  400. np->rx_ring[i].fraginfo = 0;
  401. }
  402. for (i = 0; i < TX_RING_SIZE; i++) {
  403. skb = np->tx_skbuff[i];
  404. if (skb) {
  405. pci_unmap_single(np->pdev, desc_to_dma(&np->tx_ring[i]),
  406. skb->len, PCI_DMA_TODEVICE);
  407. dev_kfree_skb(skb);
  408. np->tx_skbuff[i] = NULL;
  409. }
  410. }
  411. }
  412. static void rio_reset_ring(struct netdev_private *np)
  413. {
  414. int i;
  415. np->cur_rx = 0;
  416. np->cur_tx = 0;
  417. np->old_rx = 0;
  418. np->old_tx = 0;
  419. for (i = 0; i < TX_RING_SIZE; i++)
  420. np->tx_ring[i].status = cpu_to_le64(TFDDone);
  421. for (i = 0; i < RX_RING_SIZE; i++)
  422. np->rx_ring[i].status = 0;
  423. }
  424. /* allocate and initialize Tx and Rx descriptors */
  425. static int alloc_list(struct net_device *dev)
  426. {
  427. struct netdev_private *np = netdev_priv(dev);
  428. int i;
  429. rio_reset_ring(np);
  430. np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
  431. /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
  432. for (i = 0; i < TX_RING_SIZE; i++) {
  433. np->tx_skbuff[i] = NULL;
  434. np->tx_ring[i].next_desc = cpu_to_le64(np->tx_ring_dma +
  435. ((i + 1) % TX_RING_SIZE) *
  436. sizeof(struct netdev_desc));
  437. }
  438. /* Initialize Rx descriptors & allocate buffers */
  439. for (i = 0; i < RX_RING_SIZE; i++) {
  440. /* Allocated fixed size of skbuff */
  441. struct sk_buff *skb;
  442. skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
  443. np->rx_skbuff[i] = skb;
  444. if (!skb) {
  445. free_list(dev);
  446. return -ENOMEM;
  447. }
  448. np->rx_ring[i].next_desc = cpu_to_le64(np->rx_ring_dma +
  449. ((i + 1) % RX_RING_SIZE) *
  450. sizeof(struct netdev_desc));
  451. /* Rubicon now supports 40 bits of addressing space. */
  452. np->rx_ring[i].fraginfo =
  453. cpu_to_le64(pci_map_single(
  454. np->pdev, skb->data, np->rx_buf_sz,
  455. PCI_DMA_FROMDEVICE));
  456. np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48);
  457. }
  458. return 0;
  459. }
  460. static void rio_hw_init(struct net_device *dev)
  461. {
  462. struct netdev_private *np = netdev_priv(dev);
  463. void __iomem *ioaddr = np->ioaddr;
  464. int i;
  465. u16 macctrl;
  466. /* Reset all logic functions */
  467. dw16(ASICCtrl + 2,
  468. GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset);
  469. mdelay(10);
  470. rio_set_led_mode(dev);
  471. /* DebugCtrl bit 4, 5, 9 must set */
  472. dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230);
  473. if (np->chip_id == CHIP_IP1000A &&
  474. (np->pdev->revision == 0x40 || np->pdev->revision == 0x41)) {
  475. /* PHY magic taken from ipg driver, undocumented registers */
  476. mii_write(dev, np->phy_addr, 31, 0x0001);
  477. mii_write(dev, np->phy_addr, 27, 0x01e0);
  478. mii_write(dev, np->phy_addr, 31, 0x0002);
  479. mii_write(dev, np->phy_addr, 27, 0xeb8e);
  480. mii_write(dev, np->phy_addr, 31, 0x0000);
  481. mii_write(dev, np->phy_addr, 30, 0x005e);
  482. /* advertise 1000BASE-T half & full duplex, prefer MASTER */
  483. mii_write(dev, np->phy_addr, MII_CTRL1000, 0x0700);
  484. }
  485. if (np->phy_media)
  486. mii_set_media_pcs(dev);
  487. else
  488. mii_set_media(dev);
  489. /* Jumbo frame */
  490. if (np->jumbo != 0)
  491. dw16(MaxFrameSize, MAX_JUMBO+14);
  492. /* Set RFDListPtr */
  493. dw32(RFDListPtr0, np->rx_ring_dma);
  494. dw32(RFDListPtr1, 0);
  495. /* Set station address */
  496. /* 16 or 32-bit access is required by TC9020 datasheet but 8-bit works
  497. * too. However, it doesn't work on IP1000A so we use 16-bit access.
  498. */
  499. for (i = 0; i < 3; i++)
  500. dw16(StationAddr0 + 2 * i,
  501. cpu_to_le16(((u16 *)dev->dev_addr)[i]));
  502. set_multicast (dev);
  503. if (np->coalesce) {
  504. dw32(RxDMAIntCtrl, np->rx_coalesce | np->rx_timeout << 16);
  505. }
  506. /* Set RIO to poll every N*320nsec. */
  507. dw8(RxDMAPollPeriod, 0x20);
  508. dw8(TxDMAPollPeriod, 0xff);
  509. dw8(RxDMABurstThresh, 0x30);
  510. dw8(RxDMAUrgentThresh, 0x30);
  511. dw32(RmonStatMask, 0x0007ffff);
  512. /* clear statistics */
  513. clear_stats (dev);
  514. /* VLAN supported */
  515. if (np->vlan) {
  516. /* priority field in RxDMAIntCtrl */
  517. dw32(RxDMAIntCtrl, dr32(RxDMAIntCtrl) | 0x7 << 10);
  518. /* VLANId */
  519. dw16(VLANId, np->vlan);
  520. /* Length/Type should be 0x8100 */
  521. dw32(VLANTag, 0x8100 << 16 | np->vlan);
  522. /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
  523. VLAN information tagged by TFC' VID, CFI fields. */
  524. dw32(MACCtrl, dr32(MACCtrl) | AutoVLANuntagging);
  525. }
  526. /* Start Tx/Rx */
  527. dw32(MACCtrl, dr32(MACCtrl) | StatsEnable | RxEnable | TxEnable);
  528. macctrl = 0;
  529. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  530. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  531. macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
  532. macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
  533. dw16(MACCtrl, macctrl);
  534. }
  535. static void rio_hw_stop(struct net_device *dev)
  536. {
  537. struct netdev_private *np = netdev_priv(dev);
  538. void __iomem *ioaddr = np->ioaddr;
  539. /* Disable interrupts */
  540. dw16(IntEnable, 0);
  541. /* Stop Tx and Rx logics */
  542. dw32(MACCtrl, TxDisable | RxDisable | StatsDisable);
  543. }
  544. static int rio_open(struct net_device *dev)
  545. {
  546. struct netdev_private *np = netdev_priv(dev);
  547. const int irq = np->pdev->irq;
  548. int i;
  549. i = alloc_list(dev);
  550. if (i)
  551. return i;
  552. rio_hw_init(dev);
  553. i = request_irq(irq, rio_interrupt, IRQF_SHARED, dev->name, dev);
  554. if (i) {
  555. rio_hw_stop(dev);
  556. free_list(dev);
  557. return i;
  558. }
  559. setup_timer(&np->timer, rio_timer, (unsigned long)dev);
  560. np->timer.expires = jiffies + 1 * HZ;
  561. add_timer(&np->timer);
  562. netif_start_queue (dev);
  563. dl2k_enable_int(np);
  564. return 0;
  565. }
  566. static void
  567. rio_timer (unsigned long data)
  568. {
  569. struct net_device *dev = (struct net_device *)data;
  570. struct netdev_private *np = netdev_priv(dev);
  571. unsigned int entry;
  572. int next_tick = 1*HZ;
  573. unsigned long flags;
  574. spin_lock_irqsave(&np->rx_lock, flags);
  575. /* Recover rx ring exhausted error */
  576. if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
  577. printk(KERN_INFO "Try to recover rx ring exhausted...\n");
  578. /* Re-allocate skbuffs to fill the descriptor ring */
  579. for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
  580. struct sk_buff *skb;
  581. entry = np->old_rx % RX_RING_SIZE;
  582. /* Dropped packets don't need to re-allocate */
  583. if (np->rx_skbuff[entry] == NULL) {
  584. skb = netdev_alloc_skb_ip_align(dev,
  585. np->rx_buf_sz);
  586. if (skb == NULL) {
  587. np->rx_ring[entry].fraginfo = 0;
  588. printk (KERN_INFO
  589. "%s: Still unable to re-allocate Rx skbuff.#%d\n",
  590. dev->name, entry);
  591. break;
  592. }
  593. np->rx_skbuff[entry] = skb;
  594. np->rx_ring[entry].fraginfo =
  595. cpu_to_le64 (pci_map_single
  596. (np->pdev, skb->data, np->rx_buf_sz,
  597. PCI_DMA_FROMDEVICE));
  598. }
  599. np->rx_ring[entry].fraginfo |=
  600. cpu_to_le64((u64)np->rx_buf_sz << 48);
  601. np->rx_ring[entry].status = 0;
  602. } /* end for */
  603. } /* end if */
  604. spin_unlock_irqrestore (&np->rx_lock, flags);
  605. np->timer.expires = jiffies + next_tick;
  606. add_timer(&np->timer);
  607. }
  608. static void
  609. rio_tx_timeout (struct net_device *dev)
  610. {
  611. struct netdev_private *np = netdev_priv(dev);
  612. void __iomem *ioaddr = np->ioaddr;
  613. printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
  614. dev->name, dr32(TxStatus));
  615. rio_free_tx(dev, 0);
  616. dev->if_port = 0;
  617. netif_trans_update(dev); /* prevent tx timeout */
  618. }
  619. static netdev_tx_t
  620. start_xmit (struct sk_buff *skb, struct net_device *dev)
  621. {
  622. struct netdev_private *np = netdev_priv(dev);
  623. void __iomem *ioaddr = np->ioaddr;
  624. struct netdev_desc *txdesc;
  625. unsigned entry;
  626. u64 tfc_vlan_tag = 0;
  627. if (np->link_status == 0) { /* Link Down */
  628. dev_kfree_skb(skb);
  629. return NETDEV_TX_OK;
  630. }
  631. entry = np->cur_tx % TX_RING_SIZE;
  632. np->tx_skbuff[entry] = skb;
  633. txdesc = &np->tx_ring[entry];
  634. #if 0
  635. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  636. txdesc->status |=
  637. cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
  638. IPChecksumEnable);
  639. }
  640. #endif
  641. if (np->vlan) {
  642. tfc_vlan_tag = VLANTagInsert |
  643. ((u64)np->vlan << 32) |
  644. ((u64)skb->priority << 45);
  645. }
  646. txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
  647. skb->len,
  648. PCI_DMA_TODEVICE));
  649. txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48);
  650. /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
  651. * Work around: Always use 1 descriptor in 10Mbps mode */
  652. if (entry % np->tx_coalesce == 0 || np->speed == 10)
  653. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  654. WordAlignDisable |
  655. TxDMAIndicate |
  656. (1 << FragCountShift));
  657. else
  658. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  659. WordAlignDisable |
  660. (1 << FragCountShift));
  661. /* TxDMAPollNow */
  662. dw32(DMACtrl, dr32(DMACtrl) | 0x00001000);
  663. /* Schedule ISR */
  664. dw32(CountDown, 10000);
  665. np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
  666. if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  667. < TX_QUEUE_LEN - 1 && np->speed != 10) {
  668. /* do nothing */
  669. } else if (!netif_queue_stopped(dev)) {
  670. netif_stop_queue (dev);
  671. }
  672. /* The first TFDListPtr */
  673. if (!dr32(TFDListPtr0)) {
  674. dw32(TFDListPtr0, np->tx_ring_dma +
  675. entry * sizeof (struct netdev_desc));
  676. dw32(TFDListPtr1, 0);
  677. }
  678. return NETDEV_TX_OK;
  679. }
  680. static irqreturn_t
  681. rio_interrupt (int irq, void *dev_instance)
  682. {
  683. struct net_device *dev = dev_instance;
  684. struct netdev_private *np = netdev_priv(dev);
  685. void __iomem *ioaddr = np->ioaddr;
  686. unsigned int_status;
  687. int cnt = max_intrloop;
  688. int handled = 0;
  689. while (1) {
  690. int_status = dr16(IntStatus);
  691. dw16(IntStatus, int_status);
  692. int_status &= DEFAULT_INTR;
  693. if (int_status == 0 || --cnt < 0)
  694. break;
  695. handled = 1;
  696. /* Processing received packets */
  697. if (int_status & RxDMAComplete)
  698. receive_packet (dev);
  699. /* TxDMAComplete interrupt */
  700. if ((int_status & (TxDMAComplete|IntRequested))) {
  701. int tx_status;
  702. tx_status = dr32(TxStatus);
  703. if (tx_status & 0x01)
  704. tx_error (dev, tx_status);
  705. /* Free used tx skbuffs */
  706. rio_free_tx (dev, 1);
  707. }
  708. /* Handle uncommon events */
  709. if (int_status &
  710. (HostError | LinkEvent | UpdateStats))
  711. rio_error (dev, int_status);
  712. }
  713. if (np->cur_tx != np->old_tx)
  714. dw32(CountDown, 100);
  715. return IRQ_RETVAL(handled);
  716. }
  717. static void
  718. rio_free_tx (struct net_device *dev, int irq)
  719. {
  720. struct netdev_private *np = netdev_priv(dev);
  721. int entry = np->old_tx % TX_RING_SIZE;
  722. int tx_use = 0;
  723. unsigned long flag = 0;
  724. if (irq)
  725. spin_lock(&np->tx_lock);
  726. else
  727. spin_lock_irqsave(&np->tx_lock, flag);
  728. /* Free used tx skbuffs */
  729. while (entry != np->cur_tx) {
  730. struct sk_buff *skb;
  731. if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone)))
  732. break;
  733. skb = np->tx_skbuff[entry];
  734. pci_unmap_single (np->pdev,
  735. desc_to_dma(&np->tx_ring[entry]),
  736. skb->len, PCI_DMA_TODEVICE);
  737. if (irq)
  738. dev_kfree_skb_irq (skb);
  739. else
  740. dev_kfree_skb (skb);
  741. np->tx_skbuff[entry] = NULL;
  742. entry = (entry + 1) % TX_RING_SIZE;
  743. tx_use++;
  744. }
  745. if (irq)
  746. spin_unlock(&np->tx_lock);
  747. else
  748. spin_unlock_irqrestore(&np->tx_lock, flag);
  749. np->old_tx = entry;
  750. /* If the ring is no longer full, clear tx_full and
  751. call netif_wake_queue() */
  752. if (netif_queue_stopped(dev) &&
  753. ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  754. < TX_QUEUE_LEN - 1 || np->speed == 10)) {
  755. netif_wake_queue (dev);
  756. }
  757. }
  758. static void
  759. tx_error (struct net_device *dev, int tx_status)
  760. {
  761. struct netdev_private *np = netdev_priv(dev);
  762. void __iomem *ioaddr = np->ioaddr;
  763. int frame_id;
  764. int i;
  765. frame_id = (tx_status & 0xffff0000);
  766. printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
  767. dev->name, tx_status, frame_id);
  768. np->stats.tx_errors++;
  769. /* Ttransmit Underrun */
  770. if (tx_status & 0x10) {
  771. np->stats.tx_fifo_errors++;
  772. dw16(TxStartThresh, dr16(TxStartThresh) + 0x10);
  773. /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
  774. dw16(ASICCtrl + 2,
  775. TxReset | DMAReset | FIFOReset | NetworkReset);
  776. /* Wait for ResetBusy bit clear */
  777. for (i = 50; i > 0; i--) {
  778. if (!(dr16(ASICCtrl + 2) & ResetBusy))
  779. break;
  780. mdelay (1);
  781. }
  782. rio_set_led_mode(dev);
  783. rio_free_tx (dev, 1);
  784. /* Reset TFDListPtr */
  785. dw32(TFDListPtr0, np->tx_ring_dma +
  786. np->old_tx * sizeof (struct netdev_desc));
  787. dw32(TFDListPtr1, 0);
  788. /* Let TxStartThresh stay default value */
  789. }
  790. /* Late Collision */
  791. if (tx_status & 0x04) {
  792. np->stats.tx_fifo_errors++;
  793. /* TxReset and clear FIFO */
  794. dw16(ASICCtrl + 2, TxReset | FIFOReset);
  795. /* Wait reset done */
  796. for (i = 50; i > 0; i--) {
  797. if (!(dr16(ASICCtrl + 2) & ResetBusy))
  798. break;
  799. mdelay (1);
  800. }
  801. rio_set_led_mode(dev);
  802. /* Let TxStartThresh stay default value */
  803. }
  804. /* Maximum Collisions */
  805. #ifdef ETHER_STATS
  806. if (tx_status & 0x08)
  807. np->stats.collisions16++;
  808. #else
  809. if (tx_status & 0x08)
  810. np->stats.collisions++;
  811. #endif
  812. /* Restart the Tx */
  813. dw32(MACCtrl, dr16(MACCtrl) | TxEnable);
  814. }
  815. static int
  816. receive_packet (struct net_device *dev)
  817. {
  818. struct netdev_private *np = netdev_priv(dev);
  819. int entry = np->cur_rx % RX_RING_SIZE;
  820. int cnt = 30;
  821. /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
  822. while (1) {
  823. struct netdev_desc *desc = &np->rx_ring[entry];
  824. int pkt_len;
  825. u64 frame_status;
  826. if (!(desc->status & cpu_to_le64(RFDDone)) ||
  827. !(desc->status & cpu_to_le64(FrameStart)) ||
  828. !(desc->status & cpu_to_le64(FrameEnd)))
  829. break;
  830. /* Chip omits the CRC. */
  831. frame_status = le64_to_cpu(desc->status);
  832. pkt_len = frame_status & 0xffff;
  833. if (--cnt < 0)
  834. break;
  835. /* Update rx error statistics, drop packet. */
  836. if (frame_status & RFS_Errors) {
  837. np->stats.rx_errors++;
  838. if (frame_status & (RxRuntFrame | RxLengthError))
  839. np->stats.rx_length_errors++;
  840. if (frame_status & RxFCSError)
  841. np->stats.rx_crc_errors++;
  842. if (frame_status & RxAlignmentError && np->speed != 1000)
  843. np->stats.rx_frame_errors++;
  844. if (frame_status & RxFIFOOverrun)
  845. np->stats.rx_fifo_errors++;
  846. } else {
  847. struct sk_buff *skb;
  848. /* Small skbuffs for short packets */
  849. if (pkt_len > copy_thresh) {
  850. pci_unmap_single (np->pdev,
  851. desc_to_dma(desc),
  852. np->rx_buf_sz,
  853. PCI_DMA_FROMDEVICE);
  854. skb_put (skb = np->rx_skbuff[entry], pkt_len);
  855. np->rx_skbuff[entry] = NULL;
  856. } else if ((skb = netdev_alloc_skb_ip_align(dev, pkt_len))) {
  857. pci_dma_sync_single_for_cpu(np->pdev,
  858. desc_to_dma(desc),
  859. np->rx_buf_sz,
  860. PCI_DMA_FROMDEVICE);
  861. skb_copy_to_linear_data (skb,
  862. np->rx_skbuff[entry]->data,
  863. pkt_len);
  864. skb_put (skb, pkt_len);
  865. pci_dma_sync_single_for_device(np->pdev,
  866. desc_to_dma(desc),
  867. np->rx_buf_sz,
  868. PCI_DMA_FROMDEVICE);
  869. }
  870. skb->protocol = eth_type_trans (skb, dev);
  871. #if 0
  872. /* Checksum done by hw, but csum value unavailable. */
  873. if (np->pdev->pci_rev_id >= 0x0c &&
  874. !(frame_status & (TCPError | UDPError | IPError))) {
  875. skb->ip_summed = CHECKSUM_UNNECESSARY;
  876. }
  877. #endif
  878. netif_rx (skb);
  879. }
  880. entry = (entry + 1) % RX_RING_SIZE;
  881. }
  882. spin_lock(&np->rx_lock);
  883. np->cur_rx = entry;
  884. /* Re-allocate skbuffs to fill the descriptor ring */
  885. entry = np->old_rx;
  886. while (entry != np->cur_rx) {
  887. struct sk_buff *skb;
  888. /* Dropped packets don't need to re-allocate */
  889. if (np->rx_skbuff[entry] == NULL) {
  890. skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
  891. if (skb == NULL) {
  892. np->rx_ring[entry].fraginfo = 0;
  893. printk (KERN_INFO
  894. "%s: receive_packet: "
  895. "Unable to re-allocate Rx skbuff.#%d\n",
  896. dev->name, entry);
  897. break;
  898. }
  899. np->rx_skbuff[entry] = skb;
  900. np->rx_ring[entry].fraginfo =
  901. cpu_to_le64 (pci_map_single
  902. (np->pdev, skb->data, np->rx_buf_sz,
  903. PCI_DMA_FROMDEVICE));
  904. }
  905. np->rx_ring[entry].fraginfo |=
  906. cpu_to_le64((u64)np->rx_buf_sz << 48);
  907. np->rx_ring[entry].status = 0;
  908. entry = (entry + 1) % RX_RING_SIZE;
  909. }
  910. np->old_rx = entry;
  911. spin_unlock(&np->rx_lock);
  912. return 0;
  913. }
  914. static void
  915. rio_error (struct net_device *dev, int int_status)
  916. {
  917. struct netdev_private *np = netdev_priv(dev);
  918. void __iomem *ioaddr = np->ioaddr;
  919. u16 macctrl;
  920. /* Link change event */
  921. if (int_status & LinkEvent) {
  922. if (mii_wait_link (dev, 10) == 0) {
  923. printk (KERN_INFO "%s: Link up\n", dev->name);
  924. if (np->phy_media)
  925. mii_get_media_pcs (dev);
  926. else
  927. mii_get_media (dev);
  928. if (np->speed == 1000)
  929. np->tx_coalesce = tx_coalesce;
  930. else
  931. np->tx_coalesce = 1;
  932. macctrl = 0;
  933. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  934. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  935. macctrl |= (np->tx_flow) ?
  936. TxFlowControlEnable : 0;
  937. macctrl |= (np->rx_flow) ?
  938. RxFlowControlEnable : 0;
  939. dw16(MACCtrl, macctrl);
  940. np->link_status = 1;
  941. netif_carrier_on(dev);
  942. } else {
  943. printk (KERN_INFO "%s: Link off\n", dev->name);
  944. np->link_status = 0;
  945. netif_carrier_off(dev);
  946. }
  947. }
  948. /* UpdateStats statistics registers */
  949. if (int_status & UpdateStats) {
  950. get_stats (dev);
  951. }
  952. /* PCI Error, a catastronphic error related to the bus interface
  953. occurs, set GlobalReset and HostReset to reset. */
  954. if (int_status & HostError) {
  955. printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
  956. dev->name, int_status);
  957. dw16(ASICCtrl + 2, GlobalReset | HostReset);
  958. mdelay (500);
  959. rio_set_led_mode(dev);
  960. }
  961. }
  962. static struct net_device_stats *
  963. get_stats (struct net_device *dev)
  964. {
  965. struct netdev_private *np = netdev_priv(dev);
  966. void __iomem *ioaddr = np->ioaddr;
  967. #ifdef MEM_MAPPING
  968. int i;
  969. #endif
  970. unsigned int stat_reg;
  971. /* All statistics registers need to be acknowledged,
  972. else statistic overflow could cause problems */
  973. np->stats.rx_packets += dr32(FramesRcvOk);
  974. np->stats.tx_packets += dr32(FramesXmtOk);
  975. np->stats.rx_bytes += dr32(OctetRcvOk);
  976. np->stats.tx_bytes += dr32(OctetXmtOk);
  977. np->stats.multicast = dr32(McstFramesRcvdOk);
  978. np->stats.collisions += dr32(SingleColFrames)
  979. + dr32(MultiColFrames);
  980. /* detailed tx errors */
  981. stat_reg = dr16(FramesAbortXSColls);
  982. np->stats.tx_aborted_errors += stat_reg;
  983. np->stats.tx_errors += stat_reg;
  984. stat_reg = dr16(CarrierSenseErrors);
  985. np->stats.tx_carrier_errors += stat_reg;
  986. np->stats.tx_errors += stat_reg;
  987. /* Clear all other statistic register. */
  988. dr32(McstOctetXmtOk);
  989. dr16(BcstFramesXmtdOk);
  990. dr32(McstFramesXmtdOk);
  991. dr16(BcstFramesRcvdOk);
  992. dr16(MacControlFramesRcvd);
  993. dr16(FrameTooLongErrors);
  994. dr16(InRangeLengthErrors);
  995. dr16(FramesCheckSeqErrors);
  996. dr16(FramesLostRxErrors);
  997. dr32(McstOctetXmtOk);
  998. dr32(BcstOctetXmtOk);
  999. dr32(McstFramesXmtdOk);
  1000. dr32(FramesWDeferredXmt);
  1001. dr32(LateCollisions);
  1002. dr16(BcstFramesXmtdOk);
  1003. dr16(MacControlFramesXmtd);
  1004. dr16(FramesWEXDeferal);
  1005. #ifdef MEM_MAPPING
  1006. for (i = 0x100; i <= 0x150; i += 4)
  1007. dr32(i);
  1008. #endif
  1009. dr16(TxJumboFrames);
  1010. dr16(RxJumboFrames);
  1011. dr16(TCPCheckSumErrors);
  1012. dr16(UDPCheckSumErrors);
  1013. dr16(IPCheckSumErrors);
  1014. return &np->stats;
  1015. }
  1016. static int
  1017. clear_stats (struct net_device *dev)
  1018. {
  1019. struct netdev_private *np = netdev_priv(dev);
  1020. void __iomem *ioaddr = np->ioaddr;
  1021. #ifdef MEM_MAPPING
  1022. int i;
  1023. #endif
  1024. /* All statistics registers need to be acknowledged,
  1025. else statistic overflow could cause problems */
  1026. dr32(FramesRcvOk);
  1027. dr32(FramesXmtOk);
  1028. dr32(OctetRcvOk);
  1029. dr32(OctetXmtOk);
  1030. dr32(McstFramesRcvdOk);
  1031. dr32(SingleColFrames);
  1032. dr32(MultiColFrames);
  1033. dr32(LateCollisions);
  1034. /* detailed rx errors */
  1035. dr16(FrameTooLongErrors);
  1036. dr16(InRangeLengthErrors);
  1037. dr16(FramesCheckSeqErrors);
  1038. dr16(FramesLostRxErrors);
  1039. /* detailed tx errors */
  1040. dr16(FramesAbortXSColls);
  1041. dr16(CarrierSenseErrors);
  1042. /* Clear all other statistic register. */
  1043. dr32(McstOctetXmtOk);
  1044. dr16(BcstFramesXmtdOk);
  1045. dr32(McstFramesXmtdOk);
  1046. dr16(BcstFramesRcvdOk);
  1047. dr16(MacControlFramesRcvd);
  1048. dr32(McstOctetXmtOk);
  1049. dr32(BcstOctetXmtOk);
  1050. dr32(McstFramesXmtdOk);
  1051. dr32(FramesWDeferredXmt);
  1052. dr16(BcstFramesXmtdOk);
  1053. dr16(MacControlFramesXmtd);
  1054. dr16(FramesWEXDeferal);
  1055. #ifdef MEM_MAPPING
  1056. for (i = 0x100; i <= 0x150; i += 4)
  1057. dr32(i);
  1058. #endif
  1059. dr16(TxJumboFrames);
  1060. dr16(RxJumboFrames);
  1061. dr16(TCPCheckSumErrors);
  1062. dr16(UDPCheckSumErrors);
  1063. dr16(IPCheckSumErrors);
  1064. return 0;
  1065. }
  1066. static int
  1067. change_mtu (struct net_device *dev, int new_mtu)
  1068. {
  1069. struct netdev_private *np = netdev_priv(dev);
  1070. int max = (np->jumbo) ? MAX_JUMBO : 1536;
  1071. if ((new_mtu < 68) || (new_mtu > max)) {
  1072. return -EINVAL;
  1073. }
  1074. dev->mtu = new_mtu;
  1075. return 0;
  1076. }
  1077. static void
  1078. set_multicast (struct net_device *dev)
  1079. {
  1080. struct netdev_private *np = netdev_priv(dev);
  1081. void __iomem *ioaddr = np->ioaddr;
  1082. u32 hash_table[2];
  1083. u16 rx_mode = 0;
  1084. hash_table[0] = hash_table[1] = 0;
  1085. /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
  1086. hash_table[1] |= 0x02000000;
  1087. if (dev->flags & IFF_PROMISC) {
  1088. /* Receive all frames promiscuously. */
  1089. rx_mode = ReceiveAllFrames;
  1090. } else if ((dev->flags & IFF_ALLMULTI) ||
  1091. (netdev_mc_count(dev) > multicast_filter_limit)) {
  1092. /* Receive broadcast and multicast frames */
  1093. rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
  1094. } else if (!netdev_mc_empty(dev)) {
  1095. struct netdev_hw_addr *ha;
  1096. /* Receive broadcast frames and multicast frames filtering
  1097. by Hashtable */
  1098. rx_mode =
  1099. ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
  1100. netdev_for_each_mc_addr(ha, dev) {
  1101. int bit, index = 0;
  1102. int crc = ether_crc_le(ETH_ALEN, ha->addr);
  1103. /* The inverted high significant 6 bits of CRC are
  1104. used as an index to hashtable */
  1105. for (bit = 0; bit < 6; bit++)
  1106. if (crc & (1 << (31 - bit)))
  1107. index |= (1 << bit);
  1108. hash_table[index / 32] |= (1 << (index % 32));
  1109. }
  1110. } else {
  1111. rx_mode = ReceiveBroadcast | ReceiveUnicast;
  1112. }
  1113. if (np->vlan) {
  1114. /* ReceiveVLANMatch field in ReceiveMode */
  1115. rx_mode |= ReceiveVLANMatch;
  1116. }
  1117. dw32(HashTable0, hash_table[0]);
  1118. dw32(HashTable1, hash_table[1]);
  1119. dw16(ReceiveMode, rx_mode);
  1120. }
  1121. static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  1122. {
  1123. struct netdev_private *np = netdev_priv(dev);
  1124. strlcpy(info->driver, "dl2k", sizeof(info->driver));
  1125. strlcpy(info->version, DRV_VERSION, sizeof(info->version));
  1126. strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
  1127. }
  1128. static int rio_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1129. {
  1130. struct netdev_private *np = netdev_priv(dev);
  1131. if (np->phy_media) {
  1132. /* fiber device */
  1133. cmd->supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
  1134. cmd->advertising= ADVERTISED_Autoneg | ADVERTISED_FIBRE;
  1135. cmd->port = PORT_FIBRE;
  1136. cmd->transceiver = XCVR_INTERNAL;
  1137. } else {
  1138. /* copper device */
  1139. cmd->supported = SUPPORTED_10baseT_Half |
  1140. SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
  1141. | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
  1142. SUPPORTED_Autoneg | SUPPORTED_MII;
  1143. cmd->advertising = ADVERTISED_10baseT_Half |
  1144. ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
  1145. ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full|
  1146. ADVERTISED_Autoneg | ADVERTISED_MII;
  1147. cmd->port = PORT_MII;
  1148. cmd->transceiver = XCVR_INTERNAL;
  1149. }
  1150. if ( np->link_status ) {
  1151. ethtool_cmd_speed_set(cmd, np->speed);
  1152. cmd->duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
  1153. } else {
  1154. ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
  1155. cmd->duplex = DUPLEX_UNKNOWN;
  1156. }
  1157. if ( np->an_enable)
  1158. cmd->autoneg = AUTONEG_ENABLE;
  1159. else
  1160. cmd->autoneg = AUTONEG_DISABLE;
  1161. cmd->phy_address = np->phy_addr;
  1162. return 0;
  1163. }
  1164. static int rio_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1165. {
  1166. struct netdev_private *np = netdev_priv(dev);
  1167. netif_carrier_off(dev);
  1168. if (cmd->autoneg == AUTONEG_ENABLE) {
  1169. if (np->an_enable)
  1170. return 0;
  1171. else {
  1172. np->an_enable = 1;
  1173. mii_set_media(dev);
  1174. return 0;
  1175. }
  1176. } else {
  1177. np->an_enable = 0;
  1178. if (np->speed == 1000) {
  1179. ethtool_cmd_speed_set(cmd, SPEED_100);
  1180. cmd->duplex = DUPLEX_FULL;
  1181. printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
  1182. }
  1183. switch (ethtool_cmd_speed(cmd)) {
  1184. case SPEED_10:
  1185. np->speed = 10;
  1186. np->full_duplex = (cmd->duplex == DUPLEX_FULL);
  1187. break;
  1188. case SPEED_100:
  1189. np->speed = 100;
  1190. np->full_duplex = (cmd->duplex == DUPLEX_FULL);
  1191. break;
  1192. case SPEED_1000: /* not supported */
  1193. default:
  1194. return -EINVAL;
  1195. }
  1196. mii_set_media(dev);
  1197. }
  1198. return 0;
  1199. }
  1200. static u32 rio_get_link(struct net_device *dev)
  1201. {
  1202. struct netdev_private *np = netdev_priv(dev);
  1203. return np->link_status;
  1204. }
  1205. static const struct ethtool_ops ethtool_ops = {
  1206. .get_drvinfo = rio_get_drvinfo,
  1207. .get_settings = rio_get_settings,
  1208. .set_settings = rio_set_settings,
  1209. .get_link = rio_get_link,
  1210. };
  1211. static int
  1212. rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
  1213. {
  1214. int phy_addr;
  1215. struct netdev_private *np = netdev_priv(dev);
  1216. struct mii_ioctl_data *miidata = if_mii(rq);
  1217. phy_addr = np->phy_addr;
  1218. switch (cmd) {
  1219. case SIOCGMIIPHY:
  1220. miidata->phy_id = phy_addr;
  1221. break;
  1222. case SIOCGMIIREG:
  1223. miidata->val_out = mii_read (dev, phy_addr, miidata->reg_num);
  1224. break;
  1225. case SIOCSMIIREG:
  1226. if (!capable(CAP_NET_ADMIN))
  1227. return -EPERM;
  1228. mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in);
  1229. break;
  1230. default:
  1231. return -EOPNOTSUPP;
  1232. }
  1233. return 0;
  1234. }
  1235. #define EEP_READ 0x0200
  1236. #define EEP_BUSY 0x8000
  1237. /* Read the EEPROM word */
  1238. /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
  1239. static int read_eeprom(struct netdev_private *np, int eep_addr)
  1240. {
  1241. void __iomem *ioaddr = np->eeprom_addr;
  1242. int i = 1000;
  1243. dw16(EepromCtrl, EEP_READ | (eep_addr & 0xff));
  1244. while (i-- > 0) {
  1245. if (!(dr16(EepromCtrl) & EEP_BUSY))
  1246. return dr16(EepromData);
  1247. }
  1248. return 0;
  1249. }
  1250. enum phy_ctrl_bits {
  1251. MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
  1252. MII_DUPLEX = 0x08,
  1253. };
  1254. #define mii_delay() dr8(PhyCtrl)
  1255. static void
  1256. mii_sendbit (struct net_device *dev, u32 data)
  1257. {
  1258. struct netdev_private *np = netdev_priv(dev);
  1259. void __iomem *ioaddr = np->ioaddr;
  1260. data = ((data) ? MII_DATA1 : 0) | (dr8(PhyCtrl) & 0xf8) | MII_WRITE;
  1261. dw8(PhyCtrl, data);
  1262. mii_delay ();
  1263. dw8(PhyCtrl, data | MII_CLK);
  1264. mii_delay ();
  1265. }
  1266. static int
  1267. mii_getbit (struct net_device *dev)
  1268. {
  1269. struct netdev_private *np = netdev_priv(dev);
  1270. void __iomem *ioaddr = np->ioaddr;
  1271. u8 data;
  1272. data = (dr8(PhyCtrl) & 0xf8) | MII_READ;
  1273. dw8(PhyCtrl, data);
  1274. mii_delay ();
  1275. dw8(PhyCtrl, data | MII_CLK);
  1276. mii_delay ();
  1277. return (dr8(PhyCtrl) >> 1) & 1;
  1278. }
  1279. static void
  1280. mii_send_bits (struct net_device *dev, u32 data, int len)
  1281. {
  1282. int i;
  1283. for (i = len - 1; i >= 0; i--) {
  1284. mii_sendbit (dev, data & (1 << i));
  1285. }
  1286. }
  1287. static int
  1288. mii_read (struct net_device *dev, int phy_addr, int reg_num)
  1289. {
  1290. u32 cmd;
  1291. int i;
  1292. u32 retval = 0;
  1293. /* Preamble */
  1294. mii_send_bits (dev, 0xffffffff, 32);
  1295. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1296. /* ST,OP = 0110'b for read operation */
  1297. cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
  1298. mii_send_bits (dev, cmd, 14);
  1299. /* Turnaround */
  1300. if (mii_getbit (dev))
  1301. goto err_out;
  1302. /* Read data */
  1303. for (i = 0; i < 16; i++) {
  1304. retval |= mii_getbit (dev);
  1305. retval <<= 1;
  1306. }
  1307. /* End cycle */
  1308. mii_getbit (dev);
  1309. return (retval >> 1) & 0xffff;
  1310. err_out:
  1311. return 0;
  1312. }
  1313. static int
  1314. mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
  1315. {
  1316. u32 cmd;
  1317. /* Preamble */
  1318. mii_send_bits (dev, 0xffffffff, 32);
  1319. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1320. /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
  1321. cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
  1322. mii_send_bits (dev, cmd, 32);
  1323. /* End cycle */
  1324. mii_getbit (dev);
  1325. return 0;
  1326. }
  1327. static int
  1328. mii_wait_link (struct net_device *dev, int wait)
  1329. {
  1330. __u16 bmsr;
  1331. int phy_addr;
  1332. struct netdev_private *np;
  1333. np = netdev_priv(dev);
  1334. phy_addr = np->phy_addr;
  1335. do {
  1336. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1337. if (bmsr & BMSR_LSTATUS)
  1338. return 0;
  1339. mdelay (1);
  1340. } while (--wait > 0);
  1341. return -1;
  1342. }
  1343. static int
  1344. mii_get_media (struct net_device *dev)
  1345. {
  1346. __u16 negotiate;
  1347. __u16 bmsr;
  1348. __u16 mscr;
  1349. __u16 mssr;
  1350. int phy_addr;
  1351. struct netdev_private *np;
  1352. np = netdev_priv(dev);
  1353. phy_addr = np->phy_addr;
  1354. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1355. if (np->an_enable) {
  1356. if (!(bmsr & BMSR_ANEGCOMPLETE)) {
  1357. /* Auto-Negotiation not completed */
  1358. return -1;
  1359. }
  1360. negotiate = mii_read (dev, phy_addr, MII_ADVERTISE) &
  1361. mii_read (dev, phy_addr, MII_LPA);
  1362. mscr = mii_read (dev, phy_addr, MII_CTRL1000);
  1363. mssr = mii_read (dev, phy_addr, MII_STAT1000);
  1364. if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) {
  1365. np->speed = 1000;
  1366. np->full_duplex = 1;
  1367. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1368. } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) {
  1369. np->speed = 1000;
  1370. np->full_duplex = 0;
  1371. printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
  1372. } else if (negotiate & ADVERTISE_100FULL) {
  1373. np->speed = 100;
  1374. np->full_duplex = 1;
  1375. printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
  1376. } else if (negotiate & ADVERTISE_100HALF) {
  1377. np->speed = 100;
  1378. np->full_duplex = 0;
  1379. printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
  1380. } else if (negotiate & ADVERTISE_10FULL) {
  1381. np->speed = 10;
  1382. np->full_duplex = 1;
  1383. printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
  1384. } else if (negotiate & ADVERTISE_10HALF) {
  1385. np->speed = 10;
  1386. np->full_duplex = 0;
  1387. printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
  1388. }
  1389. if (negotiate & ADVERTISE_PAUSE_CAP) {
  1390. np->tx_flow &= 1;
  1391. np->rx_flow &= 1;
  1392. } else if (negotiate & ADVERTISE_PAUSE_ASYM) {
  1393. np->tx_flow = 0;
  1394. np->rx_flow &= 1;
  1395. }
  1396. /* else tx_flow, rx_flow = user select */
  1397. } else {
  1398. __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
  1399. switch (bmcr & (BMCR_SPEED100 | BMCR_SPEED1000)) {
  1400. case BMCR_SPEED1000:
  1401. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1402. break;
  1403. case BMCR_SPEED100:
  1404. printk (KERN_INFO "Operating at 100 Mbps, ");
  1405. break;
  1406. case 0:
  1407. printk (KERN_INFO "Operating at 10 Mbps, ");
  1408. }
  1409. if (bmcr & BMCR_FULLDPLX) {
  1410. printk (KERN_CONT "Full duplex\n");
  1411. } else {
  1412. printk (KERN_CONT "Half duplex\n");
  1413. }
  1414. }
  1415. if (np->tx_flow)
  1416. printk(KERN_INFO "Enable Tx Flow Control\n");
  1417. else
  1418. printk(KERN_INFO "Disable Tx Flow Control\n");
  1419. if (np->rx_flow)
  1420. printk(KERN_INFO "Enable Rx Flow Control\n");
  1421. else
  1422. printk(KERN_INFO "Disable Rx Flow Control\n");
  1423. return 0;
  1424. }
  1425. static int
  1426. mii_set_media (struct net_device *dev)
  1427. {
  1428. __u16 pscr;
  1429. __u16 bmcr;
  1430. __u16 bmsr;
  1431. __u16 anar;
  1432. int phy_addr;
  1433. struct netdev_private *np;
  1434. np = netdev_priv(dev);
  1435. phy_addr = np->phy_addr;
  1436. /* Does user set speed? */
  1437. if (np->an_enable) {
  1438. /* Advertise capabilities */
  1439. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1440. anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
  1441. ~(ADVERTISE_100FULL | ADVERTISE_10FULL |
  1442. ADVERTISE_100HALF | ADVERTISE_10HALF |
  1443. ADVERTISE_100BASE4);
  1444. if (bmsr & BMSR_100FULL)
  1445. anar |= ADVERTISE_100FULL;
  1446. if (bmsr & BMSR_100HALF)
  1447. anar |= ADVERTISE_100HALF;
  1448. if (bmsr & BMSR_100BASE4)
  1449. anar |= ADVERTISE_100BASE4;
  1450. if (bmsr & BMSR_10FULL)
  1451. anar |= ADVERTISE_10FULL;
  1452. if (bmsr & BMSR_10HALF)
  1453. anar |= ADVERTISE_10HALF;
  1454. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1455. mii_write (dev, phy_addr, MII_ADVERTISE, anar);
  1456. /* Enable Auto crossover */
  1457. pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
  1458. pscr |= 3 << 5; /* 11'b */
  1459. mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
  1460. /* Soft reset PHY */
  1461. mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
  1462. bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
  1463. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1464. mdelay(1);
  1465. } else {
  1466. /* Force speed setting */
  1467. /* 1) Disable Auto crossover */
  1468. pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
  1469. pscr &= ~(3 << 5);
  1470. mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
  1471. /* 2) PHY Reset */
  1472. bmcr = mii_read (dev, phy_addr, MII_BMCR);
  1473. bmcr |= BMCR_RESET;
  1474. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1475. /* 3) Power Down */
  1476. bmcr = 0x1940; /* must be 0x1940 */
  1477. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1478. mdelay (100); /* wait a certain time */
  1479. /* 4) Advertise nothing */
  1480. mii_write (dev, phy_addr, MII_ADVERTISE, 0);
  1481. /* 5) Set media and Power Up */
  1482. bmcr = BMCR_PDOWN;
  1483. if (np->speed == 100) {
  1484. bmcr |= BMCR_SPEED100;
  1485. printk (KERN_INFO "Manual 100 Mbps, ");
  1486. } else if (np->speed == 10) {
  1487. printk (KERN_INFO "Manual 10 Mbps, ");
  1488. }
  1489. if (np->full_duplex) {
  1490. bmcr |= BMCR_FULLDPLX;
  1491. printk (KERN_CONT "Full duplex\n");
  1492. } else {
  1493. printk (KERN_CONT "Half duplex\n");
  1494. }
  1495. #if 0
  1496. /* Set 1000BaseT Master/Slave setting */
  1497. mscr = mii_read (dev, phy_addr, MII_CTRL1000);
  1498. mscr |= MII_MSCR_CFG_ENABLE;
  1499. mscr &= ~MII_MSCR_CFG_VALUE = 0;
  1500. #endif
  1501. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1502. mdelay(10);
  1503. }
  1504. return 0;
  1505. }
  1506. static int
  1507. mii_get_media_pcs (struct net_device *dev)
  1508. {
  1509. __u16 negotiate;
  1510. __u16 bmsr;
  1511. int phy_addr;
  1512. struct netdev_private *np;
  1513. np = netdev_priv(dev);
  1514. phy_addr = np->phy_addr;
  1515. bmsr = mii_read (dev, phy_addr, PCS_BMSR);
  1516. if (np->an_enable) {
  1517. if (!(bmsr & BMSR_ANEGCOMPLETE)) {
  1518. /* Auto-Negotiation not completed */
  1519. return -1;
  1520. }
  1521. negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
  1522. mii_read (dev, phy_addr, PCS_ANLPAR);
  1523. np->speed = 1000;
  1524. if (negotiate & PCS_ANAR_FULL_DUPLEX) {
  1525. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1526. np->full_duplex = 1;
  1527. } else {
  1528. printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
  1529. np->full_duplex = 0;
  1530. }
  1531. if (negotiate & PCS_ANAR_PAUSE) {
  1532. np->tx_flow &= 1;
  1533. np->rx_flow &= 1;
  1534. } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
  1535. np->tx_flow = 0;
  1536. np->rx_flow &= 1;
  1537. }
  1538. /* else tx_flow, rx_flow = user select */
  1539. } else {
  1540. __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
  1541. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1542. if (bmcr & BMCR_FULLDPLX) {
  1543. printk (KERN_CONT "Full duplex\n");
  1544. } else {
  1545. printk (KERN_CONT "Half duplex\n");
  1546. }
  1547. }
  1548. if (np->tx_flow)
  1549. printk(KERN_INFO "Enable Tx Flow Control\n");
  1550. else
  1551. printk(KERN_INFO "Disable Tx Flow Control\n");
  1552. if (np->rx_flow)
  1553. printk(KERN_INFO "Enable Rx Flow Control\n");
  1554. else
  1555. printk(KERN_INFO "Disable Rx Flow Control\n");
  1556. return 0;
  1557. }
  1558. static int
  1559. mii_set_media_pcs (struct net_device *dev)
  1560. {
  1561. __u16 bmcr;
  1562. __u16 esr;
  1563. __u16 anar;
  1564. int phy_addr;
  1565. struct netdev_private *np;
  1566. np = netdev_priv(dev);
  1567. phy_addr = np->phy_addr;
  1568. /* Auto-Negotiation? */
  1569. if (np->an_enable) {
  1570. /* Advertise capabilities */
  1571. esr = mii_read (dev, phy_addr, PCS_ESR);
  1572. anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
  1573. ~PCS_ANAR_HALF_DUPLEX &
  1574. ~PCS_ANAR_FULL_DUPLEX;
  1575. if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
  1576. anar |= PCS_ANAR_HALF_DUPLEX;
  1577. if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
  1578. anar |= PCS_ANAR_FULL_DUPLEX;
  1579. anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
  1580. mii_write (dev, phy_addr, MII_ADVERTISE, anar);
  1581. /* Soft reset PHY */
  1582. mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
  1583. bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
  1584. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1585. mdelay(1);
  1586. } else {
  1587. /* Force speed setting */
  1588. /* PHY Reset */
  1589. bmcr = BMCR_RESET;
  1590. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1591. mdelay(10);
  1592. if (np->full_duplex) {
  1593. bmcr = BMCR_FULLDPLX;
  1594. printk (KERN_INFO "Manual full duplex\n");
  1595. } else {
  1596. bmcr = 0;
  1597. printk (KERN_INFO "Manual half duplex\n");
  1598. }
  1599. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1600. mdelay(10);
  1601. /* Advertise nothing */
  1602. mii_write (dev, phy_addr, MII_ADVERTISE, 0);
  1603. }
  1604. return 0;
  1605. }
  1606. static int
  1607. rio_close (struct net_device *dev)
  1608. {
  1609. struct netdev_private *np = netdev_priv(dev);
  1610. struct pci_dev *pdev = np->pdev;
  1611. netif_stop_queue (dev);
  1612. rio_hw_stop(dev);
  1613. free_irq(pdev->irq, dev);
  1614. del_timer_sync (&np->timer);
  1615. free_list(dev);
  1616. return 0;
  1617. }
  1618. static void
  1619. rio_remove1 (struct pci_dev *pdev)
  1620. {
  1621. struct net_device *dev = pci_get_drvdata (pdev);
  1622. if (dev) {
  1623. struct netdev_private *np = netdev_priv(dev);
  1624. unregister_netdev (dev);
  1625. pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
  1626. np->rx_ring_dma);
  1627. pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
  1628. np->tx_ring_dma);
  1629. #ifdef MEM_MAPPING
  1630. pci_iounmap(pdev, np->ioaddr);
  1631. #endif
  1632. pci_iounmap(pdev, np->eeprom_addr);
  1633. free_netdev (dev);
  1634. pci_release_regions (pdev);
  1635. pci_disable_device (pdev);
  1636. }
  1637. }
  1638. #ifdef CONFIG_PM_SLEEP
  1639. static int rio_suspend(struct device *device)
  1640. {
  1641. struct net_device *dev = dev_get_drvdata(device);
  1642. struct netdev_private *np = netdev_priv(dev);
  1643. if (!netif_running(dev))
  1644. return 0;
  1645. netif_device_detach(dev);
  1646. del_timer_sync(&np->timer);
  1647. rio_hw_stop(dev);
  1648. return 0;
  1649. }
  1650. static int rio_resume(struct device *device)
  1651. {
  1652. struct net_device *dev = dev_get_drvdata(device);
  1653. struct netdev_private *np = netdev_priv(dev);
  1654. if (!netif_running(dev))
  1655. return 0;
  1656. rio_reset_ring(np);
  1657. rio_hw_init(dev);
  1658. np->timer.expires = jiffies + 1 * HZ;
  1659. add_timer(&np->timer);
  1660. netif_device_attach(dev);
  1661. dl2k_enable_int(np);
  1662. return 0;
  1663. }
  1664. static SIMPLE_DEV_PM_OPS(rio_pm_ops, rio_suspend, rio_resume);
  1665. #define RIO_PM_OPS (&rio_pm_ops)
  1666. #else
  1667. #define RIO_PM_OPS NULL
  1668. #endif /* CONFIG_PM_SLEEP */
  1669. static struct pci_driver rio_driver = {
  1670. .name = "dl2k",
  1671. .id_table = rio_pci_tbl,
  1672. .probe = rio_probe1,
  1673. .remove = rio_remove1,
  1674. .driver.pm = RIO_PM_OPS,
  1675. };
  1676. module_pci_driver(rio_driver);
  1677. /*
  1678. Compile command:
  1679. gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c
  1680. Read Documentation/networking/dl2k.txt for details.
  1681. */