au1000_eth.h 3.0 KB

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  1. /*
  2. *
  3. * Alchemy Au1x00 ethernet driver include file
  4. *
  5. * Author: Pete Popov <ppopov@mvista.com>
  6. *
  7. * Copyright 2001 MontaVista Software Inc.
  8. *
  9. * ########################################################################
  10. *
  11. * This program is free software; you can distribute it and/or modify it
  12. * under the terms of the GNU General Public License (Version 2) as
  13. * published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope it will be useful, but WITHOUT
  16. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  18. * for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License along
  21. * with this program; if not, see <http://www.gnu.org/licenses/>.
  22. *
  23. * ########################################################################
  24. *
  25. *
  26. */
  27. #define MAC_IOSIZE 0x10000
  28. #define NUM_RX_DMA 4 /* Au1x00 has 4 rx hardware descriptors */
  29. #define NUM_TX_DMA 4 /* Au1x00 has 4 tx hardware descriptors */
  30. #define NUM_RX_BUFFS 4
  31. #define NUM_TX_BUFFS 4
  32. #define MAX_BUF_SIZE 2048
  33. #define ETH_TX_TIMEOUT (HZ/4)
  34. #define MAC_MIN_PKT_SIZE 64
  35. #define MULTICAST_FILTER_LIMIT 64
  36. /*
  37. * Data Buffer Descriptor. Data buffers must be aligned on 32 byte
  38. * boundary for both, receive and transmit.
  39. */
  40. struct db_dest {
  41. struct db_dest *pnext;
  42. u32 *vaddr;
  43. dma_addr_t dma_addr;
  44. };
  45. /*
  46. * The transmit and receive descriptors are memory
  47. * mapped registers.
  48. */
  49. struct tx_dma {
  50. u32 status;
  51. u32 buff_stat;
  52. u32 len;
  53. u32 pad;
  54. };
  55. struct rx_dma {
  56. u32 status;
  57. u32 buff_stat;
  58. u32 pad[2];
  59. };
  60. /*
  61. * MAC control registers, memory mapped.
  62. */
  63. struct mac_reg {
  64. u32 control;
  65. u32 mac_addr_high;
  66. u32 mac_addr_low;
  67. u32 multi_hash_high;
  68. u32 multi_hash_low;
  69. u32 mii_control;
  70. u32 mii_data;
  71. u32 flow_control;
  72. u32 vlan1_tag;
  73. u32 vlan2_tag;
  74. };
  75. struct au1000_private {
  76. struct db_dest *pDBfree;
  77. struct db_dest db[NUM_RX_BUFFS+NUM_TX_BUFFS];
  78. struct rx_dma *rx_dma_ring[NUM_RX_DMA];
  79. struct tx_dma *tx_dma_ring[NUM_TX_DMA];
  80. struct db_dest *rx_db_inuse[NUM_RX_DMA];
  81. struct db_dest *tx_db_inuse[NUM_TX_DMA];
  82. u32 rx_head;
  83. u32 tx_head;
  84. u32 tx_tail;
  85. u32 tx_full;
  86. int mac_id;
  87. int mac_enabled; /* whether MAC is currently enabled and running
  88. * (req. for mdio)
  89. */
  90. int old_link; /* used by au1000_adjust_link */
  91. int old_speed;
  92. int old_duplex;
  93. struct mii_bus *mii_bus;
  94. /* PHY configuration */
  95. int phy_static_config;
  96. int phy_search_highest_addr;
  97. int phy1_search_mac0;
  98. int phy_addr;
  99. int phy_busid;
  100. int phy_irq;
  101. /* These variables are just for quick access
  102. * to certain regs addresses.
  103. */
  104. struct mac_reg *mac; /* mac registers */
  105. u32 *enable; /* address of MAC Enable Register */
  106. void __iomem *macdma; /* base of MAC DMA port */
  107. u32 vaddr; /* virtual address of rx/tx buffers */
  108. dma_addr_t dma_addr; /* dma address of rx/tx buffers */
  109. spinlock_t lock; /* Serialise access to device */
  110. u32 msg_enable;
  111. };