RESULTS.txt 7.0 KB

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  1. 1. Interpretation of results
  2. The test program syncs with the 9918 (or similar) vertical interrupt. It
  3. does not consider any of the other interrupts in the V9938 or later.
  4. The results will probably be meaningless in any machine with separate clocks
  5. for the CPU and the VDP. Even in machines with a shared clock, there seem
  6. to be six possible phases between CPU and VDP, as demonstrated by the three
  7. different results obtained in the VG-8020/40 and the NMS-8250.
  8. All measurements are taken from the CPU (no hardware probes), therefore
  9. they all use the CPU clock as a basis.
  10. The program reports a screen with this layout:
  11. Screen mode: S
  12. Error code (0=no error): E
  13. Cycles/frame: F
  14. ACK works A cyc. after INT
  15. Bit 7 set B cyc. after INT
  16. ACK takes C to D cycles
  17. 1st fast wr. failure cycles:
  18. 12T: G12 14T: G14
  19. 17T: G17 18T: G18
  20. 19T: G19 20T: G20
  21. 21T: G21 22T: G22
  22. 23T: G23 24T: G24
  23. Where:
  24. F: total CPU cycles per frame.
  25. E: exit error code; a value of 0 means no error.
  26. Note: The value of F has been found to be stable in all tested computers,
  27. even in those with separate clocks. Cause is unknown.
  28. A: Number of ticks at which an interrupt may be acknowledged by reading
  29. the Status Register, relative to the interrupt, causing the interrupt
  30. line to go inactive. Negative means before the interrupt. It was
  31. negative in every tested VDP, but note that a positive value of up to
  32. 19 cycles would allow any interrupt service routine to acknowledge it,
  33. due to the delay for the interrupt to trigger and for the fastest IN
  34. instruction to execute.
  35. B: Number of ticks, relative to the interrupt, at which the Status
  36. Register bit 7 starts being set. Negative means before the interrupt.
  37. C, D: Minimum and maximum number of cycles for interrupt acknowledgement,
  38. that is, from the I/O read of the Status Register to an INT being
  39. no longer triggered. D=-1 means from C up. Possible values of C,D are:
  40. 0,2; 3,5; 6,10; 11,12; 13,13; 14,14; 15,15; 16,-1.
  41. I don't think software can distinguish finer results. Suggestions for
  42. how to perform a more fine-grained test are welcome.
  43. G12: Number of ticks, relative to the interrupt, at which writing to VRAM
  44. with a 12 cycle separation between OUTs causes a write failure. A value
  45. equal to F (total CPU cycles per frame) means that every fast write
  46. succeeds.
  47. G14: Like G12 but with a 14 cycle separation.
  48. G17: Like G12 but with a 17 cycle separation.
  49. G18: Like G12 but with a 18 cycle separation.
  50. G19: Like G12 but with a 19 cycle separation.
  51. G20: Like G12 but with a 20 cycle separation.
  52. G21: Like G12 but with a 21 cycle separation.
  53. G22: Like G12 but with a 22 cycle separation.
  54. G23: Like G12 but with a 23 cycle separation.
  55. G24: Like G12 but with a 24 cycle separation.
  56. Example using one set of values obtained in the Philips VG-8020/40:
  57. E: 0
  58. - Error code: 0, meaning no error.
  59. F: 71364
  60. - 71364 cycles (T-states) per frame (typical in PAL machines).
  61. A: -5
  62. B: -3
  63. - If the status register is read 5 cycles before the interrupt, the
  64. interrupt is not triggered. This counts the exact cycle at which the
  65. I/O operation takes place, not the start of the instruction.
  66. - Bit 7 of the status register is set 3 cycles before the interrupt.
  67. - Note that when A < B, that leaves a gap in which, if the status port
  68. is read at a cycle >= A and < B, neither bit 7 of the Status Register
  69. will be set, nor will the interrupt trigger.
  70. C: 3
  71. D: 5
  72. - Once the int line goes low (active), it takes between 3 and 5 cycles
  73. inclusive (but we don't know how many exactly) for the interrupt to be
  74. blocked after being acknowledged. Note: Since the /INT line is sampled
  75. at the last cycle of each instruction, this probably means that at the
  76. hardware level, it takes between 2 and 4 cycles for this line to go high
  77. again.
  78. G12: 27130
  79. - Writing to the VRAM with a 12 cycle separation (faster than the VDP
  80. can handle) is guaranteed to succeed if performed during cycles 0 to
  81. 27129 inclusive after the interrupt; the first time it will fail is
  82. 27130 cycles after the interrupt. A value equal to F (71364 in this
  83. example) means that every fast write succeeds, no matter how many
  84. cycles after the interrupt.
  85. G14: 27130
  86. - When writing to VRAM with a 14 cycle separation, the first failure
  87. appears at cycle 27130 (just like with a 12 cycle separation).
  88. G17: 27130
  89. - When writing to VRAM with a 17 cycle separation, the first failure
  90. appears at cycle 27130.
  91. [and so on]
  92. 2. Results for machines with synced clocks
  93. Philips VG-8020/40 (VDP: TMS9129NL):
  94. E: 0
  95. F: 71364
  96. C, D: 3, 5 always
  97. A, B, G12, G14, G17, G18, G19, G20, G21, G22, G23, G24:
  98. For SCREEN 0: 71364
  99. For SCREEN 1-2, and for SCREEN 3 except when A, B = -5, -4:
  100. Three possible tuples:
  101. -5 -4 27130 27130 27130 27130 27143 27143 27143 27143 27143 27143
  102. -5 -3 27130 27130 27130 27130 27144 27144 27144 27144 27144 27144
  103. -4 -3 27131 27131 27131 27144 27144 27144 27144 27144 27144 27144
  104. For SCREEN 3, G18 is different when A, B = -5, -4:
  105. -5 -4 27130 27130 27130 27143 27143 27143 27143 27143 27143 27143
  106. The values of A, B, G are consistent between runs or soft resets
  107. (DEFUSR=0); they only vary between hard resets (RESET button) or power
  108. cycles.
  109. Two possible explanations for the different A,B,G values are:
  110. - Variation in the phase between VDP and CPU.
  111. - Randomness in the initialization of the internal 2-bit "CPU" counter
  112. in the VDP (see US Patent 4,243,984).
  113. Philips NMS-8250 (VDP: V9938):
  114. E: 0
  115. F: 71364 (59736 after entering VDP(10)=0).
  116. A, B, C, D values observed:
  117. -6, -3, 3, 5
  118. -6, -2, 3, 5
  119. -6, -3, 6, 10
  120. -6, -2, 6, 10
  121. G12, G14, G17, G18, G19, G20, G21, G22, G23, G24:
  122. In SCREEN 0:
  123. 4, 4, 4, 4, 4, 4, 19, 71364/59736
  124. 3, 3, 3, 3, 3, 3, 18, 71364/59736
  125. In SCREEN 1-3:
  126. 8, 8, 71364/59736 x 6
  127. 9, 9, 71364/59736 x 6
  128. Generally consistent between runs but not always. Not consistent
  129. between hard boots (reset or power cycle).
  130. 3. Results for machines with separate clocks
  131. Sony HB-10P (VDP: T6950, separate clocks):
  132. E: 0
  133. F: 71745
  134. A, B: Variable. Minimum A observed was -15; maximum -1. Minimum B observed
  135. was -16; maximum -1. abs(A-B) was always 0 or 1, with both A<B and
  136. A>B observed. They are tested separately, therefore it's possible
  137. that they always occur at the same cycle.
  138. The values became smaller with longer power-on times, suggesting
  139. that the cause is temperature.
  140. C, D: 3, 5
  141. G: not tested yet
  142. 4. Results for openMSX (current master as of Feb 10 2020)
  143. All machines:
  144. E: 0
  145. F: 71364/59736 (PAL/NTSC)
  146. A, B: 0, 0
  147. C, D: 0, 2
  148. Gxx: 71364/59736 (PAL/NTSC) in screen 0
  149. Screens 1-3:
  150. G12, G14, G17, G18, G19, G20, G21, G22, G23: 27588/15960 (PAL/NTSC)
  151. G24: 27608/15980 (PAL/NTSC)