var static_0_0_maingraph; // size=1
// cg_declare_function for static_0_1_uniqnode returning=-2
var static_0_1_uniqnode; // size=0
// cg_declare_function for static_0_2_uniqnode_add returning=-1
var static_0_2_uniqnode_add; // size=0
// cg_declare_function for static_0_3_clear_nodelist returning=-1
var static_0_3_clear_nodelist; // size=0
// cg_declare_function for static_0_4_clear_edgelist returning=-1
var static_0_4_clear_edgelist; // size=0
// cg_declare_function for static_0_5_prep returning=-1
var static_0_5_prep; // size=0
// cg_declare_function for static_0_6_reorg returning=-1
var static_0_6_reorg; // size=0
// cg_declare_function for static_0_7_uncycle returning=-1
var static_0_7_uncycle; // size=0
// cg_declare_function for static_0_8_make_stlist returning=-1
var static_0_8_make_stlist; // size=0
// cg_declare_function for static_0_9_clear_stlist returning=-1
var static_0_9_clear_stlist; // size=0
// cg_declare_function for static_0_10_clear_stlist_all returning=-1
var static_0_10_clear_stlist_all; // size=0
// cg_declare_function for static_0_11_ylevels returning=-1
var static_0_11_ylevels; // size=0
// cg_declare_function for static_0_12_set_level2 returning=-1
var static_0_12_set_level2; // size=0
// cg_declare_function for static_0_13_shorteredges returning=-1
var static_0_13_shorteredges; // size=0
// cg_declare_function for static_0_14_edgesdownwards returning=-1
var static_0_14_edgesdownwards; // size=0
// cg_declare_function for static_0_15_edgelen returning=-1
var static_0_15_edgelen; // size=0
// cg_declare_function for static_0_16_doublespacey returning=-1
var static_0_16_doublespacey; // size=0
// cg_declare_function for static_0_17_edgelabels returning=-1
var static_0_17_edgelabels; // size=0
// cg_declare_function for static_0_18_splitedges returning=-1
var static_0_18_splitedges; // size=0
// cg_declare_function for static_0_19_nodecounts returning=-1
var static_0_19_nodecounts; // size=0
// cg_declare_function for static_0_20_barycenter returning=-1
var static_0_20_barycenter; // size=0
// cg_declare_function for static_0_21_improve_positions returning=-1
var static_0_21_improve_positions; // size=0
// cg_declare_function for static_0_22_finalxy returning=-1
var static_0_22_finalxy; // size=0
// cg_declare_function for static_0_23_findedge returning=-2
var static_0_23_findedge; // size=0
// cg_declare_function for static_0_24_setminmax returning=-1
var static_0_24_setminmax; // size=0
// cg_declare_function for sfg_version returning=0
var sfg_version; // size=0
// cg_declare_function for sfg_init returning=0
var sfg_init; // size=0
// cg_declare_function for calloc returning=-2
var calloc; // size=0
// cg_declare_function for sfg_deinit returning=0
var sfg_deinit; // size=0
// cg_declare_function for free returning=-1
var free; // size=0
// cg_declare_function for sfg_addnode returning=0
var sfg_addnode; // size=0
// cg_declare_function for sfg_addedge returning=0
var sfg_addedge; // size=0
// cg_declare_function for sfg_layout returning=0
var sfg_layout; // size=0
// cg_declare_function for sfg_crossings returning=0
var sfg_crossings; // size=0
// cg_declare_function for sfg_initialcrossings returning=0
var sfg_initialcrossings; // size=0
// cg_declare_function for sfg_edgelabels returning=0
var sfg_edgelabels; // size=0
// cg_declare_function for sfg_nodexpos returning=0
var sfg_nodexpos; // size=0
// cg_declare_function for sfg_nodeypos returning=0
var sfg_nodeypos; // size=0
// cg_declare_function for sfg_noderelxpos returning=0
var sfg_noderelxpos; // size=0
// cg_declare_function for sfg_noderelypos returning=0
var sfg_noderelypos; // size=0
// cg_declare_function for sfg_nodely0 returning=0
var sfg_nodely0; // size=0
// cg_declare_function for sfg_nodely1 returning=0
var sfg_nodely1; // size=0
// cg_declare_function for sfg_nodexsize returning=0
var sfg_nodexsize; // size=0
// cg_declare_function for sfg_nodeysize returning=0
var sfg_nodeysize; // size=0
// cg_declare_function for sfg_xspacing returning=0
var sfg_xspacing; // size=0
// cg_declare_function for sfg_yspacing returning=0
var sfg_yspacing; // size=0
// cg_declare_function for sfg_maxx returning=0
var sfg_maxx; // size=0
// cg_declare_function for sfg_maxy returning=0
var sfg_maxy; // size=0
// cg_declare_function for sfg_nodemin returning=0
var sfg_nodemin; // size=0
// cg_declare_function for sfg_nodemax returning=0
var sfg_nodemax; // size=0
// cg_declare_function for sfg_edgemin returning=0
var sfg_edgemin; // size=0
// cg_declare_function for sfg_edgemax returning=0
var sfg_edgemax; // size=0
// cg_declare_function for sfg_nlevels returning=0
var sfg_nlevels; // size=0
// cg_declare_function for sfg_nnodes returning=0
var sfg_nnodes; // size=0
// cg_declare_function for sfg_nedges returning=0
var sfg_nedges; // size=0
// cg_declare_function for sfg_nodetype returning=0
var sfg_nodetype; // size=0
// cg_declare_function for sfg_nodeselfedges returning=0
var sfg_nodeselfedges; // size=0
// cg_declare_function for sfg_nodeindegree returning=0
var sfg_nodeindegree; // size=0
// cg_declare_function for sfg_nodeoutdegree returning=0
var sfg_nodeoutdegree; // size=0
// cg_declare_function for sfg_nodeenum returning=0
var sfg_nodeenum; // size=0
// cg_declare_function for sfg_nodedata returning=-2
var sfg_nodedata; // size=0
// cg_declare_function for sfg_setnodedata returning=0
var sfg_setnodedata; // size=0
// cg_declare_function for sfg_edgefrom returning=0
var sfg_edgefrom; // size=0
// cg_declare_function for sfg_edgeto returning=0
var sfg_edgeto; // size=0
// cg_declare_function for sfg_edgetype returning=0
var sfg_edgetype; // size=0
// cg_declare_function for sfg_edgerev returning=0
var sfg_edgerev; // size=0
// cg_declare_function for static_0_25_uniqnode returning=-2
var static_0_25_uniqnode; // size=0
// cg_declare_function for static_0_26_uniqnode_add returning=-1
var static_0_26_uniqnode_add; // size=0
// cg_declare_function for static_0_27_clear_nodelist returning=-1
var static_0_27_clear_nodelist; // size=0
// cg_declare_function for static_0_28_clear_edgelist returning=-1
var static_0_28_clear_edgelist; // size=0
// cg_declare_function for static_0_29_prep returning=-1
var static_0_29_prep; // size=0
// cg_declare_function for static_0_30_reorg returning=-1
var static_0_30_reorg; // size=0
// cg_declare_function for static_0_31_decycle3 returning=0
var static_0_31_decycle3; // size=0
// cg_declare_function for static_0_32_uncycle returning=-1
var static_0_32_uncycle; // size=0
// cg_declare_function for static_0_33_make_stlist returning=-1
var static_0_33_make_stlist; // size=0
// cg_declare_function for static_0_34_clear_stlist returning=-1
var static_0_34_clear_stlist; // size=0
// cg_declare_function for static_0_35_clear_stlist_all returning=-1
var static_0_35_clear_stlist_all; // size=0
// cg_declare_function for static_0_36_add_singlenode returning=-1
var static_0_36_add_singlenode; // size=0
// cg_declare_function for static_0_37_ylevels returning=-1
var static_0_37_ylevels; // size=0
// cg_declare_function for static_0_38_set_level2 returning=-1
var static_0_38_set_level2; // size=0
// cg_declare_function for static_0_39_unrev returning=-1
var static_0_39_unrev; // size=0
// cg_declare_function for static_0_40_do_abs returning=0
var static_0_40_do_abs; // size=0
// cg_declare_function for static_0_41_shorteredges returning=-1
var static_0_41_shorteredges; // size=0
// cg_declare_function for static_0_42_edgesdownwards returning=-1
var static_0_42_edgesdownwards; // size=0
// cg_declare_function for static_0_43_edgelen returning=-1
var static_0_43_edgelen; // size=0
// cg_declare_function for static_0_44_doublespacey returning=-1
var static_0_44_doublespacey; // size=0
// cg_declare_function for static_0_45_add_new_dummynode returning=-1
var static_0_45_add_new_dummynode; // size=0
// cg_declare_function for static_0_46_add_new_dummyedge returning=-1
var static_0_46_add_new_dummyedge; // size=0
// cg_declare_function for static_0_47_del_edge returning=-1
var static_0_47_del_edge; // size=0
// cg_declare_function for static_0_48_edgelabels returning=-1
var static_0_48_edgelabels; // size=0
// cg_declare_function for static_0_49_splitedges returning=-1
var static_0_49_splitedges; // size=0
// cg_declare_function for static_0_50_nodecounts returning=-1
var static_0_50_nodecounts; // size=0
// cg_declare_function for static_0_51_number_of_crossings2 returning=0
var static_0_51_number_of_crossings2; // size=0
// cg_declare_function for static_0_52_testbit returning=0
var static_0_52_testbit; // size=0
// cg_declare_function for static_0_53_mget returning=0
var static_0_53_mget; // size=0
// cg_declare_function for static_0_54_number_of_crossings3 returning=0
var static_0_54_number_of_crossings3; // size=0
// cg_declare_function for static_0_55_number_of_crossings_a returning=0
var static_0_55_number_of_crossings_a; // size=0
// cg_declare_function for static_0_56_make_matrix returning=-1
var static_0_56_make_matrix; // size=0
// cg_declare_function for static_0_57_setbit returning=-1
var static_0_57_setbit; // size=0
// cg_declare_function for static_0_58_clearbit returning=-1
var static_0_58_clearbit; // size=0
// cg_declare_function for static_0_59_mget_set returning=-1
var static_0_59_mget_set; // size=0
// cg_declare_function for static_0_60_su_find_node_with_number returning=-2
var static_0_60_su_find_node_with_number; // size=0
// cg_declare_function for static_0_61_store_new_positions returning=-1
var static_0_61_store_new_positions; // size=0
// cg_declare_function for static_0_62_copy_m returning=-1
var static_0_62_copy_m; // size=0
// cg_declare_function for do_memmove returning=-1
var do_memmove; // size=0
// cg_declare_function for static_0_63_equal_m returning=0
var static_0_63_equal_m; // size=0
// cg_declare_function for static_0_64_equal_a returning=0
var static_0_64_equal_a; // size=0
// cg_declare_function for static_0_65_exch_rows returning=-1
var static_0_65_exch_rows; // size=0
// cg_declare_function for static_0_66_exch_columns returning=-1
var static_0_66_exch_columns; // size=0
// cg_declare_function for static_0_67_reverse_r returning=0
var static_0_67_reverse_r; // size=0
// cg_declare_function for static_0_68_reverse_c returning=0
var static_0_68_reverse_c; // size=0
// cg_declare_function for static_0_69_row_barycenter returning=0
var static_0_69_row_barycenter; // size=0
// cg_declare_function for static_0_70_column_barycenter returning=0
var static_0_70_column_barycenter; // size=0
// cg_declare_function for static_0_71_r_r returning=0
var static_0_71_r_r; // size=0
// cg_declare_function for static_0_72_r_c returning=0
var static_0_72_r_c; // size=0
// cg_declare_function for static_0_73_b_r returning=0
var static_0_73_b_r; // size=0
// cg_declare_function for static_0_74_b_c returning=0
var static_0_74_b_c; // size=0
// cg_declare_function for static_0_75_sorted returning=0
var static_0_75_sorted; // size=0
// cg_declare_function for static_0_76_bc_n returning=-1
var static_0_76_bc_n; // size=0
// cg_declare_function for static_0_77_copy_a returning=-1
var static_0_77_copy_a; // size=0
// cg_declare_function for static_0_78_phase1_down returning=0
var static_0_78_phase1_down; // size=0
// cg_declare_function for static_0_79_phase1_up returning=0
var static_0_79_phase1_up; // size=0
// cg_declare_function for static_0_80_phase2_down returning=0
var static_0_80_phase2_down; // size=0
// cg_declare_function for static_0_81_phase2_up returning=0
var static_0_81_phase2_up; // size=0
// cg_declare_function for static_0_82_barycenter returning=-1
var static_0_82_barycenter; // size=0
var static_0_83_mindist; // size=1
var static_0_84_csn; // size=1
var static_0_85_cnodelist; // size=1
var static_0_86_cnodelisttail; // size=1
var static_0_87_cnnodes_of_level; // size=1
var static_0_88_cmaxx; // size=1
var static_0_89_cmaxy; // size=1
var static_0_90_cwidestnnodes; // size=1
var static_0_91_cwpos; // size=1
var static_0_92_cposnodes; // size=1
var static_0_93_chpos; // size=1
var static_0_94_clevelnodes; // size=1
var static_0_95_xspacing; // size=1
var static_0_96_yspacing; // size=1
var static_0_97_nl; // size=1
// cg_declare_function for static_0_98_is_dummy returning=0
var static_0_98_is_dummy; // size=0
// cg_declare_function for static_0_99_upper_connectivity returning=0
var static_0_99_upper_connectivity; // size=0
// cg_declare_function for static_0_100_lower_connectivity returning=0
var static_0_100_lower_connectivity; // size=0
// cg_declare_function for static_0_101_do_floor returning=0
var static_0_101_do_floor; // size=0
// cg_declare_function for static_0_102_upper_barycenter returning=0
var static_0_102_upper_barycenter; // size=0
// cg_declare_function for static_0_103_lower_barycenter returning=0
var static_0_103_lower_barycenter; // size=0
// cg_declare_function for static_0_104_sort returning=-1
var static_0_104_sort; // size=0
// cg_declare_function for static_0_105_make_node_list_up returning=-1
var static_0_105_make_node_list_up; // size=0
// cg_declare_function for static_0_106_make_node_list_down returning=-1
var static_0_106_make_node_list_down; // size=0
// cg_declare_function for static_0_107_find_next returning=0
var static_0_107_find_next; // size=0
// cg_declare_function for static_0_108_do_down returning=-1
var static_0_108_do_down; // size=0
// cg_declare_function for static_0_109_do_up returning=-1
var static_0_109_do_up; // size=0
// cg_declare_function for static_0_110_improve_positions2local returning=-1
var static_0_110_improve_positions2local; // size=0
// cg_declare_function for static_0_111_make_cnnodes_at_level returning=-1
var static_0_111_make_cnnodes_at_level; // size=0
// cg_declare_function for static_0_112_clear_cnnodes_at_level returning=-1
var static_0_112_clear_cnnodes_at_level; // size=0
// cg_declare_function for static_0_113_make_cnodelist returning=-1
var static_0_113_make_cnodelist; // size=0
// cg_declare_function for static_0_114_clear_cnodelist returning=-1
var static_0_114_clear_cnodelist; // size=0
// cg_declare_function for static_0_115_move0 returning=-1
var static_0_115_move0; // size=0
// cg_declare_function for static_0_116_make_cposnodes returning=-1
var static_0_116_make_cposnodes; // size=0
// cg_declare_function for static_0_117_clear_cposnodes returning=-1
var static_0_117_clear_cposnodes; // size=0
// cg_declare_function for static_0_118_make_clevelnodes returning=-1
var static_0_118_make_clevelnodes; // size=0
// cg_declare_function for static_0_119_clear_clevelnodes returning=-1
var static_0_119_clear_clevelnodes; // size=0
// cg_declare_function for static_0_120_cfinalxy returning=-1
var static_0_120_cfinalxy; // size=0
// cg_declare_function for static_0_121_movefinal returning=-1
var static_0_121_movefinal; // size=0
// cg_declare_function for static_0_122_tunedummy returning=-1
var static_0_122_tunedummy; // size=0
// cg_declare_function for static_0_123_tunenodes returning=-1
var static_0_123_tunenodes; // size=0
// cg_declare_function for static_0_124_improve_positions returning=-1
var static_0_124_improve_positions; // size=0
// cg_declare_function for static_0_125_finalxy returning=-1
var static_0_125_finalxy; // size=0
// cg_declare_function for static_0_126_findedge returning=-2
var static_0_126_findedge; // size=0
// cg_declare_function for static_0_127_setminmax returning=-1
var static_0_127_setminmax; // size=0

function sfg_version(fp, stack) {
var sp;
var REG0;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG0 = 20;
return REG0;
} } }

function sfg_init(fp, stack) {
var sp;
var REG0;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG1 = static_0_0_maingraph;
REG0 = 0;
REG2 = REG1[REG0 + 0];
REG3 = REG1[REG0 + 1];
state = REG3 ? 1 : 4; break;
case 1: // basic block start for source line 202
REG0 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 199
return REG0;
case 3: // basic block start for source line 206
REG0 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 204
REG0 = 35;
REG3 = 1;
REG4 = calloc;
REG5 = REG4(sp, stack, REG3, REG0);
REG6 = REG5[1]
REG5 = REG5[0]
REG1 = REG5;
REG2 = REG6;
REG3 = static_0_0_maingraph;
REG0 = 0;
REG3[REG0 + 0] = REG1;
REG3[REG0 + 1] = REG2;
state = REG2 ? 5 : 3; break;
case 5: // basic block start for source line 209
REG3 = 5;
REG2[REG1 + 13] = REG3;
REG2 = static_0_0_maingraph;
REG1 = 0;
REG3 = REG2[REG1 + 0];
REG4 = REG2[REG1 + 1];
REG1 = 15;
REG4[REG3 + 14] = REG1;
REG2 = static_0_0_maingraph;
REG1 = 0;
REG3 = REG2[REG1 + 0];
REG4 = REG2[REG1 + 1];
REG1 = 1;
REG4[REG3 + 7] = REG1;
REG0 = 0;
state = 2; break;
} } }

function sfg_deinit(fp, stack) {
var sp;
var REG0;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = static_0_0_maingraph;
REG2 = 0;
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
state = REG1 ? 6 : 1; break;
case 1: // basic block start for source line 222
REG2 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 219
return REG2;
case 3: // basic block start for source line 236
REG1 = static_0_0_maingraph;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = static_0_10_clear_stlist_all;
REG0(sp, stack, REG3, REG4);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = static_0_4_clear_edgelist;
REG0(sp, stack, REG3, REG4);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = static_0_3_clear_nodelist;
REG0(sp, stack, REG3, REG4);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = free;
REG0(sp, stack, REG3, REG4);
REG0 = 0;
REG3 = static_0_0_maingraph;
REG1 = 0;
REG3[REG1 + 0] = REG0;
REG2 = 0;
state = 2; break;
case 4: // basic block start for source line 232
REG1 = static_0_0_maingraph;
REG0 = 0;
REG5 = REG1[REG0 + 0];
REG6 = REG1[REG0 + 1];
REG0 = REG6[REG5 + 12];
REG1 = REG6[REG5 + 13];
state = REG1 ? 9 : 3; break;
case 5: // basic block start for source line 228
REG1 = static_0_0_maingraph;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = REG4[REG3 + 21];
REG1 = REG4[REG3 + 22];
state = REG1 ? 8 : 4; break;
case 6: // basic block start for source line 224
REG2 = REG1[REG0 + 27];
REG3 = REG1[REG0 + 28];
state = REG3 ? 7 : 5; break;
case 7: // basic block start for source line 225
REG2 = REG1[REG0 + 27];
REG3 = REG1[REG0 + 28];
REG0 = free;
REG0(sp, stack, REG2, REG3);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG2 = REG1[REG0 + 0];
REG3 = REG1[REG0 + 1];
REG0 = 0;
REG3[REG2 + 27] = REG0;
state = 5; break;
case 8: // basic block start for source line 229
REG0 = REG4[REG3 + 21];
REG1 = REG4[REG3 + 22];
REG2 = free;
REG2(sp, stack, REG0, REG1);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG2 = REG1[REG0 + 0];
REG3 = REG1[REG0 + 1];
REG0 = 0;
REG3[REG2 + 21] = REG0;
state = 4; break;
case 9: // basic block start for source line 233
REG0 = REG6[REG5 + 12];
REG1 = REG6[REG5 + 13];
REG2 = free;
REG2(sp, stack, REG0, REG1);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG2 = REG1[REG0 + 0];
REG3 = REG1[REG0 + 1];
REG0 = 0;
REG3[REG2 + 12] = REG0;
state = 3; break;
} } }

function sfg_addnode(fp, stack, REG0, REG1, REG2) {
var sp;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG6 = static_0_0_maingraph;
REG5 = 0;
REG3 = REG6[REG5 + 0];
REG4 = REG6[REG5 + 1];
state = REG4 ? 4 : 1; break;
case 1: // basic block start for source line 261
REG5 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 256
return REG5;
case 3: // basic block start for source line 264
REG5 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 263
REG5 = 1;
REG6 = (REG0 < REG5) ? 1 : 0;
state = REG6 ? 3 : 5; break;
case 5: // basic block start for source line 266
REG5 = 0;
REG6 = (REG1 < REG5) ? 1 : 0;
state = REG6 ? 6 : 7; break;
case 6: // basic block start for source line 267
REG5 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 269
REG5 = 0;
REG6 = (REG2 < REG5) ? 1 : 0;
state = REG6 ? 8 : 9; break;
case 8: // basic block start for source line 270
REG5 = 4294967292;
state = 2; break;
case 9: // basic block start for source line 272
REG5 = REG4[REG3 + 0];
state = REG5 ? 10 : 11; break;
case 10: // basic block start for source line 273
REG5 = 4294967291;
state = 2; break;
case 11: // basic block start for source line 276
REG5 = static_0_1_uniqnode;
REG6 = REG5(sp, stack, REG3, REG4, REG0);
REG7 = REG6[1]
REG6 = REG6[0]
state = REG7 ? 12 : 13; break;
case 12: // basic block start for source line 277
REG5 = 4294967290;
state = 2; break;
case 13: // basic block start for source line 280
REG3 = 32;
REG4 = 1;
REG5 = calloc;
REG8 = REG5(sp, stack, REG4, REG3);
REG9 = REG8[1]
REG8 = REG8[0]
REG6 = REG8;
REG7 = REG9;
state = REG7 ? 15 : 14; break;
case 14: // basic block start for source line 282
REG5 = 4294967289;
state = 2; break;
case 15: // basic block start for source line 284
REG3 = 2;
REG4 = 1;
REG5 = calloc;
REG10 = REG5(sp, stack, REG4, REG3);
REG11 = REG10[1]
REG10 = REG10[0]
REG8 = REG10;
REG9 = REG11;
state = REG9 ? 17 : 16; break;
case 16: // basic block start for source line 286
REG0 = free;
REG0(sp, stack, REG6, REG7);
REG5 = 4294967289;
state = 2; break;
case 17: // basic block start for source line 289
REG7[REG6 + 0] = REG0;
REG7[REG6 + 1] = REG1;
REG7[REG6 + 2] = REG2;
REG9[REG8 + 0] = REG6;
REG9[REG8 + 1] = REG7;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG10 = REG4[REG3 + 0];
REG11 = REG4[REG3 + 1];
REG3 = REG11[REG10 + 15];
REG4 = REG11[REG10 + 16];
state = REG4 ? 20 : 18; break;
case 18: // basic block start for source line 295
REG11[REG10 + 15] = REG8;
REG11[REG10 + 16] = REG9;
REG2 = static_0_0_maingraph;
REG1 = 0;
REG3 = REG2[REG1 + 0];
REG4 = REG2[REG1 + 1];
REG4[REG3 + 16] = REG8;
REG4[REG3 + 17] = REG9;
state = 19; break;
case 19: // basic block start for source line 301
REG2 = static_0_0_maingraph;
REG1 = 0;
REG12 = REG2[REG1 + 0];
REG13 = REG2[REG1 + 1];
REG1 = REG13[REG12 + 1];
REG2 = (REG0 > REG1) ? 1 : 0;
state = REG2 ? 21 : 22; break;
case 20: // basic block start for source line 298
REG1 = REG11[REG10 + 16];
REG2 = REG11[REG10 + 17];
REG2[REG1 + 1] = REG8;
REG2[REG1 + 2] = REG9;
REG2 = static_0_0_maingraph;
REG1 = 0;
REG3 = REG2[REG1 + 0];
REG4 = REG2[REG1 + 1];
REG4[REG3 + 16] = REG8;
REG4[REG3 + 17] = REG9;
state = 19; break;
case 21: // basic block start for source line 303
REG13[REG12 + 1] = REG0;
state = 22; break;
case 22: // basic block start for source line 305
REG1 = static_0_0_maingraph;
REG0 = 0;
REG2 = REG1[REG0 + 0];
REG3 = REG1[REG0 + 1];
REG0 = static_0_2_uniqnode_add;
REG0(sp, stack, REG2, REG3, REG6, REG7);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG2 = REG1[REG0 + 0];
REG3 = REG1[REG0 + 1];
REG0 = REG3[REG2 + 2];
REG1 = 1;
REG4 = REG0 + REG1;
REG3[REG2 + 2] = REG4;
REG5 = 0;
state = 2; break;
} } }

function sfg_addedge(fp, stack, REG0, REG1, REG2, REG3, REG4) {
var sp;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var REG16;
var REG17;
var REG18;
var REG19;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG8 = static_0_0_maingraph;
REG7 = 0;
REG5 = REG8[REG7 + 0];
REG6 = REG8[REG7 + 1];
state = REG6 ? 4 : 1; break;
case 1: // basic block start for source line 333
REG7 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 326
return REG7;
case 3: // basic block start for source line 336
REG7 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 335
REG7 = 1;
REG8 = (REG0 < REG7) ? 1 : 0;
state = REG8 ? 3 : 5; break;
case 5: // basic block start for source line 338
REG7 = 0;
REG8 = (REG3 < REG7) ? 1 : 0;
state = REG8 ? 6 : 7; break;
case 6: // basic block start for source line 339
REG7 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 341
REG7 = 0;
REG8 = (REG4 < REG7) ? 1 : 0;
state = REG8 ? 8 : 9; break;
case 8: // basic block start for source line 342
REG7 = 4294967292;
state = 2; break;
case 9: // basic block start for source line 344
REG7 = 1;
REG8 = (REG1 < REG7) ? 1 : 0;
state = REG8 ? 10 : 11; break;
case 10: // basic block start for source line 345
REG7 = 4294967291;
state = 2; break;
case 11: // basic block start for source line 347
REG7 = 1;
REG8 = (REG2 < REG7) ? 1 : 0;
state = REG8 ? 12 : 13; break;
case 12: // basic block start for source line 348
REG7 = 4294967290;
state = 2; break;
case 13: // basic block start for source line 350
REG7 = (REG1 == REG2) ? 1 : 0;
state = REG7 ? 14 : 16; break;
case 14: // basic block start for source line 351
REG7 = 0;
REG8 = (REG3 != REG7) ? 1 : 0;
REG7 = 0;
REG9 = (REG4 != REG7) ? 1 : 0;
REG7 = REG8 | REG9;
state = REG7 ? 15 : 16; break;
case 15: // basic block start for source line 352
REG7 = 4294967289;
state = 2; break;
case 16: // basic block start for source line 355
REG7 = REG6[REG5 + 0];
state = REG7 ? 17 : 18; break;
case 17: // basic block start for source line 356
REG7 = 4294967288;
state = 2; break;
case 18: // basic block start for source line 358
REG7 = static_0_1_uniqnode;
REG8 = REG7(sp, stack, REG5, REG6, REG1);
REG9 = REG8[1]
REG8 = REG8[0]
state = REG9 ? 20 : 19; break;
case 19: // basic block start for source line 360
REG7 = 4294967291;
state = 2; break;
case 20: // basic block start for source line 362
REG5 = static_0_0_maingraph;
REG1 = 0;
REG6 = REG5[REG1 + 0];
REG7 = REG5[REG1 + 1];
REG1 = static_0_1_uniqnode;
REG10 = REG1(sp, stack, REG6, REG7, REG2);
REG11 = REG10[1]
REG10 = REG10[0]
state = REG11 ? 22 : 21; break;
case 21: // basic block start for source line 364
REG7 = 4294967290;
state = 2; break;
case 22: // basic block start for source line 366
REG2 = static_0_0_maingraph;
REG1 = 0;
REG12 = REG2[REG1 + 0];
REG13 = REG2[REG1 + 1];
REG1 = REG13[REG12 + 3];
REG2 = (REG0 > REG1) ? 1 : 0;
state = REG2 ? 23 : 24; break;
case 23: // basic block start for source line 367
REG13[REG12 + 3] = REG0;
state = 24; break;
case 24: // basic block start for source line 369
REG2 = static_0_0_maingraph;
REG1 = 0;
REG5 = REG2[REG1 + 0];
REG6 = REG2[REG1 + 1];
REG1 = REG6[REG5 + 4];
REG2 = 1;
REG7 = REG1 + REG2;
REG6[REG5 + 4] = REG7;
REG1 = (REG8 == REG10) ? 1 : 0;
state = REG1 ? 25 : 31; break;
case 25: // basic block start for source line 372
REG0 = REG9[REG8 + 8];
REG1 = 1;
REG2 = REG0 + REG1;
REG9[REG8 + 8] = REG2;
state = 26; break;
case 26: // basic block start for source line 404
REG7 = 0;
state = 2; break;
case 27: // basic block start for source line 397
REG19[REG18 + 19] = REG16;
REG19[REG18 + 20] = REG17;
REG1 = static_0_0_maingraph;
REG0 = 0;
REG2 = REG1[REG0 + 0];
REG3 = REG1[REG0 + 1];
REG3[REG2 + 20] = REG16;
REG3[REG2 + 21] = REG17;
state = 26; break;
case 28: // basic block start for source line 395
REG17[REG16 + 0] = REG14;
REG17[REG16 + 1] = REG15;
REG1 = static_0_0_maingraph;
REG0 = 0;
REG18 = REG1[REG0 + 0];
REG19 = REG1[REG0 + 1];
REG0 = REG19[REG18 + 19];
REG1 = REG19[REG18 + 20];
state = REG1 ? 35 : 27; break;
case 29: // basic block start for source line 384
REG15[REG14 + 0] = REG0;
REG15[REG14 + 1] = REG8;
REG15[REG14 + 2] = REG9;
REG15[REG14 + 2] = REG10;
REG15[REG14 + 3] = REG11;
REG15[REG14 + 3] = REG3;
REG15[REG14 + 4] = REG4;
REG1 = 0;
REG2 = (REG3 != REG1) ? 1 : 0;
REG1 = 0;
REG5 = (REG4 != REG1) ? 1 : 0;
REG1 = REG2 | REG5;
state = REG1 ? 34 : 28; break;
case 30: // basic block start for source line 379
REG1 = 2;
REG2 = 1;
REG5 = calloc;
REG6 = REG5(sp, stack, REG2, REG1);
REG7 = REG6[1]
REG6 = REG6[0]
REG16 = REG6;
REG17 = REG7;
state = REG17 ? 29 : 33; break;
case 31: // basic block start for source line 375
REG1 = 8;
REG2 = 1;
REG5 = calloc;
REG6 = REG5(sp, stack, REG2, REG1);
REG7 = REG6[1]
REG6 = REG6[0]
REG14 = REG6;
REG15 = REG7;
state = REG15 ? 30 : 32; break;
case 32: // basic block start for source line 377
REG7 = 4294967287;
state = 2; break;
case 33: // basic block start for source line 381
REG0 = free;
REG0(sp, stack, REG14, REG15);
REG7 = 4294967287;
state = 2; break;
case 34: // basic block start for source line 391
REG0 = 1;
REG15[REG14 + 5] = REG0;
REG1 = static_0_0_maingraph;
REG0 = 0;
REG2 = REG1[REG0 + 0];
REG3 = REG1[REG0 + 1];
REG0 = REG3[REG2 + 6];
REG1 = 1;
REG4 = REG0 + REG1;
REG3[REG2 + 6] = REG4;
state = 28; break;
case 35: // basic block start for source line 400
REG0 = REG19[REG18 + 20];
REG1 = REG19[REG18 + 21];
REG1[REG0 + 1] = REG16;
REG1[REG0 + 2] = REG17;
REG1 = static_0_0_maingraph;
REG0 = 0;
REG2 = REG1[REG0 + 0];
REG3 = REG1[REG0 + 1];
REG3[REG2 + 20] = REG16;
REG3[REG2 + 21] = REG17;
state = 26; break;
} } }

function sfg_layout(fp, stack) {
var sp;
var REG0;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = static_0_0_maingraph;
REG2 = 0;
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
state = REG1 ? 4 : 1; break;
case 1: // basic block start for source line 416
REG2 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 413
return REG2;
case 3: // basic block start for source line 419
REG2 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 418
REG2 = REG1[REG0 + 0];
state = REG2 ? 3 : 5; break;
case 5: // basic block start for source line 421
REG2 = REG1[REG0 + 15];
REG3 = REG1[REG0 + 16];
state = REG3 ? 7 : 6; break;
case 6: // basic block start for source line 422
REG2 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 426
REG3 = static_0_5_prep;
REG3(sp, stack, REG0, REG1);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = static_0_6_reorg;
REG0(sp, stack, REG3, REG4);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = static_0_7_uncycle;
REG0(sp, stack, REG3, REG4);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = static_0_6_reorg;
REG0(sp, stack, REG3, REG4);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = static_0_11_ylevels;
REG0(sp, stack, REG3, REG4);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = static_0_13_shorteredges;
REG0(sp, stack, REG3, REG4);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = static_0_14_edgesdownwards;
REG0(sp, stack, REG3, REG4);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = static_0_15_edgelen;
REG0(sp, stack, REG3, REG4);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = static_0_16_doublespacey;
REG0(sp, stack, REG3, REG4);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = static_0_17_edgelabels;
REG0(sp, stack, REG3, REG4);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = static_0_18_splitedges;
REG0(sp, stack, REG3, REG4);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = static_0_19_nodecounts;
REG0(sp, stack, REG3, REG4);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = 100;
REG1 = 100;
REG5 = static_0_20_barycenter;
REG5(sp, stack, REG3, REG4, REG1, REG0);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = static_0_21_improve_positions;
REG0(sp, stack, REG3, REG4);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = static_0_22_finalxy;
REG0(sp, stack, REG3, REG4);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = static_0_24_setminmax;
REG0(sp, stack, REG3, REG4);
REG1 = static_0_0_maingraph;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = 1;
REG4[REG3 + 0] = REG0;
REG2 = 0;
state = 2; break;
} } }

function sfg_crossings(fp, stack) {
var sp;
var REG0;
var REG1;
var REG2;
var REG3;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = static_0_0_maingraph;
REG2 = 0;
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
state = REG1 ? 4 : 1; break;
case 1: // basic block start for source line 487
REG2 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 484
return REG2;
case 3: // basic block start for source line 490
REG2 = 4294967274;
state = 2; break;
case 4: // basic block start for source line 489
REG2 = REG1[REG0 + 0];
state = REG2 ? 5 : 3; break;
case 5: // basic block start for source line 492
REG3 = REG1[REG0 + 25];
REG2 = REG3;
state = 2; break;
} } }

function sfg_initialcrossings(fp, stack) {
var sp;
var REG0;
var REG1;
var REG2;
var REG3;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = static_0_0_maingraph;
REG2 = 0;
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
state = REG1 ? 4 : 1; break;
case 1: // basic block start for source line 503
REG2 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 500
return REG2;
case 3: // basic block start for source line 506
REG2 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 505
REG2 = REG1[REG0 + 0];
state = REG2 ? 5 : 3; break;
case 5: // basic block start for source line 508
REG3 = REG1[REG0 + 24];
REG2 = REG3;
state = 2; break;
} } }

function sfg_edgelabels(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 4 : 1; break;
case 1: // basic block start for source line 519
REG3 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 516
return REG3;
case 3: // basic block start for source line 522
REG3 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 521
REG3 = REG2[REG1 + 0];
state = REG3 ? 3 : 5; break;
case 5: // basic block start for source line 524
state = REG0 ? 6 : 8; break;
case 6: // basic block start for source line 525
REG0 = 1;
REG2[REG1 + 7] = REG0;
state = 7; break;
case 7: // basic block start for source line 529
REG3 = 0;
state = 2; break;
case 8: // basic block start for source line 527
REG0 = 1;
REG2[REG1 + 7] = REG0;
state = 7; break;
} } }

function sfg_nodexpos(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 4 : 1; break;
case 1: // basic block start for source line 543
REG3 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 539
return REG3;
case 3: // basic block start for source line 546
REG3 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 545
REG3 = REG2[REG1 + 0];
state = REG3 ? 5 : 3; break;
case 5: // basic block start for source line 548
REG3 = 1;
REG4 = (REG0 < REG3) ? 1 : 0;
state = REG4 ? 6 : 7; break;
case 6: // basic block start for source line 549
REG3 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 551
REG3 = static_0_1_uniqnode;
REG4 = REG3(sp, stack, REG1, REG2, REG0);
REG5 = REG4[1]
REG4 = REG4[0]
state = REG5 ? 9 : 8; break;
case 8: // basic block start for source line 553
REG3 = 4294967292;
state = 2; break;
case 9: // basic block start for source line 555
REG0 = REG5[REG4 + 23];
REG3 = REG0;
state = 2; break;
} } }

function sfg_nodeypos(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 4 : 1; break;
case 1: // basic block start for source line 569
REG3 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 565
return REG3;
case 3: // basic block start for source line 572
REG3 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 571
REG3 = REG2[REG1 + 0];
state = REG3 ? 5 : 3; break;
case 5: // basic block start for source line 574
REG3 = 1;
REG4 = (REG0 < REG3) ? 1 : 0;
state = REG4 ? 6 : 7; break;
case 6: // basic block start for source line 575
REG3 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 577
REG3 = static_0_1_uniqnode;
REG4 = REG3(sp, stack, REG1, REG2, REG0);
REG5 = REG4[1]
REG4 = REG4[0]
state = REG5 ? 9 : 8; break;
case 8: // basic block start for source line 579
REG3 = 4294967292;
state = 2; break;
case 9: // basic block start for source line 581
REG0 = REG5[REG4 + 24];
REG3 = REG0;
state = 2; break;
} } }

function sfg_noderelxpos(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 4 : 1; break;
case 1: // basic block start for source line 595
REG3 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 591
return REG3;
case 3: // basic block start for source line 598
REG3 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 597
REG3 = REG2[REG1 + 0];
state = REG3 ? 5 : 3; break;
case 5: // basic block start for source line 600
REG3 = 1;
REG4 = (REG0 < REG3) ? 1 : 0;
state = REG4 ? 6 : 7; break;
case 6: // basic block start for source line 601
REG3 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 603
REG3 = static_0_1_uniqnode;
REG4 = REG3(sp, stack, REG1, REG2, REG0);
REG5 = REG4[1]
REG4 = REG4[0]
state = REG5 ? 9 : 8; break;
case 8: // basic block start for source line 605
REG3 = 4294967292;
state = 2; break;
case 9: // basic block start for source line 607
REG0 = REG5[REG4 + 15];
REG3 = REG0;
state = 2; break;
} } }

function sfg_noderelypos(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 4 : 1; break;
case 1: // basic block start for source line 621
REG3 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 617
return REG3;
case 3: // basic block start for source line 624
REG3 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 623
REG3 = REG2[REG1 + 0];
state = REG3 ? 5 : 3; break;
case 5: // basic block start for source line 626
REG3 = 1;
REG4 = (REG0 < REG3) ? 1 : 0;
state = REG4 ? 6 : 7; break;
case 6: // basic block start for source line 627
REG3 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 629
REG3 = static_0_1_uniqnode;
REG4 = REG3(sp, stack, REG1, REG2, REG0);
REG5 = REG4[1]
REG4 = REG4[0]
state = REG5 ? 9 : 8; break;
case 8: // basic block start for source line 631
REG3 = 4294967292;
state = 2; break;
case 9: // basic block start for source line 633
REG0 = REG5[REG4 + 16];
REG3 = REG0;
state = 2; break;
} } }

function sfg_nodely0(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 4 : 1; break;
case 1: // basic block start for source line 647
REG3 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 643
return REG3;
case 3: // basic block start for source line 650
REG3 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 649
REG3 = REG2[REG1 + 0];
state = REG3 ? 5 : 3; break;
case 5: // basic block start for source line 652
REG3 = 1;
REG4 = (REG0 < REG3) ? 1 : 0;
state = REG4 ? 6 : 7; break;
case 6: // basic block start for source line 653
REG3 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 655
REG3 = static_0_1_uniqnode;
REG4 = REG3(sp, stack, REG1, REG2, REG0);
REG5 = REG4[1]
REG4 = REG4[0]
state = REG5 ? 9 : 8; break;
case 8: // basic block start for source line 657
REG3 = 4294967292;
state = 2; break;
case 9: // basic block start for source line 659
REG0 = REG5[REG4 + 20];
REG3 = REG0;
state = 2; break;
} } }

function sfg_nodely1(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 4 : 1; break;
case 1: // basic block start for source line 673
REG3 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 669
return REG3;
case 3: // basic block start for source line 676
REG3 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 675
REG3 = REG2[REG1 + 0];
state = REG3 ? 5 : 3; break;
case 5: // basic block start for source line 678
REG3 = 1;
REG4 = (REG0 < REG3) ? 1 : 0;
state = REG4 ? 6 : 7; break;
case 6: // basic block start for source line 679
REG3 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 681
REG3 = static_0_1_uniqnode;
REG4 = REG3(sp, stack, REG1, REG2, REG0);
REG5 = REG4[1]
REG4 = REG4[0]
state = REG5 ? 9 : 8; break;
case 8: // basic block start for source line 683
REG3 = 4294967292;
state = 2; break;
case 9: // basic block start for source line 685
REG0 = REG5[REG4 + 22];
REG3 = REG0;
state = 2; break;
} } }

function sfg_nodexsize(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 4 : 1; break;
case 1: // basic block start for source line 699
REG3 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 695
return REG3;
case 3: // basic block start for source line 702
REG3 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 701
REG3 = REG2[REG1 + 0];
state = REG3 ? 5 : 3; break;
case 5: // basic block start for source line 704
REG3 = 1;
REG4 = (REG0 < REG3) ? 1 : 0;
state = REG4 ? 6 : 7; break;
case 6: // basic block start for source line 705
REG3 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 707
REG3 = static_0_1_uniqnode;
REG4 = REG3(sp, stack, REG1, REG2, REG0);
REG5 = REG4[1]
REG4 = REG4[0]
state = REG5 ? 9 : 8; break;
case 8: // basic block start for source line 709
REG3 = 4294967292;
state = 2; break;
case 9: // basic block start for source line 711
REG0 = REG5[REG4 + 1];
REG3 = REG0;
state = 2; break;
} } }

function sfg_nodeysize(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 4 : 1; break;
case 1: // basic block start for source line 725
REG3 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 721
return REG3;
case 3: // basic block start for source line 728
REG3 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 727
REG3 = REG2[REG1 + 0];
state = REG3 ? 5 : 3; break;
case 5: // basic block start for source line 730
REG3 = 1;
REG4 = (REG0 < REG3) ? 1 : 0;
state = REG4 ? 6 : 7; break;
case 6: // basic block start for source line 731
REG3 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 733
REG3 = static_0_1_uniqnode;
REG4 = REG3(sp, stack, REG1, REG2, REG0);
REG5 = REG4[1]
REG4 = REG4[0]
state = REG5 ? 9 : 8; break;
case 8: // basic block start for source line 735
REG3 = 4294967292;
state = 2; break;
case 9: // basic block start for source line 737
REG0 = REG5[REG4 + 2];
REG3 = REG0;
state = 2; break;
} } }

function sfg_xspacing(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 4 : 1; break;
case 1: // basic block start for source line 749
REG3 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 746
return REG3;
case 3: // basic block start for source line 752
REG3 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 751
REG3 = 1;
REG4 = (REG0 < REG3) ? 1 : 0;
state = REG4 ? 3 : 5; break;
case 5: // basic block start for source line 754
REG3 = REG2[REG1 + 0];
state = REG3 ? 6 : 7; break;
case 6: // basic block start for source line 755
REG3 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 757
REG2[REG1 + 13] = REG0;
REG3 = 0;
state = 2; break;
} } }

function sfg_yspacing(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 4 : 1; break;
case 1: // basic block start for source line 770
REG3 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 767
return REG3;
case 3: // basic block start for source line 773
REG3 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 772
REG3 = 1;
REG4 = (REG0 < REG3) ? 1 : 0;
state = REG4 ? 3 : 5; break;
case 5: // basic block start for source line 775
REG3 = REG2[REG1 + 0];
state = REG3 ? 6 : 7; break;
case 6: // basic block start for source line 776
REG3 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 778
REG2[REG1 + 14] = REG0;
REG3 = 0;
state = 2; break;
} } }

function sfg_maxx(fp, stack) {
var sp;
var REG0;
var REG1;
var REG2;
var REG3;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = static_0_0_maingraph;
REG2 = 0;
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
state = REG1 ? 4 : 1; break;
case 1: // basic block start for source line 790
REG2 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 787
return REG2;
case 3: // basic block start for source line 793
REG2 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 792
REG2 = REG1[REG0 + 0];
state = REG2 ? 5 : 3; break;
case 5: // basic block start for source line 795
REG3 = REG1[REG0 + 29];
REG2 = REG3;
state = 2; break;
} } }

function sfg_maxy(fp, stack) {
var sp;
var REG0;
var REG1;
var REG2;
var REG3;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = static_0_0_maingraph;
REG2 = 0;
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
state = REG1 ? 4 : 1; break;
case 1: // basic block start for source line 806
REG2 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 803
return REG2;
case 3: // basic block start for source line 809
REG2 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 808
REG2 = REG1[REG0 + 0];
state = REG2 ? 5 : 3; break;
case 5: // basic block start for source line 811
REG3 = REG1[REG0 + 30];
REG2 = REG3;
state = 2; break;
} } }

function sfg_nodemin(fp, stack) {
var sp;
var REG0;
var REG1;
var REG2;
var REG3;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = static_0_0_maingraph;
REG2 = 0;
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
state = REG1 ? 4 : 1; break;
case 1: // basic block start for source line 823
REG2 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 820
return REG2;
case 3: // basic block start for source line 826
REG2 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 825
REG2 = REG1[REG0 + 0];
state = REG2 ? 5 : 3; break;
case 5: // basic block start for source line 828
REG2 = REG1[REG0 + 15];
REG3 = REG1[REG0 + 16];
state = REG3 ? 7 : 6; break;
case 6: // basic block start for source line 829
REG2 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 831
REG3 = REG1[REG0 + 31];
REG2 = REG3;
state = 2; break;
} } }

function sfg_nodemax(fp, stack) {
var sp;
var REG0;
var REG1;
var REG2;
var REG3;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = static_0_0_maingraph;
REG2 = 0;
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
state = REG1 ? 4 : 1; break;
case 1: // basic block start for source line 843
REG2 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 840
return REG2;
case 3: // basic block start for source line 846
REG2 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 845
REG2 = REG1[REG0 + 0];
state = REG2 ? 5 : 3; break;
case 5: // basic block start for source line 848
REG2 = REG1[REG0 + 15];
REG3 = REG1[REG0 + 16];
state = REG3 ? 7 : 6; break;
case 6: // basic block start for source line 849
REG2 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 851
REG3 = REG1[REG0 + 32];
REG2 = REG3;
state = 2; break;
} } }

function sfg_edgemin(fp, stack) {
var sp;
var REG0;
var REG1;
var REG2;
var REG3;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = static_0_0_maingraph;
REG2 = 0;
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
state = REG1 ? 4 : 1; break;
case 1: // basic block start for source line 863
REG2 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 860
return REG2;
case 3: // basic block start for source line 866
REG2 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 865
REG2 = REG1[REG0 + 0];
state = REG2 ? 5 : 3; break;
case 5: // basic block start for source line 868
REG2 = REG1[REG0 + 19];
REG3 = REG1[REG0 + 20];
state = REG3 ? 7 : 6; break;
case 6: // basic block start for source line 869
REG2 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 871
REG3 = REG1[REG0 + 33];
REG2 = REG3;
state = 2; break;
} } }

function sfg_edgemax(fp, stack) {
var sp;
var REG0;
var REG1;
var REG2;
var REG3;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = static_0_0_maingraph;
REG2 = 0;
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
state = REG1 ? 4 : 1; break;
case 1: // basic block start for source line 883
REG2 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 880
return REG2;
case 3: // basic block start for source line 886
REG2 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 885
REG2 = REG1[REG0 + 0];
state = REG2 ? 5 : 3; break;
case 5: // basic block start for source line 888
REG2 = REG1[REG0 + 19];
REG3 = REG1[REG0 + 20];
state = REG3 ? 7 : 6; break;
case 6: // basic block start for source line 889
REG2 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 891
REG3 = REG1[REG0 + 34];
REG2 = REG3;
state = 2; break;
} } }

function sfg_nlevels(fp, stack) {
var sp;
var REG0;
var REG1;
var REG2;
var REG3;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = static_0_0_maingraph;
REG2 = 0;
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
state = REG1 ? 4 : 1; break;
case 1: // basic block start for source line 902
REG2 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 899
return REG2;
case 3: // basic block start for source line 905
REG2 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 904
REG2 = REG1[REG0 + 0];
state = REG2 ? 5 : 3; break;
case 5: // basic block start for source line 907
REG3 = REG1[REG0 + 5];
REG0 = 1;
REG1 = REG3 + REG0;
REG2 = REG1;
state = 2; break;
} } }

function sfg_nnodes(fp, stack) {
var sp;
var REG0;
var REG1;
var REG2;
var REG3;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = static_0_0_maingraph;
REG2 = 0;
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
state = REG1 ? 4 : 1; break;
case 1: // basic block start for source line 918
REG2 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 915
return REG2;
case 3: // basic block start for source line 921
REG2 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 920
REG2 = REG1[REG0 + 0];
state = REG2 ? 5 : 3; break;
case 5: // basic block start for source line 923
REG3 = REG1[REG0 + 2];
REG2 = REG3;
state = 2; break;
} } }

function sfg_nedges(fp, stack) {
var sp;
var REG0;
var REG1;
var REG2;
var REG3;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = static_0_0_maingraph;
REG2 = 0;
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
state = REG1 ? 4 : 1; break;
case 1: // basic block start for source line 934
REG2 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 931
return REG2;
case 3: // basic block start for source line 937
REG2 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 936
REG2 = REG1[REG0 + 0];
state = REG2 ? 5 : 3; break;
case 5: // basic block start for source line 939
REG3 = REG1[REG0 + 4];
REG2 = REG3;
state = 2; break;
} } }

function sfg_nodetype(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 4 : 1; break;
case 1: // basic block start for source line 954
REG3 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 949
return REG3;
case 3: // basic block start for source line 957
REG3 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 956
REG3 = REG2[REG1 + 0];
state = REG3 ? 5 : 3; break;
case 5: // basic block start for source line 959
REG3 = 1;
REG4 = (REG0 < REG3) ? 1 : 0;
state = REG4 ? 6 : 7; break;
case 6: // basic block start for source line 960
REG3 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 962
REG3 = static_0_1_uniqnode;
REG4 = REG3(sp, stack, REG1, REG2, REG0);
REG5 = REG4[1]
REG4 = REG4[0]
state = REG5 ? 9 : 8; break;
case 8: // basic block start for source line 964
REG3 = 4294967292;
state = 2; break;
case 9: // basic block start for source line 966
REG0 = REG5[REG4 + 5];
state = REG0 ? 10 : 12; break;
case 10: // basic block start for source line 967
REG6 = 2;
state = 11; break;
case 11: // basic block start for source line 973
REG3 = REG6;
state = 2; break;
case 12: // basic block start for source line 968
REG0 = REG5[REG4 + 6];
REG1 = 1;
REG2 = 3;
if (REG0) { REG3 = REG2; } else { REG3 = REG1; }
REG6 = REG3;
state = 11; break;
} } }

function sfg_nodeselfedges(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 4 : 1; break;
case 1: // basic block start for source line 987
REG3 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 983
return REG3;
case 3: // basic block start for source line 990
REG3 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 989
REG3 = REG2[REG1 + 0];
state = REG3 ? 5 : 3; break;
case 5: // basic block start for source line 992
REG3 = 1;
REG4 = (REG0 < REG3) ? 1 : 0;
state = REG4 ? 6 : 7; break;
case 6: // basic block start for source line 993
REG3 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 995
REG3 = static_0_1_uniqnode;
REG4 = REG3(sp, stack, REG1, REG2, REG0);
REG5 = REG4[1]
REG4 = REG4[0]
state = REG5 ? 9 : 8; break;
case 8: // basic block start for source line 997
REG3 = 4294967292;
state = 2; break;
case 9: // basic block start for source line 999
REG0 = REG5[REG4 + 8];
REG3 = REG0;
state = 2; break;
} } }

function sfg_nodeindegree(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 4 : 1; break;
case 1: // basic block start for source line 1013
REG3 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 1009
return REG3;
case 3: // basic block start for source line 1016
REG3 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 1015
REG3 = REG2[REG1 + 0];
state = REG3 ? 5 : 3; break;
case 5: // basic block start for source line 1018
REG3 = 1;
REG4 = (REG0 < REG3) ? 1 : 0;
state = REG4 ? 6 : 7; break;
case 6: // basic block start for source line 1019
REG3 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 1021
REG3 = static_0_1_uniqnode;
REG4 = REG3(sp, stack, REG1, REG2, REG0);
REG5 = REG4[1]
REG4 = REG4[0]
state = REG5 ? 9 : 8; break;
case 8: // basic block start for source line 1023
REG3 = 4294967292;
state = 2; break;
case 9: // basic block start for source line 1025
REG0 = REG5[REG4 + 11];
REG3 = REG0;
state = 2; break;
} } }

function sfg_nodeoutdegree(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 4 : 1; break;
case 1: // basic block start for source line 1039
REG3 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 1035
return REG3;
case 3: // basic block start for source line 1042
REG3 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 1041
REG3 = REG2[REG1 + 0];
state = REG3 ? 5 : 3; break;
case 5: // basic block start for source line 1044
REG3 = 1;
REG4 = (REG0 < REG3) ? 1 : 0;
state = REG4 ? 6 : 7; break;
case 6: // basic block start for source line 1045
REG3 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 1047
REG3 = static_0_1_uniqnode;
REG4 = REG3(sp, stack, REG1, REG2, REG0);
REG5 = REG4[1]
REG4 = REG4[0]
state = REG5 ? 9 : 8; break;
case 8: // basic block start for source line 1049
REG3 = 4294967292;
state = 2; break;
case 9: // basic block start for source line 1051
REG0 = REG5[REG4 + 12];
REG3 = REG0;
state = 2; break;
} } }

function sfg_nodeenum(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 4 : 1; break;
case 1: // basic block start for source line 1066
REG3 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 1062
return REG3;
case 3: // basic block start for source line 1069
REG3 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 1068
REG3 = REG2[REG1 + 0];
state = REG3 ? 5 : 3; break;
case 5: // basic block start for source line 1071
REG3 = 1;
REG4 = (REG0 < REG3) ? 1 : 0;
state = REG4 ? 6 : 7; break;
case 6: // basic block start for source line 1072
REG3 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 1074
REG3 = static_0_1_uniqnode;
REG4 = REG3(sp, stack, REG1, REG2, REG0);
REG5 = REG4[1]
REG4 = REG4[0]
state = REG5 ? 9 : 8; break;
case 8: // basic block start for source line 1076
REG3 = 4294967292;
state = 2; break;
case 9: // basic block start for source line 1078
REG0 = REG5[REG4 + 6];
state = REG0 ? 11 : 10; break;
case 10: // basic block start for source line 1079
REG3 = 4294967291;
state = 2; break;
case 11: // basic block start for source line 1081
REG0 = REG5[REG4 + 7];
REG3 = REG0;
state = 2; break;
} } }

function sfg_nodedata(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 4 : 1; break;
case 1: // basic block start for source line 1095
REG3 = 0;
state = 2; break;
case 2: // basic block start for source line 1091
return [REG3, REG4];
case 3: // basic block start for source line 1098
REG3 = 0;
state = 2; break;
case 4: // basic block start for source line 1097
REG3 = REG2[REG1 + 0];
state = REG3 ? 5 : 3; break;
case 5: // basic block start for source line 1100
REG3 = 1;
REG4 = (REG0 < REG3) ? 1 : 0;
state = REG4 ? 6 : 7; break;
case 6: // basic block start for source line 1101
REG3 = 0;
state = 2; break;
case 7: // basic block start for source line 1103
REG3 = static_0_1_uniqnode;
REG5 = REG3(sp, stack, REG1, REG2, REG0);
REG6 = REG5[1]
REG5 = REG5[0]
state = REG6 ? 9 : 8; break;
case 8: // basic block start for source line 1105
REG3 = 0;
state = 2; break;
case 9: // basic block start for source line 1107
REG0 = REG6[REG5 + 14];
REG1 = REG6[REG5 + 15];
REG3 = REG0;
REG4 = REG1;
state = 2; break;
} } }

function sfg_setnodedata(fp, stack, REG0, REG1) {
var sp;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG6 = static_0_0_maingraph;
REG5 = 0;
REG3 = REG6[REG5 + 0];
REG4 = REG6[REG5 + 1];
state = REG4 ? 4 : 1; break;
case 1: // basic block start for source line 1121
REG5 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 1117
return REG5;
case 3: // basic block start for source line 1124
REG5 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 1123
REG5 = REG4[REG3 + 0];
state = REG5 ? 5 : 3; break;
case 5: // basic block start for source line 1126
REG5 = 1;
REG6 = (REG0 < REG5) ? 1 : 0;
state = REG6 ? 6 : 7; break;
case 6: // basic block start for source line 1127
REG5 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 1129
REG5 = static_0_1_uniqnode;
REG6 = REG5(sp, stack, REG3, REG4, REG0);
REG7 = REG6[1]
REG6 = REG6[0]
state = REG7 ? 9 : 8; break;
case 8: // basic block start for source line 1131
REG5 = 4294967292;
state = 2; break;
case 9: // basic block start for source line 1133
REG7[REG6 + 14] = REG1;
REG7[REG6 + 15] = REG2;
REG5 = 0;
state = 2; break;
} } }

function sfg_edgefrom(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 4 : 1; break;
case 1: // basic block start for source line 1213
REG3 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 1209
return REG3;
case 3: // basic block start for source line 1216
REG3 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 1215
REG3 = REG2[REG1 + 0];
state = REG3 ? 5 : 3; break;
case 5: // basic block start for source line 1218
REG1 = 1;
REG2 = (REG0 < REG1) ? 1 : 0;
state = REG2 ? 6 : 7; break;
case 6: // basic block start for source line 1219
REG3 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 1221
REG1 = static_0_23_findedge;
REG4 = REG1(sp, stack, REG0);
REG5 = REG4[1]
REG4 = REG4[0]
state = REG5 ? 9 : 8; break;
case 8: // basic block start for source line 1223
REG3 = 4294967292;
state = 2; break;
case 9: // basic block start for source line 1225
REG0 = REG5[REG4 + 1];
REG1 = REG5[REG4 + 2];
REG2 = REG1[REG0 + 0];
REG3 = REG2;
state = 2; break;
} } }

function sfg_edgeto(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 4 : 1; break;
case 1: // basic block start for source line 1239
REG3 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 1235
return REG3;
case 3: // basic block start for source line 1242
REG3 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 1241
REG3 = REG2[REG1 + 0];
state = REG3 ? 5 : 3; break;
case 5: // basic block start for source line 1244
REG1 = 1;
REG2 = (REG0 < REG1) ? 1 : 0;
state = REG2 ? 6 : 7; break;
case 6: // basic block start for source line 1245
REG3 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 1247
REG1 = static_0_23_findedge;
REG4 = REG1(sp, stack, REG0);
REG5 = REG4[1]
REG4 = REG4[0]
state = REG5 ? 9 : 8; break;
case 8: // basic block start for source line 1249
REG3 = 4294967292;
state = 2; break;
case 9: // basic block start for source line 1251
REG0 = REG5[REG4 + 2];
REG1 = REG5[REG4 + 3];
REG2 = REG1[REG0 + 0];
REG3 = REG2;
state = 2; break;
} } }

function sfg_edgetype(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 4 : 1; break;
case 1: // basic block start for source line 1266
REG3 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 1261
return REG3;
case 3: // basic block start for source line 1269
REG3 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 1268
REG3 = REG2[REG1 + 0];
state = REG3 ? 5 : 3; break;
case 5: // basic block start for source line 1271
REG1 = 1;
REG2 = (REG0 < REG1) ? 1 : 0;
state = REG2 ? 6 : 7; break;
case 6: // basic block start for source line 1272
REG3 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 1274
REG1 = static_0_23_findedge;
REG4 = REG1(sp, stack, REG0);
REG5 = REG4[1]
REG4 = REG4[0]
state = REG5 ? 9 : 8; break;
case 8: // basic block start for source line 1276
REG3 = 4294967292;
state = 2; break;
case 9: // basic block start for source line 1278
REG0 = REG5[REG4 + 1];
REG1 = REG5[REG4 + 2];
REG2 = REG1[REG0 + 0];
REG0 = REG5[REG4 + 2];
REG1 = REG5[REG4 + 3];
REG3 = REG1[REG0 + 0];
REG0 = (REG2 == REG3) ? 1 : 0;
state = REG0 ? 10 : 12; break;
case 10: // basic block start for source line 1279
REG6 = 2;
state = 11; break;
case 11: // basic block start for source line 1285
REG3 = REG6;
state = 2; break;
case 12: // basic block start for source line 1280
REG0 = REG5[REG4 + 7];
REG1 = 1;
REG2 = 3;
if (REG0) { REG3 = REG2; } else { REG3 = REG1; }
REG6 = REG3;
state = 11; break;
} } }

function sfg_edgerev(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 4 : 1; break;
case 1: // basic block start for source line 1299
REG3 = 4294967295;
state = 2; break;
case 2: // basic block start for source line 1295
return REG3;
case 3: // basic block start for source line 1302
REG3 = 4294967294;
state = 2; break;
case 4: // basic block start for source line 1301
REG3 = REG2[REG1 + 0];
state = REG3 ? 5 : 3; break;
case 5: // basic block start for source line 1304
REG1 = 1;
REG2 = (REG0 < REG1) ? 1 : 0;
state = REG2 ? 6 : 7; break;
case 6: // basic block start for source line 1305
REG3 = 4294967293;
state = 2; break;
case 7: // basic block start for source line 1307
REG1 = static_0_23_findedge;
REG4 = REG1(sp, stack, REG0);
REG5 = REG4[1]
REG4 = REG4[0]
state = REG5 ? 9 : 8; break;
case 8: // basic block start for source line 1309
REG3 = 4294967292;
state = 2; break;
case 9: // basic block start for source line 1311
REG0 = REG5[REG4 + 6];
REG3 = REG0;
state = 2; break;
} } }

function static_0_25_uniqnode(fp, stack, REG0, REG1) {
var sp;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = REG1[REG0 + 15];
REG4 = REG1[REG0 + 16];
state = REG4 ? 5 : 1; break;
case 1: // basic block start for source line 1375
REG5 = 0;
state = 2; break;
case 2: // basic block start for source line 1370
return [REG5, REG6];
case 3: // basic block start for source line 1385
REG5 = REG11;
REG6 = REG12;
state = 2; break;
case 4: // basic block start for source line 1378
REG11 = 0;
state = REG8 ? 7 : 3; break;
case 5: // basic block start for source line 1377
REG7 = REG3;
REG8 = REG4;
state = 4; break;
case 6: // basic block start for source line 1383
REG0 = REG8[REG7 + 1];
REG1 = REG8[REG7 + 2];
REG7 = REG0;
REG8 = REG1;
state = 4; break;
case 7: // basic block start for source line 1379
REG9 = REG8[REG7 + 0];
REG10 = REG8[REG7 + 1];
REG0 = REG10[REG9 + 0];
REG1 = (REG0 == REG2) ? 1 : 0;
state = REG1 ? 8 : 6; break;
case 8: // basic block start for source line 1380
REG11 = REG9;
REG12 = REG10;
state = 3; break;
} } }

function static_0_26_uniqnode_add(fp, stack, REG0, REG1) {
var sp;
var REG2;
var REG3;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
return;
} } }

function static_0_27_clear_nodelist(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = REG1[REG0 + 15];
REG5 = REG1[REG0 + 16];
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 1: // basic block start for source line 1404
state = REG3 ? 2 : 3; break;
case 2: // basic block start for source line 1405
REG4 = REG3[REG2 + 1];
REG5 = REG3[REG2 + 2];
REG6 = REG3[REG2 + 0];
REG7 = REG3[REG2 + 1];
REG8 = free;
REG8(sp, stack, REG6, REG7);
REG6 = 0;
REG3[REG2 + 0] = REG6;
REG6 = free;
REG6(sp, stack, REG2, REG3);
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 3: // basic block start for source line 1412
REG2 = 0;
REG1[REG0 + 15] = REG2;
REG2 = 0;
REG1[REG0 + 16] = REG2;
REG2 = 0;
REG1[REG0 + 1] = REG2;
REG2 = 0;
REG1[REG0 + 2] = REG2;
return;
} } }

function static_0_28_clear_edgelist(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = REG1[REG0 + 19];
REG5 = REG1[REG0 + 20];
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 1: // basic block start for source line 1425
state = REG3 ? 2 : 3; break;
case 2: // basic block start for source line 1426
REG4 = REG3[REG2 + 1];
REG5 = REG3[REG2 + 2];
REG6 = REG3[REG2 + 0];
REG7 = REG3[REG2 + 1];
REG8 = free;
REG8(sp, stack, REG6, REG7);
REG6 = 0;
REG3[REG2 + 0] = REG6;
REG6 = free;
REG6(sp, stack, REG2, REG3);
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 3: // basic block start for source line 1433
REG2 = 0;
REG1[REG0 + 19] = REG2;
REG2 = 0;
REG1[REG0 + 20] = REG2;
REG2 = 0;
REG1[REG0 + 4] = REG2;
REG2 = 0;
REG1[REG0 + 3] = REG2;
return;
} } }

function static_0_29_prep(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = REG1[REG0 + 19];
REG5 = REG1[REG0 + 20];
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 1: // basic block start for source line 1445
state = REG3 ? 2 : 3; break;
case 2: // basic block start for source line 1447
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
REG4 = REG1[REG0 + 1];
REG5 = REG1[REG0 + 2];
REG0 = REG5[REG4 + 12];
REG1 = 1;
REG6 = REG0 + REG1;
REG5[REG4 + 12] = REG6;
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
REG4 = REG1[REG0 + 2];
REG5 = REG1[REG0 + 3];
REG0 = REG5[REG4 + 11];
REG1 = 1;
REG6 = REG0 + REG1;
REG5[REG4 + 11] = REG6;
REG0 = REG3[REG2 + 1];
REG1 = REG3[REG2 + 2];
REG2 = REG0;
REG3 = REG1;
state = 1; break;
case 3: // basic block start for source line 1441
return;
} } }

function static_0_30_reorg(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var REG16;
var REG17;
var REG18;
var REG19;
var REG20;
var REG21;
var REG22;
var REG23;
var REG24;
var REG25;
var REG26;
var REG27;
var REG28;
var REG29;
var REG30;
var REG31;
var REG32;
var REG33;
var REG34;
var REG35;
var REG36;
var REG37;
var REG38;
var REG39;
var REG40;
var REG41;
var REG42;
var REG43;
var REG44;
var REG45;
var REG46;
var REG47;
var REG48;
var REG49;
var REG50;
var REG51;
var REG52;
var REG53;
var REG54;
var REG55;
var REG56;
var REG57;
var REG58;
var REG59;
var REG60;
var REG61;
var REG62;
var REG63;
var REG64;
var REG65;
var REG66;
var REG67;
var REG68;
var REG69;
var REG70;
var REG71;
var REG72;
var REG73;
var REG74;
var REG75;
var REG76;
var REG77;
var REG78;
var REG79;
var REG80;
var REG81;
var REG82;
var REG83;
var REG84;
var REG85;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG2 = REG1[REG0 + 15];
REG3 = REG1[REG0 + 16];
state = REG3 ? 12 : 1; break;
case 1: // basic block start for source line 1456
return;
case 2: // basic block start for source line 1556
REG1[REG0 + 15] = REG64;
REG1[REG0 + 16] = REG65;
REG1[REG0 + 16] = REG66;
REG1[REG0 + 17] = REG67;
state = 1; break;
case 3: // basic block start for source line 1548
state = REG85 ? 45 : 2; break;
case 4: // basic block start for source line 1547
REG2 = REG1[REG0 + 15];
REG3 = REG1[REG0 + 16];
REG84 = REG2;
REG85 = REG3;
state = 3; break;
case 5: // basic block start for source line 1528
state = REG69 ? 38 : 4; break;
case 6: // basic block start for source line 1527
REG2 = REG1[REG0 + 15];
REG3 = REG1[REG0 + 16];
REG68 = REG2;
REG69 = REG3;
REG64 = REG44;
REG65 = REG45;
REG66 = REG46;
REG67 = REG47;
state = 5; break;
case 7: // basic block start for source line 1509
state = REG49 ? 30 : 6; break;
case 8: // basic block start for source line 1508
REG2 = REG1[REG0 + 15];
REG3 = REG1[REG0 + 16];
REG48 = REG2;
REG49 = REG3;
REG44 = REG24;
REG45 = REG25;
REG46 = REG26;
REG47 = REG27;
state = 7; break;
case 9: // basic block start for source line 1490
state = REG29 ? 22 : 8; break;
case 10: // basic block start for source line 1489
REG2 = REG1[REG0 + 15];
REG3 = REG1[REG0 + 16];
REG28 = REG2;
REG29 = REG3;
REG24 = REG4;
REG25 = REG5;
REG26 = REG6;
REG27 = REG7;
state = 9; break;
case 11: // basic block start for source line 1471
state = REG9 ? 14 : 10; break;
case 12: // basic block start for source line 1471
REG8 = REG2;
REG9 = REG3;
REG4 = 0;
REG6 = 0;
state = 11; break;
case 13: // basic block start for source line 1486
REG2 = REG9[REG8 + 1];
REG3 = REG9[REG8 + 2];
REG8 = REG2;
REG9 = REG3;
REG4 = REG10;
REG5 = REG11;
REG6 = REG12;
REG7 = REG13;
state = 11; break;
case 14: // basic block start for source line 1473
REG14 = REG9[REG8 + 0];
REG15 = REG9[REG8 + 1];
REG2 = REG15[REG14 + 11];
REG10 = REG4;
REG11 = REG5;
REG12 = REG6;
REG13 = REG7;
state = REG2 ? 13 : 15; break;
case 15: // basic block start for source line 1473
REG2 = REG15[REG14 + 12];
REG10 = REG4;
REG11 = REG5;
REG12 = REG6;
REG13 = REG7;
state = REG2 ? 13 : 16; break;
case 16: // basic block start for source line 1474
REG2 = 2;
REG3 = 1;
REG10 = calloc;
REG11 = REG10(sp, stack, REG3, REG2);
REG12 = REG11[1]
REG11 = REG11[0]
REG20 = REG11;
REG21 = REG12;
REG16 = REG4;
REG17 = REG5;
REG18 = REG6;
REG19 = REG7;
state = REG21 ? 17 : 20; break;
case 17: // basic block start for source line 1476
REG2 = REG9[REG8 + 0];
REG3 = REG9[REG8 + 1];
REG21[REG20 + 0] = REG2;
REG21[REG20 + 1] = REG3;
if (REG5) { REG22 = REG4; REG23 = REG5; } else { REG22 = REG20; REG23 = REG21; }
state = REG5 ? 19 : 18; break;
case 18: // basic block start for source line 1477
REG16 = REG22;
REG17 = REG23;
REG18 = REG20;
REG19 = REG21;
state = 20; break;
case 19: // basic block start for source line 1481
REG7[REG6 + 1] = REG20;
REG7[REG6 + 2] = REG21;
state = 18; break;
case 20: // basic block start for source line 1475
REG10 = REG16;
REG11 = REG17;
REG12 = REG18;
REG13 = REG19;
state = 13; break;
case 21: // basic block start for source line 1505
REG2 = REG29[REG28 + 1];
REG3 = REG29[REG28 + 2];
REG28 = REG2;
REG29 = REG3;
REG24 = REG30;
REG25 = REG31;
REG26 = REG32;
REG27 = REG33;
state = 9; break;
case 22: // basic block start for source line 1492
REG34 = REG29[REG28 + 0];
REG35 = REG29[REG28 + 1];
REG2 = REG35[REG34 + 11];
REG30 = REG24;
REG31 = REG25;
REG32 = REG26;
REG33 = REG27;
state = REG2 ? 21 : 23; break;
case 23: // basic block start for source line 1492
REG2 = REG35[REG34 + 12];
REG30 = REG24;
REG31 = REG25;
REG32 = REG26;
REG33 = REG27;
state = REG2 ? 24 : 21; break;
case 24: // basic block start for source line 1493
REG2 = 2;
REG3 = 1;
REG4 = calloc;
REG5 = REG4(sp, stack, REG3, REG2);
REG6 = REG5[1]
REG5 = REG5[0]
REG40 = REG5;
REG41 = REG6;
REG36 = REG24;
REG37 = REG25;
REG38 = REG26;
REG39 = REG27;
state = REG41 ? 25 : 28; break;
case 25: // basic block start for source line 1495
REG2 = REG29[REG28 + 0];
REG3 = REG29[REG28 + 1];
REG41[REG40 + 0] = REG2;
REG41[REG40 + 1] = REG3;
if (REG25) { REG42 = REG24; REG43 = REG25; } else { REG42 = REG40; REG43 = REG41; }
state = REG25 ? 27 : 26; break;
case 26: // basic block start for source line 1496
REG36 = REG42;
REG37 = REG43;
REG38 = REG40;
REG39 = REG41;
state = 28; break;
case 27: // basic block start for source line 1500
REG27[REG26 + 1] = REG40;
REG27[REG26 + 2] = REG41;
state = 26; break;
case 28: // basic block start for source line 1494
REG30 = REG36;
REG31 = REG37;
REG32 = REG38;
REG33 = REG39;
state = 21; break;
case 29: // basic block start for source line 1524
REG2 = REG49[REG48 + 1];
REG3 = REG49[REG48 + 2];
REG48 = REG2;
REG49 = REG3;
REG44 = REG50;
REG45 = REG51;
REG46 = REG52;
REG47 = REG53;
state = 7; break;
case 30: // basic block start for source line 1511
REG54 = REG49[REG48 + 0];
REG55 = REG49[REG48 + 1];
REG2 = REG55[REG54 + 11];
REG50 = REG44;
REG51 = REG45;
REG52 = REG46;
REG53 = REG47;
state = REG2 ? 31 : 29; break;
case 31: // basic block start for source line 1511
REG2 = REG55[REG54 + 12];
REG50 = REG44;
REG51 = REG45;
REG52 = REG46;
REG53 = REG47;
state = REG2 ? 32 : 29; break;
case 32: // basic block start for source line 1512
REG2 = 2;
REG3 = 1;
REG4 = calloc;
REG5 = REG4(sp, stack, REG3, REG2);
REG6 = REG5[1]
REG5 = REG5[0]
REG60 = REG5;
REG61 = REG6;
REG56 = REG44;
REG57 = REG45;
REG58 = REG46;
REG59 = REG47;
state = REG61 ? 33 : 36; break;
case 33: // basic block start for source line 1514
REG2 = REG49[REG48 + 0];
REG3 = REG49[REG48 + 1];
REG61[REG60 + 0] = REG2;
REG61[REG60 + 1] = REG3;
if (REG45) { REG62 = REG44; REG63 = REG45; } else { REG62 = REG60; REG63 = REG61; }
state = REG45 ? 35 : 34; break;
case 34: // basic block start for source line 1515
REG56 = REG62;
REG57 = REG63;
REG58 = REG60;
REG59 = REG61;
state = 36; break;
case 35: // basic block start for source line 1519
REG47[REG46 + 1] = REG60;
REG47[REG46 + 2] = REG61;
state = 34; break;
case 36: // basic block start for source line 1513
REG50 = REG56;
REG51 = REG57;
REG52 = REG58;
REG53 = REG59;
state = 29; break;
case 37: // basic block start for source line 1543
REG2 = REG69[REG68 + 1];
REG3 = REG69[REG68 + 2];
REG68 = REG2;
REG69 = REG3;
REG64 = REG74;
REG65 = REG75;
REG66 = REG70;
REG67 = REG71;
state = 5; break;
case 38: // basic block start for source line 1530
REG72 = REG69[REG68 + 0];
REG73 = REG69[REG68 + 1];
REG2 = REG73[REG72 + 11];
REG74 = REG64;
REG75 = REG65;
REG70 = REG66;
REG71 = REG67;
state = REG2 ? 39 : 37; break;
case 39: // basic block start for source line 1530
REG2 = REG73[REG72 + 12];
REG74 = REG64;
REG75 = REG65;
REG70 = REG66;
REG71 = REG67;
state = REG2 ? 37 : 40; break;
case 40: // basic block start for source line 1531
REG2 = 2;
REG3 = 1;
REG4 = calloc;
REG5 = REG4(sp, stack, REG3, REG2);
REG6 = REG5[1]
REG5 = REG5[0]
REG78 = REG5;
REG79 = REG6;
REG80 = REG64;
REG81 = REG65;
REG76 = REG66;
REG77 = REG67;
state = REG79 ? 41 : 44; break;
case 41: // basic block start for source line 1533
REG2 = REG69[REG68 + 0];
REG3 = REG69[REG68 + 1];
REG79[REG78 + 0] = REG2;
REG79[REG78 + 1] = REG3;
if (REG65) { REG82 = REG64; REG83 = REG65; } else { REG82 = REG78; REG83 = REG79; }
state = REG65 ? 43 : 42; break;
case 42: // basic block start for source line 1534
REG80 = REG82;
REG81 = REG83;
REG76 = REG78;
REG77 = REG79;
state = 44; break;
case 43: // basic block start for source line 1538
REG67[REG66 + 1] = REG78;
REG67[REG66 + 2] = REG79;
state = 42; break;
case 44: // basic block start for source line 1532
REG74 = REG80;
REG75 = REG81;
REG70 = REG76;
REG71 = REG77;
state = 37; break;
case 45: // basic block start for source line 1549
REG2 = REG85[REG84 + 1];
REG3 = REG85[REG84 + 2];
REG4 = free;
REG4(sp, stack, REG84, REG85);
REG84 = REG2;
REG85 = REG3;
state = 3; break;
} } }

function static_0_31_decycle3(fp, stack, REG0, REG1, REG2, REG3) {
var sp;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var REG16;
var REG17;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG7 = REG3[REG2 + 9];
state = REG7 ? 1 : 7; break;
case 1: // basic block start for source line 1575
REG0 = REG3[REG2 + 16];
REG1 = (REG4 > REG0) ? 1 : 0;
state = REG1 ? 2 : 3; break;
case 2: // basic block start for source line 1576
REG3[REG2 + 16] = REG4;
state = 3; break;
case 3: // basic block start for source line 1578
REG7 = 0;
state = 4; break;
case 4: // basic block start for source line 1563
return REG7;
case 5: // basic block start for source line 1612
REG0 = 0;
REG3[REG2 + 10] = REG0;
REG7 = REG10;
state = 4; break;
case 6: // basic block start for source line 1588
state = REG9 ? 12 : 5; break;
case 7: // basic block start for source line 1581
REG3[REG2 + 16] = REG4;
REG7 = 1;
REG3[REG2 + 9] = REG7;
REG7 = 1;
REG3[REG2 + 10] = REG7;
REG7 = REG3[REG2 + 25];
REG11 = REG3[REG2 + 26];
REG8 = REG7;
REG9 = REG11;
REG10 = 0;
state = 6; break;
case 8: // basic block start for source line 1608
REG7 = REG9[REG8 + 1];
REG11 = REG9[REG8 + 2];
REG8 = REG7;
REG9 = REG11;
REG10 = REG16;
state = 6; break;
case 9: // basic block start for source line 1598
REG16 = REG17;
state = 8; break;
case 10: // basic block start for source line 1599
REG7 = 0;
REG12[REG11 + 6] = REG7;
state = 9; break;
case 11: // basic block start for source line 1593
REG7 = 1;
REG17 = REG10 + REG7;
REG7 = REG12[REG11 + 1];
REG10 = REG12[REG11 + 2];
REG12[REG11 + 2] = REG7;
REG12[REG11 + 3] = REG10;
REG12[REG11 + 1] = REG13;
REG12[REG11 + 2] = REG14;
REG7 = REG12[REG11 + 6];
state = REG7 ? 10 : 16; break;
case 12: // basic block start for source line 1589
REG11 = REG9[REG8 + 0];
REG12 = REG9[REG8 + 1];
REG13 = REG12[REG11 + 2];
REG14 = REG12[REG11 + 3];
REG7 = REG14[REG13 + 10];
state = REG7 ? 11 : 13; break;
case 13: // basic block start for source line 1604
REG7 = REG14[REG13 + 9];
REG15 = REG10;
state = REG7 ? 15 : 14; break;
case 14: // basic block start for source line 1605
REG7 = 1;
REG11 = REG4 + REG7;
REG7 = static_0_31_decycle3;
REG12 = REG7(sp, stack, REG0, REG1, REG13, REG14, REG11, REG5, REG6);
REG7 = REG10 + REG12;
REG15 = REG7;
state = 15; break;
case 15: // basic block start for source line 1604
REG16 = REG15;
state = 8; break;
case 16: // basic block start for source line 1601
REG7 = 1;
REG12[REG11 + 6] = REG7;
state = 9; break;
} } }

function static_0_32_uncycle(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var REG16;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_10_clear_stlist_all;
REG4(sp, stack, REG0, REG1);
REG4 = static_0_8_make_stlist;
REG4(sp, stack, REG0, REG1);
REG4 = 0;
REG1[REG0 + 5] = REG4;
REG4 = REG1[REG0 + 15];
REG5 = REG1[REG0 + 16];
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 1: // basic block start for source line 1627
state = REG3 ? 2 : 3; break;
case 2: // basic block start for source line 1628
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG6 = 4294967295;
REG5[REG4 + 16] = REG6;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG6 = 0;
REG5[REG4 + 9] = REG6;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG6 = 0;
REG5[REG4 + 10] = REG6;
REG4 = REG3[REG2 + 1];
REG5 = REG3[REG2 + 2];
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 3: // basic block start for source line 1635
REG2 = REG1[REG0 + 15];
REG3 = REG1[REG0 + 16];
REG4 = REG2;
REG5 = REG3;
REG6 = 0;
state = 4; break;
case 4: // basic block start for source line 1637
state = REG5 ? 6 : 11; break;
case 5: // basic block start for source line 1645
REG2 = REG5[REG4 + 1];
REG3 = REG5[REG4 + 2];
REG4 = REG2;
REG5 = REG3;
REG6 = REG9;
state = 4; break;
case 6: // basic block start for source line 1639
REG7 = REG5[REG4 + 0];
REG8 = REG5[REG4 + 1];
REG2 = REG8[REG7 + 11];
REG9 = REG6;
state = REG2 ? 5 : 7; break;
case 7: // basic block start for source line 1639
REG2 = REG8[REG7 + 12];
REG9 = REG6;
state = REG2 ? 8 : 5; break;
case 8: // basic block start for source line 1640
REG2 = REG8[REG7 + 9];
REG10 = REG6;
state = REG2 ? 10 : 9; break;
case 9: // basic block start for source line 1642
REG9 = 0;
REG11 = static_0_31_decycle3;
REG12 = REG11(sp, stack, REG0, REG1, REG7, REG8, REG9, REG2, REG3);
REG7 = REG6 + REG12;
REG10 = REG7;
state = 10; break;
case 10: // basic block start for source line 1640
REG9 = REG10;
state = 5; break;
case 11: // basic block start for source line 1649
REG2 = REG1[REG0 + 15];
REG3 = REG1[REG0 + 16];
REG11 = REG2;
REG12 = REG3;
REG13 = REG6;
state = 12; break;
case 12: // basic block start for source line 1650
state = REG12 ? 14 : 16; break;
case 13: // basic block start for source line 1656
REG2 = REG12[REG11 + 1];
REG3 = REG12[REG11 + 2];
REG11 = REG2;
REG12 = REG3;
REG13 = REG16;
state = 12; break;
case 14: // basic block start for source line 1652
REG14 = REG12[REG11 + 0];
REG15 = REG12[REG11 + 1];
REG2 = REG15[REG14 + 16];
REG3 = 4294967295;
REG4 = (REG2 == REG3) ? 1 : 0;
REG16 = REG13;
state = REG4 ? 15 : 13; break;
case 15: // basic block start for source line 1654
REG4 = 0;
REG5 = static_0_31_decycle3;
REG6 = REG5(sp, stack, REG0, REG1, REG14, REG15, REG4, REG2, REG3);
REG4 = REG13 + REG6;
REG16 = REG4;
state = 13; break;
case 16: // basic block start for source line 1658
state = REG13 ? 17 : 18; break;
case 17: // basic block start for source line 1660
REG2 = static_0_10_clear_stlist_all;
REG2(sp, stack, REG0, REG1);
REG2 = static_0_8_make_stlist;
REG2(sp, stack, REG0, REG1);
state = 18; break;
case 18: // basic block start for source line 1617
return;
} } }

function static_0_33_make_stlist(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = REG1[REG0 + 15];
REG5 = REG1[REG0 + 16];
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 1: // basic block start for source line 1678
state = REG3 ? 2 : 3; break;
case 2: // basic block start for source line 1680
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG6 = 0;
REG5[REG4 + 25] = REG6;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG6 = 0;
REG5[REG4 + 26] = REG6;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG6 = 0;
REG5[REG4 + 27] = REG6;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG6 = 0;
REG5[REG4 + 28] = REG6;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG6 = 0;
REG5[REG4 + 11] = REG6;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG6 = 0;
REG5[REG4 + 12] = REG6;
REG4 = REG3[REG2 + 1];
REG5 = REG3[REG2 + 2];
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 3: // basic block start for source line 1689
REG2 = REG1[REG0 + 19];
REG3 = REG1[REG0 + 20];
REG4 = REG2;
REG5 = REG3;
state = 4; break;
case 4: // basic block start for source line 1690
state = REG5 ? 11 : 12; break;
case 5: // basic block start for source line 1726
REG0 = REG11[REG10 + 11];
REG1 = 1;
REG2 = REG0 + REG1;
REG11[REG10 + 11] = REG2;
REG0 = REG5[REG4 + 1];
REG1 = REG5[REG4 + 2];
REG4 = REG0;
REG5 = REG1;
state = 4; break;
case 6: // basic block start for source line 1719
REG11[REG10 + 27] = REG14;
REG11[REG10 + 28] = REG15;
REG11[REG10 + 28] = REG14;
REG11[REG10 + 29] = REG15;
state = 5; break;
case 7: // basic block start for source line 1716
REG15[REG14 + 0] = REG6;
REG15[REG14 + 1] = REG7;
REG0 = REG11[REG10 + 27];
REG1 = REG11[REG10 + 28];
state = REG1 ? 14 : 6; break;
case 8: // basic block start for source line 1710
REG0 = REG9[REG8 + 12];
REG1 = 1;
REG2 = REG0 + REG1;
REG9[REG8 + 12] = REG2;
REG0 = 2;
REG1 = 1;
REG2 = calloc;
REG3 = REG2(sp, stack, REG1, REG0);
REG8 = REG3[1]
REG3 = REG3[0]
REG14 = REG3;
REG15 = REG8;
state = REG15 ? 7 : 12; break;
case 9: // basic block start for source line 1703
REG9[REG8 + 25] = REG12;
REG9[REG8 + 26] = REG13;
REG9[REG8 + 26] = REG12;
REG9[REG8 + 27] = REG13;
state = 8; break;
case 10: // basic block start for source line 1700
REG13[REG12 + 0] = REG6;
REG13[REG12 + 1] = REG7;
REG0 = REG9[REG8 + 25];
REG1 = REG9[REG8 + 26];
state = REG1 ? 13 : 9; break;
case 11: // basic block start for source line 1691
REG6 = REG5[REG4 + 0];
REG7 = REG5[REG4 + 1];
REG8 = REG7[REG6 + 1];
REG9 = REG7[REG6 + 2];
REG10 = REG7[REG6 + 2];
REG11 = REG7[REG6 + 3];
REG0 = 2;
REG1 = 1;
REG2 = calloc;
REG3 = REG2(sp, stack, REG1, REG0);
REG14 = REG3[1]
REG3 = REG3[0]
REG12 = REG3;
REG13 = REG14;
state = REG13 ? 10 : 12; break;
case 12: // basic block start for source line 1668
return;
case 13: // basic block start for source line 1706
REG0 = REG9[REG8 + 26];
REG1 = REG9[REG8 + 27];
REG1[REG0 + 1] = REG12;
REG1[REG0 + 2] = REG13;
REG9[REG8 + 26] = REG12;
REG9[REG8 + 27] = REG13;
state = 8; break;
case 14: // basic block start for source line 1722
REG0 = REG11[REG10 + 28];
REG1 = REG11[REG10 + 29];
REG1[REG0 + 1] = REG14;
REG1[REG0 + 2] = REG15;
REG11[REG10 + 28] = REG14;
REG11[REG10 + 29] = REG15;
state = 5; break;
} } }

function static_0_34_clear_stlist(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = REG1[REG0 + 25];
REG5 = REG1[REG0 + 26];
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 1: // basic block start for source line 1740
state = REG3 ? 2 : 3; break;
case 2: // basic block start for source line 1741
REG4 = REG3[REG2 + 1];
REG5 = REG3[REG2 + 2];
REG6 = free;
REG6(sp, stack, REG2, REG3);
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 3: // basic block start for source line 1747
REG2 = 0;
REG1[REG0 + 25] = REG2;
REG2 = 0;
REG1[REG0 + 26] = REG2;
REG2 = 0;
REG1[REG0 + 12] = REG2;
REG2 = REG1[REG0 + 27];
REG3 = REG1[REG0 + 28];
REG4 = REG2;
REG5 = REG3;
state = 4; break;
case 4: // basic block start for source line 1752
state = REG5 ? 5 : 6; break;
case 5: // basic block start for source line 1753
REG2 = REG5[REG4 + 1];
REG3 = REG5[REG4 + 2];
REG6 = free;
REG6(sp, stack, REG4, REG5);
REG4 = REG2;
REG5 = REG3;
state = 4; break;
case 6: // basic block start for source line 1759
REG2 = 0;
REG1[REG0 + 27] = REG2;
REG2 = 0;
REG1[REG0 + 28] = REG2;
REG2 = 0;
REG1[REG0 + 11] = REG2;
return;
} } }

function static_0_35_clear_stlist_all(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = REG1[REG0 + 15];
REG5 = REG1[REG0 + 16];
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 1: // basic block start for source line 1770
state = REG3 ? 2 : 3; break;
case 2: // basic block start for source line 1771
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
REG4 = static_0_34_clear_stlist;
REG4(sp, stack, REG0, REG1);
REG0 = REG3[REG2 + 1];
REG1 = REG3[REG2 + 2];
REG2 = REG0;
REG3 = REG1;
state = 1; break;
case 3: // basic block start for source line 1766
return;
} } }

function static_0_36_add_singlenode(fp, stack, REG0, REG1) {
var sp;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG6 = 2;
REG7 = 1;
REG8 = calloc;
REG9 = REG8(sp, stack, REG7, REG6);
REG10 = REG9[1]
REG9 = REG9[0]
REG4 = REG9;
REG5 = REG10;
state = REG5 ? 1 : 3; break;
case 1: // basic block start for source line 1783
REG5[REG4 + 0] = REG2;
REG5[REG4 + 1] = REG3;
REG6 = REG1[REG0 + 17];
REG7 = REG1[REG0 + 18];
state = REG7 ? 4 : 2; break;
case 2: // basic block start for source line 1785
REG1[REG0 + 17] = REG4;
REG1[REG0 + 18] = REG5;
REG1[REG0 + 18] = REG4;
REG1[REG0 + 19] = REG5;
state = 3; break;
case 3: // basic block start for source line 1778
return;
case 4: // basic block start for source line 1788
REG2 = REG1[REG0 + 18];
REG3 = REG1[REG0 + 19];
REG3[REG2 + 1] = REG4;
REG3[REG2 + 2] = REG5;
REG1[REG0 + 18] = REG4;
REG1[REG0 + 19] = REG5;
state = 3; break;
} } }

function static_0_37_ylevels(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var REG16;
var REG17;
var REG18;
var REG19;
var REG20;
var REG21;
var REG22;
var REG23;
var REG24;
var REG25;
var REG26;
var REG27;
var REG28;
var REG29;
var REG30;
var REG31;
var REG32;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG2 = REG1[REG0 + 15];
REG3 = REG1[REG0 + 16];
state = REG3 ? 9 : 1; break;
case 1: // basic block start for source line 1796
return;
case 2: // basic block start for source line 1879
REG2 = REG1[REG0 + 11];
REG3 = 1;
REG4 = calloc;
REG5 = REG4(sp, stack, REG3, REG2);
REG6 = REG5[1]
REG5 = REG5[0]
REG23 = REG5;
REG24 = REG6;
REG1[REG0 + 12] = REG23;
REG1[REG0 + 13] = REG24;
state = REG24 ? 25 : 1; break;
case 3: // basic block start for source line 1870
REG19 = REG1[REG0 + 11];
REG20 = 0;
state = REG19 ? 2 : 22; break;
case 4: // basic block start for source line 1860
state = REG16 ? 20 : 3; break;
case 5: // basic block start for source line 1859
REG2 = REG1[REG0 + 15];
REG3 = REG1[REG0 + 16];
REG15 = REG2;
REG16 = REG3;
state = 4; break;
case 6: // basic block start for source line 1847
state = REG11 ? 15 : 5; break;
case 7: // basic block start for source line 1834
REG2 = REG1[REG0 + 8];
REG3 = 0;
REG12 = (REG2 != REG3) ? 1 : 0;
REG2 = 0;
REG1[REG0 + 11] = REG2;
REG1[REG0 + 10] = REG12;
REG2 = REG1[REG0 + 15];
REG3 = REG1[REG0 + 16];
REG10 = REG2;
REG11 = REG3;
state = 6; break;
case 8: // basic block start for source line 1813
state = REG5 ? 11 : 7; break;
case 9: // basic block start for source line 1809
REG7 = 0;
REG1[REG0 + 8] = REG7;
REG4 = REG2;
REG5 = REG3;
REG6 = 0;
state = 8; break;
case 10: // basic block start for source line 1830
REG2 = REG5[REG4 + 1];
REG3 = REG5[REG4 + 2];
REG4 = REG2;
REG5 = REG3;
REG6 = REG7;
state = 8; break;
case 11: // basic block start for source line 1814
REG2 = 1;
REG7 = REG6 + REG2;
REG2 = REG5[REG4 + 0];
REG3 = REG5[REG4 + 1];
REG6 = 4294967295;
REG3[REG2 + 16] = REG6;
REG2 = REG5[REG4 + 0];
REG3 = REG5[REG4 + 1];
REG6 = 0;
REG3[REG2 + 9] = REG6;
REG2 = REG5[REG4 + 0];
REG3 = REG5[REG4 + 1];
REG6 = 0;
REG3[REG2 + 10] = REG6;
REG2 = REG5[REG4 + 0];
REG3 = REG5[REG4 + 1];
REG6 = 4294967295;
REG3[REG2 + 29] = REG6;
REG8 = REG5[REG4 + 0];
REG9 = REG5[REG4 + 1];
REG2 = REG9[REG8 + 25];
REG3 = REG9[REG8 + 26];
state = REG3 ? 10 : 12; break;
case 12: // basic block start for source line 1821
REG2 = REG9[REG8 + 27];
REG3 = REG9[REG8 + 28];
state = REG3 ? 10 : 13; break;
case 13: // basic block start for source line 1823
REG2 = 0;
REG9[REG8 + 16] = REG2;
REG2 = REG5[REG4 + 0];
REG3 = REG5[REG4 + 1];
REG6 = 1;
REG3[REG2 + 9] = REG6;
REG2 = REG5[REG4 + 0];
REG3 = REG5[REG4 + 1];
REG6 = 0;
REG3[REG2 + 29] = REG6;
REG2 = REG1[REG0 + 8];
REG3 = 1;
REG6 = REG2 + REG3;
REG1[REG0 + 8] = REG6;
REG2 = REG5[REG4 + 0];
REG3 = REG5[REG4 + 1];
REG6 = static_0_36_add_singlenode;
REG6(sp, stack, REG0, REG1, REG2, REG3);
state = 10; break;
case 14: // basic block start for source line 1855
REG2 = REG11[REG10 + 1];
REG3 = REG11[REG10 + 2];
REG10 = REG2;
REG11 = REG3;
state = 6; break;
case 15: // basic block start for source line 1848
REG13 = REG11[REG10 + 0];
REG14 = REG11[REG10 + 1];
REG2 = REG14[REG13 + 16];
REG3 = 4294967295;
REG4 = (REG2 == REG3) ? 1 : 0;
state = REG4 ? 16 : 14; break;
case 16: // basic block start for source line 1850
REG2 = REG14[REG13 + 11];
state = REG2 ? 14 : 17; break;
case 17: // basic block start for source line 1850
REG2 = REG14[REG13 + 12];
state = REG2 ? 18 : 14; break;
case 18: // basic block start for source line 1851
REG2 = REG1[REG0 + 11];
REG3 = 1;
REG4 = REG2 + REG3;
REG1[REG0 + 11] = REG4;
REG2 = REG11[REG10 + 0];
REG3 = REG11[REG10 + 1];
REG4 = REG3[REG2 + 0];
REG5 = static_0_12_set_level2;
REG5(sp, stack, REG0, REG1, REG2, REG3, REG12, REG4);
state = 14; break;
case 19: // basic block start for source line 1864
REG2 = REG16[REG15 + 1];
REG3 = REG16[REG15 + 2];
REG15 = REG2;
REG16 = REG3;
state = 4; break;
case 20: // basic block start for source line 1861
REG17 = REG16[REG15 + 0];
REG18 = REG16[REG15 + 1];
REG2 = REG18[REG17 + 16];
REG3 = 4294967295;
REG4 = (REG2 == REG3) ? 1 : 0;
state = REG4 ? 21 : 19; break;
case 21: // basic block start for source line 1862
REG2 = REG18[REG17 + 0];
REG3 = static_0_12_set_level2;
REG3(sp, stack, REG0, REG1, REG17, REG18, REG12, REG2);
state = 19; break;
case 22: // basic block start for source line 1871
REG2 = 1;
REG3 = REG19 + REG2;
REG1[REG0 + 11] = REG3;
REG21 = REG1[REG0 + 15];
REG22 = REG1[REG0 + 16];
state = REG22 ? 23 : 24; break;
case 23: // basic block start for source line 1873
REG2 = REG22[REG21 + 0];
REG3 = REG22[REG21 + 1];
REG4 = REG3[REG2 + 0];
REG5 = static_0_12_set_level2;
REG5(sp, stack, REG0, REG1, REG2, REG3, REG12, REG4);
state = 24; break;
case 24: // basic block start for source line 1875
REG20 = 1;
state = 2; break;
case 25: // basic block start for source line 1885
state = REG20 ? 26 : 28; break;
case 26: // basic block start for source line 1887
REG25 = REG1[REG0 + 15];
REG26 = REG1[REG0 + 16];
state = REG26 ? 27 : 1; break;
case 27: // basic block start for source line 1888
REG0 = REG26[REG25 + 0];
REG1 = REG26[REG25 + 1];
REG2 = REG1[REG0 + 0];
REG24[REG23 + 0] = REG2;
state = 1; break;
case 28: // basic block start for source line 1892
REG2 = REG1[REG0 + 15];
REG3 = REG1[REG0 + 16];
REG27 = REG2;
REG28 = REG3;
REG29 = 0;
state = 29; break;
case 29: // basic block start for source line 1894
state = REG28 ? 31 : 1; break;
case 30: // basic block start for source line 1901
REG2 = REG28[REG27 + 1];
REG3 = REG28[REG27 + 2];
REG27 = REG2;
REG28 = REG3;
REG29 = REG32;
state = 29; break;
case 31: // basic block start for source line 1896
REG30 = REG28[REG27 + 0];
REG31 = REG28[REG27 + 1];
REG2 = REG31[REG30 + 11];
REG32 = REG29;
state = REG2 ? 30 : 32; break;
case 32: // basic block start for source line 1896
REG2 = REG31[REG30 + 12];
REG32 = REG29;
state = REG2 ? 33 : 30; break;
case 33: // basic block start for source line 1898
REG2 = REG31[REG30 + 0];
REG3 = REG1[REG0 + 12];
REG4 = REG1[REG0 + 13];
REG5 = REG3 + REG29;
REG4[REG5 + 0] = REG2;
REG2 = 1;
REG3 = REG29 + REG2;
REG32 = REG3;
state = 30; break;
} } }

function static_0_38_set_level2(fp, stack, REG0, REG1, REG2, REG3) {
var sp;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG7 = REG3[REG2 + 9];
REG6 = REG7;
state = REG7 ? 1 : 10; break;
case 1: // basic block start for source line 1915
REG6 = REG3[REG2 + 16];
REG7 = (REG4 > REG6) ? 1 : 0;
state = REG7 ? 2 : 5; break;
case 2: // basic block start for source line 1915
REG6 = REG3[REG2 + 10];
state = REG6 ? 5 : 3; break;
case 3: // basic block start for source line 1916
REG3[REG2 + 16] = REG4;
REG6 = REG1[REG0 + 5];
REG7 = (REG4 > REG6) ? 1 : 0;
state = REG7 ? 4 : 5; break;
case 4: // basic block start for source line 1918
REG1[REG0 + 5] = REG4;
state = 5; break;
case 5: // basic block start for source line 1921
REG6 = REG3[REG2 + 10];
state = REG6 ? 6 : 11; break;
case 6: // basic block start for source line 1909
return;
case 7: // basic block start for source line 1946
REG0 = 0;
REG3[REG2 + 10] = REG0;
state = 6; break;
case 8: // basic block start for source line 1940
state = REG8 ? 13 : 7; break;
case 9: // basic block start for source line 1939
REG6 = REG3[REG2 + 25];
REG9 = REG3[REG2 + 26];
REG7 = REG6;
REG8 = REG9;
state = 8; break;
case 10: // basic block start for source line 1929
REG7 = REG3[REG2 + 10];
REG8 = 1;
REG9 = REG7 + REG8;
REG3[REG2 + 10] = REG9;
REG7 = 1;
REG8 = REG6 + REG7;
REG3[REG2 + 9] = REG8;
REG3[REG2 + 16] = REG4;
REG3[REG2 + 29] = REG5;
REG6 = REG1[REG0 + 5];
REG7 = (REG4 > REG6) ? 1 : 0;
state = REG7 ? 12 : 9; break;
case 11: // basic block start for source line 1924
REG7 = REG3[REG2 + 9];
REG8 = 1;
REG9 = (REG7 > REG8) ? 1 : 0;
REG6 = REG7;
state = REG9 ? 6 : 10; break;
case 12: // basic block start for source line 1935
REG1[REG0 + 5] = REG4;
state = 9; break;
case 13: // basic block start for source line 1941
REG6 = REG8[REG7 + 0];
REG9 = REG8[REG7 + 1];
REG10 = REG9[REG6 + 2];
REG11 = REG9[REG6 + 3];
REG6 = 1;
REG9 = REG4 + REG6;
REG6 = static_0_38_set_level2;
REG6(sp, stack, REG0, REG1, REG10, REG11, REG9, REG5);
REG6 = REG8[REG7 + 1];
REG9 = REG8[REG7 + 2];
REG7 = REG6;
REG8 = REG9;
state = 8; break;
} } }

function static_0_39_unrev(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG5 = REG1[REG0 + 19];
REG6 = REG1[REG0 + 20];
REG2 = REG5;
REG3 = REG6;
REG4 = 0;
state = 1; break;
case 1: // basic block start for source line 1960
state = REG3 ? 3 : 5; break;
case 2: // basic block start for source line 1972
REG5 = REG3[REG2 + 1];
REG6 = REG3[REG2 + 2];
REG2 = REG5;
REG3 = REG6;
REG4 = REG7;
state = 1; break;
case 3: // basic block start for source line 1961
REG5 = REG3[REG2 + 0];
REG6 = REG3[REG2 + 1];
REG8 = REG6[REG5 + 6];
REG7 = REG4;
state = REG8 ? 4 : 2; break;
case 4: // basic block start for source line 1963
REG8 = 1;
REG9 = REG4 + REG8;
REG4 = REG6[REG5 + 1];
REG8 = REG6[REG5 + 2];
REG10 = REG6[REG5 + 2];
REG11 = REG6[REG5 + 3];
REG6[REG5 + 2] = REG4;
REG6[REG5 + 3] = REG8;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG5[REG4 + 1] = REG10;
REG5[REG4 + 2] = REG11;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG6 = 0;
REG5[REG4 + 6] = REG6;
REG7 = REG9;
state = 2; break;
case 5: // basic block start for source line 1974
state = REG4 ? 6 : 7; break;
case 6: // basic block start for source line 1976
REG2 = 0;
REG1[REG0 + 5] = REG2;
REG2 = static_0_35_clear_stlist_all;
REG2(sp, stack, REG0, REG1);
REG2 = static_0_33_make_stlist;
REG2(sp, stack, REG0, REG1);
state = 7; break;
case 7: // basic block start for source line 1951
return;
} } }

function static_0_40_do_abs(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG1 = 0;
REG2 = (REG0 < REG1) ? 1 : 0;
state = REG2 ? 1 : 3; break;
case 1: // basic block start for source line 1988
REG2 = -REG0;
REG1 = REG2;
state = 2; break;
case 2: // basic block start for source line 1985
return REG1;
case 3: // basic block start for source line 1990
REG1 = REG0;
state = 2; break;
} } }

function static_0_41_shorteredges(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_39_unrev;
REG4(sp, stack, REG0, REG1);
REG4 = REG1[REG0 + 15];
REG5 = REG1[REG0 + 16];
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 1: // basic block start for source line 2008
state = REG3 ? 3 : 8; break;
case 2: // basic block start for source line 2022
REG0 = REG3[REG2 + 1];
REG1 = REG3[REG2 + 2];
REG2 = REG0;
REG3 = REG1;
state = 1; break;
case 3: // basic block start for source line 2009
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG0 = REG5[REG4 + 11];
REG1 = 1;
REG6 = (REG0 == REG1) ? 1 : 0;
state = REG6 ? 4 : 2; break;
case 4: // basic block start for source line 2009
REG0 = REG5[REG4 + 12];
REG1 = 1;
REG6 = (REG0 == REG1) ? 1 : 0;
state = REG6 ? 5 : 2; break;
case 5: // basic block start for source line 2010
REG0 = REG5[REG4 + 25];
REG1 = REG5[REG4 + 26];
REG10 = REG5[REG4 + 27];
REG11 = REG5[REG4 + 28];
REG12 = REG11[REG10 + 0];
REG13 = REG11[REG10 + 1];
REG10 = REG1[REG0 + 0];
REG11 = REG1[REG0 + 1];
REG6 = REG13[REG12 + 1];
REG7 = REG13[REG12 + 2];
REG8 = REG11[REG10 + 2];
REG9 = REG11[REG10 + 3];
REG0 = REG7[REG6 + 16];
REG1 = REG5[REG4 + 16];
REG4 = REG0 - REG1;
REG0 = static_0_40_do_abs;
REG1 = REG0(sp, stack, REG4);
REG0 = 1;
REG4 = (REG1 > REG0) ? 1 : 0;
state = REG4 ? 6 : 7; break;
case 6: // basic block start for source line 2019
REG0 = REG7[REG6 + 16];
REG1 = REG9[REG8 + 16];
REG4 = REG0 + REG1;
REG0 = 2;
REG1 = REG4 / REG0;
REG1 = (REG1).toFixed();
REG0 = REG3[REG2 + 0];
REG4 = REG3[REG2 + 1];
REG4[REG0 + 16] = REG1;
state = 2; break;
case 7: // basic block start for source line 2017
REG0 = REG9[REG8 + 16];
REG1 = REG3[REG2 + 0];
REG4 = REG3[REG2 + 1];
REG5 = REG4[REG1 + 16];
REG1 = REG0 - REG5;
REG0 = static_0_40_do_abs;
REG4 = REG0(sp, stack, REG1);
REG0 = 1;
REG1 = (REG4 > REG0) ? 1 : 0;
state = REG1 ? 6 : 2; break;
case 8: // basic block start for source line 1995
return;
} } }

function static_0_42_edgesdownwards(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG5 = REG1[REG0 + 19];
REG6 = REG1[REG0 + 20];
REG2 = REG5;
REG3 = REG6;
REG4 = 0;
state = 1; break;
case 1: // basic block start for source line 2039
state = REG3 ? 3 : 8; break;
case 2: // basic block start for source line 2057
REG5 = REG3[REG2 + 1];
REG6 = REG3[REG2 + 2];
REG2 = REG5;
REG3 = REG6;
REG4 = REG11;
state = 1; break;
case 3: // basic block start for source line 2040
REG5 = REG3[REG2 + 0];
REG6 = REG3[REG2 + 1];
REG7 = REG6[REG5 + 1];
REG8 = REG6[REG5 + 2];
REG9 = REG6[REG5 + 2];
REG10 = REG6[REG5 + 3];
REG12 = REG10[REG9 + 16];
REG13 = REG8[REG7 + 16];
REG14 = REG12 - REG13;
REG12 = 0;
REG13 = (REG14 < REG12) ? 1 : 0;
REG11 = REG4;
state = REG13 ? 4 : 2; break;
case 4: // basic block start for source line 2045
REG6[REG5 + 2] = REG7;
REG6[REG5 + 3] = REG8;
REG5 = REG3[REG2 + 0];
REG6 = REG3[REG2 + 1];
REG6[REG5 + 1] = REG9;
REG6[REG5 + 2] = REG10;
REG12 = REG3[REG2 + 0];
REG13 = REG3[REG2 + 1];
REG5 = REG13[REG12 + 6];
state = REG5 ? 5 : 7; break;
case 5: // basic block start for source line 2050
REG5 = 0;
REG13[REG12 + 6] = REG5;
state = 6; break;
case 6: // basic block start for source line 2054
REG5 = 1;
REG6 = REG4 + REG5;
REG11 = REG6;
state = 2; break;
case 7: // basic block start for source line 2052
REG5 = 1;
REG13[REG12 + 6] = REG5;
state = 6; break;
case 8: // basic block start for source line 2059
state = REG4 ? 9 : 10; break;
case 9: // basic block start for source line 2061
REG2 = 0;
REG1[REG0 + 5] = REG2;
REG2 = static_0_35_clear_stlist_all;
REG2(sp, stack, REG0, REG1);
REG2 = static_0_33_make_stlist;
REG2(sp, stack, REG0, REG1);
state = 10; break;
case 10: // basic block start for source line 2029
return;
} } }

function static_0_43_edgelen(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG5 = REG1[REG0 + 19];
REG6 = REG1[REG0 + 20];
REG2 = REG5;
REG3 = REG6;
REG4 = 0;
state = 1; break;
case 1: // basic block start for source line 2080
state = REG3 ? 3 : 5; break;
case 2: // basic block start for source line 2091
REG5 = REG3[REG2 + 1];
REG6 = REG3[REG2 + 2];
REG2 = REG5;
REG3 = REG6;
REG4 = REG11;
state = 1; break;
case 3: // basic block start for source line 2081
REG5 = REG3[REG2 + 0];
REG6 = REG3[REG2 + 1];
REG7 = REG6[REG5 + 1];
REG8 = REG6[REG5 + 2];
REG9 = REG6[REG5 + 2];
REG10 = REG6[REG5 + 3];
REG12 = REG10[REG9 + 16];
REG13 = REG8[REG7 + 16];
REG14 = REG12 - REG13;
REG12 = 0;
REG13 = (REG14 < REG12) ? 1 : 0;
REG11 = REG4;
state = REG13 ? 4 : 2; break;
case 4: // basic block start for source line 2085
REG12 = 1;
REG13 = REG4 + REG12;
REG6[REG5 + 2] = REG7;
REG6[REG5 + 3] = REG8;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG5[REG4 + 1] = REG9;
REG5[REG4 + 2] = REG10;
REG11 = REG13;
state = 2; break;
case 5: // basic block start for source line 2094
state = REG4 ? 6 : 7; break;
case 6: // basic block start for source line 2096
REG2 = static_0_35_clear_stlist_all;
REG2(sp, stack, REG0, REG1);
REG2 = static_0_33_make_stlist;
REG2(sp, stack, REG0, REG1);
state = 7; break;
case 7: // basic block start for source line 2071
return;
} } }

function static_0_44_doublespacey(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = 0;
REG1[REG0 + 5] = REG4;
REG4 = REG1[REG0 + 15];
REG5 = REG1[REG0 + 16];
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 1: // basic block start for source line 2111
state = REG3 ? 3 : 5; break;
case 2: // basic block start for source line 2116
REG4 = REG3[REG2 + 1];
REG5 = REG3[REG2 + 2];
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 3: // basic block start for source line 2112
REG5 = REG3[REG2 + 0];
REG6 = REG3[REG2 + 1];
REG7 = REG6[REG5 + 16];
REG8 = REG7 * <no-name-for-reg>;
REG6[REG5 + 16] = REG8;
REG5 = REG3[REG2 + 0];
REG6 = REG3[REG2 + 1];
REG4 = REG6[REG5 + 16];
REG5 = REG1[REG0 + 5];
REG6 = (REG4 > REG5) ? 1 : 0;
state = REG6 ? 4 : 2; break;
case 4: // basic block start for source line 2114
REG1[REG0 + 5] = REG4;
state = 2; break;
case 5: // basic block start for source line 2104
return;
} } }

function static_0_45_add_new_dummynode(fp, stack, REG0, REG1) {
var sp;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG5 = REG4[REG3 + 0];
REG6 = REG4[REG3 + 1];
REG3 = static_0_25_uniqnode;
REG4 = REG3(sp, stack, REG5, REG6, REG2);
REG7 = REG4[1]
REG4 = REG4[0]
state = REG7 ? 1 : 4; break;
case 1: // basic block start for source line 2123
return;
case 2: // basic block start for source line 2139
REG0 = free;
REG0(sp, stack, REG3, REG4);
state = 1; break;
case 3: // basic block start for source line 2135
REG4[REG3 + 0] = REG2;
REG8 = static_0_0_maingraph;
REG7 = 0;
REG9 = REG8[REG7 + 0];
REG10 = REG8[REG7 + 1];
REG7 = static_0_26_uniqnode_add;
REG7(sp, stack, REG9, REG10, REG3, REG4);
REG7 = 2;
REG8 = 1;
REG9 = calloc;
REG10 = REG9(sp, stack, REG8, REG7);
REG11 = REG10[1]
REG10 = REG10[0]
REG5 = REG10;
REG6 = REG11;
state = REG6 ? 5 : 2; break;
case 4: // basic block start for source line 2131
REG5 = 32;
REG6 = 1;
REG7 = calloc;
REG8 = REG7(sp, stack, REG6, REG5);
REG9 = REG8[1]
REG8 = REG8[0]
REG3 = REG8;
REG4 = REG9;
state = REG4 ? 3 : 1; break;
case 5: // basic block start for source line 2143
REG6[REG5 + 0] = REG3;
REG6[REG5 + 1] = REG4;
REG2 = REG1[REG0 + 15];
REG3 = REG1[REG0 + 16];
state = REG3 ? 7 : 6; break;
case 6: // basic block start for source line 2145
REG1[REG0 + 15] = REG5;
REG1[REG0 + 16] = REG6;
REG1[REG0 + 16] = REG5;
REG1[REG0 + 17] = REG6;
state = 1; break;
case 7: // basic block start for source line 2148
REG2 = REG1[REG0 + 16];
REG3 = REG1[REG0 + 17];
REG3[REG2 + 1] = REG5;
REG3[REG2 + 2] = REG6;
REG1[REG0 + 16] = REG5;
REG1[REG0 + 17] = REG6;
state = 1; break;
} } }

function static_0_46_add_new_dummyedge(fp, stack, REG0, REG1, REG2, REG3) {
var sp;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG8 = static_0_0_maingraph;
REG7 = 0;
REG9 = REG8[REG7 + 0];
REG10 = REG8[REG7 + 1];
REG7 = static_0_25_uniqnode;
REG5 = REG7(sp, stack, REG9, REG10, REG2);
REG6 = REG5[1]
REG5 = REG5[0]
state = REG6 ? 5 : 1; break;
case 1: // basic block start for source line 2156
return;
case 2: // basic block start for source line 2183
REG0 = free;
REG0(sp, stack, REG9, REG10);
state = 1; break;
case 3: // basic block start for source line 2176
REG2 = REG1[REG0 + 3];
REG3 = 1;
REG13 = REG2 + REG3;
REG1[REG0 + 3] = REG13;
REG10[REG9 + 0] = REG13;
REG10[REG9 + 1] = REG5;
REG10[REG9 + 2] = REG6;
REG10[REG9 + 2] = REG7;
REG10[REG9 + 3] = REG8;
REG10[REG9 + 6] = REG4;
REG2 = 2;
REG3 = 1;
REG5 = calloc;
REG6 = REG5(sp, stack, REG3, REG2);
REG7 = REG6[1]
REG6 = REG6[0]
REG11 = REG6;
REG12 = REG7;
state = REG12 ? 6 : 2; break;
case 4: // basic block start for source line 2172
REG2 = 8;
REG3 = 1;
REG11 = calloc;
REG12 = REG11(sp, stack, REG3, REG2);
REG13 = REG12[1]
REG12 = REG12[0]
REG9 = REG12;
REG10 = REG13;
state = REG10 ? 3 : 1; break;
case 5: // basic block start for source line 2167
REG9 = static_0_0_maingraph;
REG2 = 0;
REG10 = REG9[REG2 + 0];
REG11 = REG9[REG2 + 1];
REG2 = static_0_25_uniqnode;
REG7 = REG2(sp, stack, REG10, REG11, REG3);
REG8 = REG7[1]
REG7 = REG7[0]
state = REG8 ? 4 : 1; break;
case 6: // basic block start for source line 2187
REG12[REG11 + 0] = REG9;
REG12[REG11 + 1] = REG10;
REG2 = REG1[REG0 + 19];
REG3 = REG1[REG0 + 20];
state = REG3 ? 8 : 7; break;
case 7: // basic block start for source line 2189
REG1[REG0 + 19] = REG11;
REG1[REG0 + 20] = REG12;
REG1[REG0 + 20] = REG11;
REG1[REG0 + 21] = REG12;
state = 1; break;
case 8: // basic block start for source line 2192
REG2 = REG1[REG0 + 20];
REG3 = REG1[REG0 + 21];
REG3[REG2 + 1] = REG11;
REG3[REG2 + 2] = REG12;
REG1[REG0 + 20] = REG11;
REG1[REG0 + 21] = REG12;
state = 1; break;
} } }

function static_0_47_del_edge(fp, stack, REG0, REG1) {
var sp;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var REG16;
var REG17;
var REG18;
var REG19;
var REG20;
var REG21;
var REG22;
var REG23;
var REG24;
var REG25;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = REG1[REG0 + 19];
REG5 = REG1[REG0 + 20];
state = REG5 ? 5 : 1; break;
case 1: // basic block start for source line 2200
return;
case 2: // basic block start for source line 2226
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
REG4 = free;
REG4(sp, stack, REG0, REG1);
REG0 = 0;
REG3[REG2 + 0] = REG0;
REG0 = free;
REG0(sp, stack, REG2, REG3);
state = 1; break;
case 3: // basic block start for source line 2212
REG4 = 0;
REG1[REG0 + 20] = REG4;
state = 2; break;
case 4: // basic block start for source line 2210
REG16 = REG5[REG4 + 1];
REG17 = REG5[REG4 + 2];
REG1[REG0 + 19] = REG16;
REG1[REG0 + 20] = REG17;
REG4 = REG1[REG0 + 20];
REG5 = REG1[REG0 + 21];
REG6 = (REG4 == REG2) ? 1 : 0;
state = REG6 ? 3 : 14; break;
case 5: // basic block start for source line 2209
REG6 = (REG2 == REG4) ? 1 : 0;
state = REG6 ? 4 : 6; break;
case 6: // basic block start for source line 2231
REG6 = REG3[REG2 + 1];
REG7 = REG3[REG2 + 2];
REG10 = REG4;
REG11 = REG5;
REG8 = REG4;
REG9 = REG5;
state = 7; break;
case 7: // basic block start for source line 2234
REG14 = REG8;
REG15 = REG9;
state = REG11 ? 9 : 11; break;
case 8: // basic block start for source line 2234
REG10 = REG12;
REG11 = REG13;
REG8 = REG10;
REG9 = REG11;
state = 7; break;
case 9: // basic block start for source line 2235
REG12 = REG11[REG10 + 1];
REG13 = REG11[REG10 + 2];
REG4 = (REG12 == REG2) ? 1 : 0;
state = REG4 ? 10 : 8; break;
case 10: // basic block start for source line 2237
REG14 = REG10;
REG15 = REG11;
state = 11; break;
case 11: // basic block start for source line 2242
REG15[REG14 + 1] = REG6;
REG15[REG14 + 2] = REG7;
REG4 = REG1[REG0 + 20];
REG5 = REG1[REG0 + 21];
REG6 = (REG4 == REG2) ? 1 : 0;
state = REG6 ? 12 : 13; break;
case 12: // basic block start for source line 2244
REG1[REG0 + 20] = REG14;
REG1[REG0 + 21] = REG15;
state = 13; break;
case 13: // basic block start for source line 2247
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
REG4 = free;
REG4(sp, stack, REG0, REG1);
REG0 = 0;
REG3[REG2 + 0] = REG0;
REG0 = free;
REG0(sp, stack, REG2, REG3);
state = 1; break;
case 14: // basic block start for source line 2214
REG20 = REG16;
REG21 = REG17;
REG18 = REG16;
REG19 = REG17;
state = 15; break;
case 15: // basic block start for source line 2216
REG24 = REG18;
REG25 = REG19;
state = REG21 ? 17 : 19; break;
case 16: // basic block start for source line 2216
REG20 = REG22;
REG21 = REG23;
REG18 = REG20;
REG19 = REG21;
state = 15; break;
case 17: // basic block start for source line 2217
REG22 = REG21[REG20 + 1];
REG23 = REG21[REG20 + 2];
REG4 = (REG22 == REG2) ? 1 : 0;
state = REG4 ? 18 : 16; break;
case 18: // basic block start for source line 2219
REG24 = REG20;
REG25 = REG21;
state = 19; break;
case 19: // basic block start for source line 2223
REG1[REG0 + 20] = REG24;
REG1[REG0 + 21] = REG25;
state = 2; break;
} } }

function static_0_48_edgelabels(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var REG16;
var REG17;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG2 = REG1[REG0 + 6];
state = REG2 ? 7 : 1; break;
case 1: // basic block start for source line 2256
return;
case 2: // basic block start for source line 2334
REG2 = static_0_35_clear_stlist_all;
REG2(sp, stack, REG0, REG1);
REG2 = static_0_33_make_stlist;
REG2(sp, stack, REG0, REG1);
state = 1; break;
case 3: // basic block start for source line 2294
state = REG13 ? 14 : 2; break;
case 4: // basic block start for source line 2293
REG2 = REG1[REG0 + 19];
REG3 = REG1[REG0 + 20];
REG12 = REG2;
REG13 = REG3;
state = 3; break;
case 5: // basic block start for source line 2276
state = REG3 ? 9 : 4; break;
case 6: // basic block start for source line 2275
REG4 = REG1[REG0 + 19];
REG5 = REG1[REG0 + 20];
REG2 = REG4;
REG3 = REG5;
state = 5; break;
case 7: // basic block start for source line 2269
REG2 = REG1[REG0 + 7];
state = REG2 ? 6 : 1; break;
case 8: // basic block start for source line 2289
REG4 = REG3[REG2 + 1];
REG5 = REG3[REG2 + 2];
REG2 = REG4;
REG3 = REG5;
state = 5; break;
case 9: // basic block start for source line 2278
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG6 = REG5[REG4 + 1];
REG7 = REG5[REG4 + 2];
REG10 = REG7[REG6 + 16];
REG8 = REG5[REG4 + 2];
REG9 = REG5[REG4 + 3];
REG11 = REG9[REG8 + 16];
REG12 = (REG10 > REG11) ? 1 : 0;
state = REG12 ? 10 : 8; break;
case 10: // basic block start for source line 2279
REG5[REG4 + 1] = REG8;
REG5[REG4 + 2] = REG9;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG5[REG4 + 2] = REG6;
REG5[REG4 + 3] = REG7;
REG10 = REG3[REG2 + 0];
REG11 = REG3[REG2 + 1];
REG4 = REG11[REG10 + 6];
state = REG4 ? 11 : 12; break;
case 11: // basic block start for source line 2284
REG4 = 0;
REG11[REG10 + 6] = REG4;
state = 8; break;
case 12: // basic block start for source line 2286
REG4 = 1;
REG11[REG10 + 6] = REG4;
state = 8; break;
case 13: // basic block start for source line 2294
REG12 = REG14;
REG13 = REG15;
state = 3; break;
case 14: // basic block start for source line 2295
REG14 = REG13[REG12 + 1];
REG15 = REG13[REG12 + 2];
REG16 = REG13[REG12 + 0];
REG17 = REG13[REG12 + 1];
REG2 = REG17[REG16 + 5];
state = REG2 ? 15 : 13; break;
case 15: // basic block start for source line 2299
REG2 = REG17[REG16 + 0];
REG3 = REG17[REG16 + 6];
REG5 = static_0_0_maingraph;
REG4 = 0;
REG6 = REG5[REG4 + 0];
REG7 = REG5[REG4 + 1];
REG4 = REG7[REG6 + 1];
REG5 = 1;
REG8 = REG4 + REG5;
REG7[REG6 + 1] = REG8;
REG5 = static_0_0_maingraph;
REG4 = 0;
REG6 = REG5[REG4 + 0];
REG7 = REG5[REG4 + 1];
REG4 = REG7[REG6 + 1];
REG5 = static_0_45_add_new_dummynode;
REG5(sp, stack, REG0, REG1, REG4);
REG5 = static_0_0_maingraph;
REG4 = 0;
REG6 = REG5[REG4 + 0];
REG7 = REG5[REG4 + 1];
REG4 = REG7[REG6 + 1];
REG5 = static_0_25_uniqnode;
REG8 = REG5(sp, stack, REG6, REG7, REG4);
REG9 = REG8[1]
REG8 = REG8[0]
REG4 = REG13[REG12 + 0];
REG5 = REG13[REG12 + 1];
REG6 = REG5[REG4 + 1];
REG7 = REG5[REG4 + 2];
REG9[REG8 + 30] = REG6;
REG9[REG8 + 31] = REG7;
REG4 = REG13[REG12 + 0];
REG5 = REG13[REG12 + 1];
REG10 = REG5[REG4 + 2];
REG11 = REG5[REG4 + 3];
REG9[REG8 + 31] = REG10;
REG9[REG8 + 32] = REG11;
REG4 = REG11[REG10 + 16];
REG5 = REG7[REG6 + 16];
REG6 = REG4 - REG5;
REG4 = 2;
REG7 = REG6 / REG4;
REG7 = (REG7).toFixed();
REG4 = REG5 + REG7;
REG9[REG8 + 16] = REG4;
REG4 = 1;
REG9[REG8 + 6] = REG4;
REG4 = 0;
REG9[REG8 + 5] = REG4;
REG9[REG8 + 7] = REG2;
REG2 = REG13[REG12 + 0];
REG4 = REG13[REG12 + 1];
REG5 = REG4[REG2 + 3];
REG9[REG8 + 1] = REG5;
REG2 = REG13[REG12 + 0];
REG4 = REG13[REG12 + 1];
REG5 = REG4[REG2 + 4];
REG9[REG8 + 2] = REG5;
REG2 = REG13[REG12 + 0];
REG4 = REG13[REG12 + 1];
REG5 = REG4[REG2 + 1];
REG6 = REG4[REG2 + 2];
REG2 = REG6[REG5 + 29];
REG9[REG8 + 29] = REG2;
REG2 = REG13[REG12 + 0];
REG4 = REG13[REG12 + 1];
REG5 = REG4[REG2 + 1];
REG6 = REG4[REG2 + 2];
REG2 = REG6[REG5 + 0];
REG5 = static_0_0_maingraph;
REG4 = 0;
REG6 = REG5[REG4 + 0];
REG7 = REG5[REG4 + 1];
REG4 = REG7[REG6 + 1];
REG5 = static_0_46_add_new_dummyedge;
REG5(sp, stack, REG0, REG1, REG2, REG4, REG3);
REG4 = static_0_0_maingraph;
REG2 = 0;
REG5 = REG4[REG2 + 0];
REG6 = REG4[REG2 + 1];
REG2 = REG6[REG5 + 1];
REG4 = REG13[REG12 + 0];
REG5 = REG13[REG12 + 1];
REG6 = REG5[REG4 + 2];
REG7 = REG5[REG4 + 3];
REG4 = REG7[REG6 + 0];
REG5 = static_0_46_add_new_dummyedge;
REG5(sp, stack, REG0, REG1, REG2, REG4, REG3);
REG2 = static_0_47_del_edge;
REG2(sp, stack, REG0, REG1, REG12, REG13);
state = 13; break;
} } }

function static_0_49_splitedges(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var REG16;
var REG17;
var REG18;
var REG19;
var REG20;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = REG1[REG0 + 19];
REG5 = REG1[REG0 + 20];
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 1: // basic block start for source line 2356
state = REG3 ? 4 : 10; break;
case 2: // basic block start for source line 2356
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 3: // basic block start for source line 2366
REG2 = 1;
REG7[REG6 + 7] = REG2;
REG2 = REG1[REG0 + 9];
REG3 = 1;
REG6 = REG2 + REG3;
REG1[REG0 + 9] = REG6;
REG2 = 1;
REG9[REG8 + 13] = REG2;
REG2 = 1;
REG11[REG10 + 13] = REG2;
state = 2; break;
case 4: // basic block start for source line 2357
REG4 = REG3[REG2 + 1];
REG5 = REG3[REG2 + 2];
REG6 = REG3[REG2 + 0];
REG7 = REG3[REG2 + 1];
REG8 = REG7[REG6 + 1];
REG9 = REG7[REG6 + 2];
REG10 = REG7[REG6 + 2];
REG11 = REG7[REG6 + 3];
REG12 = REG7[REG6 + 6];
REG15 = REG11[REG10 + 16];
REG13 = REG9[REG8 + 16];
REG14 = REG15 - REG13;
state = REG14 ? 5 : 3; break;
case 5: // basic block start for source line 2371
REG6 = 1;
REG7 = (REG14 > REG6) ? 1 : 0;
state = REG7 ? 6 : 2; break;
case 6: // basic block start for source line 2373
REG6 = REG9[REG8 + 0];
REG15 = REG6;
REG16 = 1;
state = 7; break;
case 7: // basic block start for source line 2375
REG6 = (REG16 < REG14) ? 1 : 0;
state = REG6 ? 8 : 9; break;
case 8: // basic block start for source line 2377
REG7 = static_0_0_maingraph;
REG6 = 0;
REG17 = REG7[REG6 + 0];
REG18 = REG7[REG6 + 1];
REG6 = REG18[REG17 + 1];
REG7 = 1;
REG19 = REG6 + REG7;
REG18[REG17 + 1] = REG19;
REG7 = static_0_0_maingraph;
REG6 = 0;
REG17 = REG7[REG6 + 0];
REG18 = REG7[REG6 + 1];
REG6 = REG18[REG17 + 1];
REG7 = static_0_45_add_new_dummynode;
REG7(sp, stack, REG17, REG18, REG6);
REG17 = static_0_0_maingraph;
REG7 = 0;
REG18 = REG17[REG7 + 0];
REG19 = REG17[REG7 + 1];
REG7 = static_0_25_uniqnode;
REG17 = REG7(sp, stack, REG18, REG19, REG6);
REG20 = REG17[1]
REG17 = REG17[0]
REG7 = 1;
REG20[REG17 + 5] = REG7;
REG7 = 0;
REG20[REG17 + 6] = REG7;
REG7 = REG13 + REG16;
REG20[REG17 + 16] = REG7;
REG7 = REG9[REG8 + 29];
REG20[REG17 + 29] = REG7;
REG7 = static_0_46_add_new_dummyedge;
REG7(sp, stack, REG0, REG1, REG15, REG6, REG12);
REG7 = 1;
REG17 = REG16 + REG7;
REG15 = REG6;
REG16 = REG17;
state = 7; break;
case 9: // basic block start for source line 2389
REG6 = REG11[REG10 + 0];
REG7 = static_0_46_add_new_dummyedge;
REG7(sp, stack, REG0, REG1, REG15, REG6, REG12);
REG6 = static_0_47_del_edge;
REG6(sp, stack, REG0, REG1, REG2, REG3);
state = 2; break;
case 10: // basic block start for source line 2341
return;
} } }

function static_0_50_nodecounts(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_35_clear_stlist_all;
REG4(sp, stack, REG0, REG1);
REG4 = static_0_33_make_stlist;
REG4(sp, stack, REG0, REG1);
REG4 = REG1[REG0 + 5];
REG5 = 1;
REG6 = REG4 + REG5;
REG4 = 1;
REG5 = calloc;
REG7 = REG5(sp, stack, REG6, REG4);
REG8 = REG7[1]
REG7 = REG7[0]
REG4 = REG7;
REG5 = REG8;
REG1[REG0 + 21] = REG4;
REG1[REG0 + 22] = REG5;
REG2 = REG4;
REG3 = REG5;
state = REG5 ? 3 : 1; break;
case 1: // basic block start for source line 2404
return;
case 2: // basic block start for source line 2420
state = REG5 ? 5 : 1; break;
case 3: // basic block start for source line 2417
REG6 = 0;
REG1[REG0 + 23] = REG6;
REG6 = 0;
REG1[REG0 + 22] = REG6;
REG6 = REG1[REG0 + 15];
REG7 = REG1[REG0 + 16];
REG4 = REG6;
REG5 = REG7;
state = 2; break;
case 4: // basic block start for source line 2429
REG6 = REG5[REG4 + 1];
REG7 = REG5[REG4 + 2];
REG4 = REG6;
REG5 = REG7;
state = 2; break;
case 5: // basic block start for source line 2422
REG8 = REG5[REG4 + 0];
REG9 = REG5[REG4 + 1];
REG10 = REG9[REG8 + 16];
REG8 = REG2 + REG10;
REG9 = REG3[REG8 + 0];
REG10 = 1;
REG11 = REG9 + REG10;
REG3[REG8 + 0] = REG11;
REG8 = REG1[REG0 + 21];
REG9 = REG1[REG0 + 22];
REG10 = REG5[REG4 + 0];
REG11 = REG5[REG4 + 1];
REG12 = REG11[REG10 + 16];
REG13 = REG8 + REG12;
REG8 = REG9[REG13 + 0];
REG11[REG10 + 15] = REG8;
REG8 = REG1[REG0 + 21];
REG9 = REG1[REG0 + 22];
REG10 = REG5[REG4 + 0];
REG11 = REG5[REG4 + 1];
REG12 = REG11[REG10 + 16];
REG7 = REG9;
REG6 = REG8 + REG12;
REG10 = REG7[REG6 + 0];
REG11 = REG1[REG0 + 22];
REG12 = (REG10 >= REG11) ? 1 : 0;
REG2 = REG8;
REG3 = REG9;
REG2 = REG8;
REG3 = REG9;
state = REG12 ? 6 : 4; break;
case 6: // basic block start for source line 2426
REG8 = REG7[REG6 + 0];
REG1[REG0 + 22] = REG8;
REG6 = REG5[REG4 + 0];
REG7 = REG5[REG4 + 1];
REG8 = REG7[REG6 + 16];
REG1[REG0 + 23] = REG8;
state = 4; break;
} } }

function static_0_51_number_of_crossings2(fp, stack, REG0, REG1, REG2) {
var sp;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var REG16;
var REG17;
var REG18;
var REG19;
var REG20;
var REG21;
var REG22;
var REG23;
var REG24;
var REG25;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = 1;
REG5 = 0;
state = 1; break;
case 1: // basic block start for source line 2520
REG6 = -1;
REG7 = REG2 + REG6;
REG6 = (REG4 <= REG7) ? 1 : 0;
state = REG6 ? 4 : 18; break;
case 2: // basic block start for source line 2520
REG4 = REG6;
REG5 = REG8;
state = 1; break;
case 3: // basic block start for source line 2521
REG5 = (REG7 <= REG2) ? 1 : 0;
state = REG5 ? 7 : 2; break;
case 4: // basic block start for source line 2521
REG9 = 1;
REG6 = REG4 + REG9;
REG7 = REG6;
REG8 = REG5;
state = 3; break;
case 5: // basic block start for source line 2521
REG5 = 1;
REG9 = REG7 + REG5;
REG7 = REG9;
REG8 = REG10;
state = 3; break;
case 6: // basic block start for source line 2522
REG5 = -1;
REG8 = REG3 + REG5;
REG5 = (REG9 <= REG8) ? 1 : 0;
state = REG5 ? 10 : 5; break;
case 7: // basic block start for source line 2522
REG9 = 1;
REG10 = REG8;
state = 6; break;
case 8: // basic block start for source line 2522
REG9 = REG11;
REG10 = REG13;
state = 6; break;
case 9: // basic block start for source line 2523
REG5 = (REG12 <= REG3) ? 1 : 0;
state = REG5 ? 15 : 8; break;
case 10: // basic block start for source line 2523
REG5 = 1;
REG11 = REG9 + REG5;
REG12 = REG11;
REG13 = REG10;
state = 9; break;
case 11: // basic block start for source line 2490
REG5 = 8;
REG8 = REG22 / REG5;
REG8 = (REG8).toFixed();
REG5 = REG14 + REG8;
REG8 = REG15[REG5 + 0];
REG5 = REG8 & REG24;
REG8 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
REG10 = REG21 * REG5;
REG5 = REG13 + REG10;
REG10 = 1;
REG14 = REG12 + REG10;
REG12 = REG14;
REG13 = REG5;
state = 9; break;
case 12: // basic block start for source line 2487
REG5 = (REG25 < REG23) ? 1 : 0;
state = REG5 ? 17 : 11; break;
case 13: // basic block start for source line 2490
REG5 = 8;
REG8 = REG17 / REG5;
REG8 = (REG8).toFixed();
REG5 = REG14 + REG8;
REG8 = REG15[REG5 + 0];
REG21 = REG8 & REG19;
REG5 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
REG8 = REG7 * REG16;
REG22 = REG8 + REG9;
REG8 = 8;
REG23 = REG22 % REG8;
REG24 = 1;
REG25 = 0;
state = 12; break;
case 14: // basic block start for source line 2487
REG5 = (REG20 < REG18) ? 1 : 0;
state = REG5 ? 16 : 13; break;
case 15: // basic block start for source line 2525
REG14 = REG1[REG0 + 10];
REG15 = REG1[REG0 + 11];
REG16 = REG1[REG0 + 2];
REG5 = REG4 * REG16;
REG17 = REG5 + REG12;
REG5 = 8;
REG18 = REG17 % REG5;
REG19 = 1;
REG20 = 0;
state = 14; break;
case 16: // basic block start for source line 2488
REG5 = REG19 * <no-name-for-reg>;
REG8 = 1;
REG10 = REG20 + REG8;
REG19 = REG5;
REG20 = REG10;
state = 14; break;
case 17: // basic block start for source line 2488
REG5 = REG24 * <no-name-for-reg>;
REG8 = 1;
REG10 = REG25 + REG8;
REG24 = REG5;
REG25 = REG10;
state = 12; break;
case 18: // basic block start for source line 2512
return REG5;
} } }

function static_0_54_number_of_crossings3(fp, stack, REG0, REG1, REG2) {
var sp;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var REG16;
var REG17;
var REG18;
var REG19;
var REG20;
var REG21;
var REG22;
var REG23;
var REG24;
var REG25;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = 1;
REG5 = 0;
state = 1; break;
case 1: // basic block start for source line 2545
REG6 = -1;
REG7 = REG2 + REG6;
REG6 = (REG4 <= REG7) ? 1 : 0;
state = REG6 ? 4 : 22; break;
case 2: // basic block start for source line 2545
REG4 = REG6;
REG5 = REG8;
state = 1; break;
case 3: // basic block start for source line 2546
REG5 = (REG7 <= REG2) ? 1 : 0;
state = REG5 ? 7 : 2; break;
case 4: // basic block start for source line 2546
REG9 = 1;
REG6 = REG4 + REG9;
REG7 = REG6;
REG8 = REG5;
state = 3; break;
case 5: // basic block start for source line 2546
REG5 = 1;
REG9 = REG7 + REG5;
REG7 = REG9;
REG8 = REG10;
state = 3; break;
case 6: // basic block start for source line 2547
REG5 = -1;
REG8 = REG3 + REG5;
REG5 = (REG9 <= REG8) ? 1 : 0;
state = REG5 ? 11 : 5; break;
case 7: // basic block start for source line 2547
REG9 = 1;
REG10 = REG8;
state = 6; break;
case 8: // basic block start for source line 2550
REG5 = 1;
REG8 = REG9 + REG5;
REG9 = REG8;
REG10 = REG18;
state = 6; break;
case 9: // basic block start for source line 2490
REG5 = 8;
REG8 = REG14 / REG5;
REG8 = (REG8).toFixed();
REG5 = REG11 + REG8;
REG8 = REG12[REG5 + 0];
REG5 = REG8 & REG16;
REG8 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
REG18 = REG10;
state = REG5 ? 13 : 8; break;
case 10: // basic block start for source line 2487
REG5 = (REG17 < REG15) ? 1 : 0;
state = REG5 ? 12 : 9; break;
case 11: // basic block start for source line 2550
REG11 = REG1[REG0 + 10];
REG12 = REG1[REG0 + 11];
REG13 = REG1[REG0 + 2];
REG5 = REG7 * REG13;
REG14 = REG5 + REG9;
REG5 = 8;
REG15 = REG14 % REG5;
REG16 = 1;
REG17 = 0;
state = 10; break;
case 12: // basic block start for source line 2488
REG5 = REG16 * <no-name-for-reg>;
REG8 = 1;
REG18 = REG17 + REG8;
REG16 = REG5;
REG17 = REG18;
state = 10; break;
case 13: // basic block start for source line 2551
REG5 = 1;
REG8 = REG9 + REG5;
REG19 = REG8;
REG20 = REG10;
state = 14; break;
case 14: // basic block start for source line 2551
REG5 = (REG19 <= REG3) ? 1 : 0;
state = REG5 ? 18 : 21; break;
case 15: // basic block start for source line 2553
REG5 = 1;
REG8 = REG19 + REG5;
REG19 = REG8;
REG20 = REG25;
state = 14; break;
case 16: // basic block start for source line 2490
REG5 = 8;
REG8 = REG21 / REG5;
REG8 = (REG8).toFixed();
REG5 = REG11 + REG8;
REG8 = REG12[REG5 + 0];
REG5 = REG8 & REG23;
REG8 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
REG25 = REG20;
state = REG5 ? 20 : 15; break;
case 17: // basic block start for source line 2487
REG5 = (REG24 < REG22) ? 1 : 0;
state = REG5 ? 19 : 16; break;
case 18: // basic block start for source line 2553
REG5 = REG4 * REG13;
REG21 = REG5 + REG19;
REG5 = 8;
REG22 = REG21 % REG5;
REG23 = 1;
REG24 = 0;
state = 17; break;
case 19: // basic block start for source line 2488
REG5 = REG23 * <no-name-for-reg>;
REG8 = 1;
REG10 = REG24 + REG8;
REG23 = REG5;
REG24 = REG10;
state = 17; break;
case 20: // basic block start for source line 2554
REG5 = 1;
REG8 = REG20 + REG5;
REG25 = REG8;
state = 15; break;
case 21: // basic block start for source line 2551
REG18 = REG20;
state = 8; break;
case 22: // basic block start for source line 2533
return REG5;
} } }

function static_0_55_number_of_crossings_a(fp, stack, REG0, REG1) {
var sp;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = 0;
REG5 = 0;
state = 1; break;
case 1: // basic block start for source line 2574
REG6 = REG1[REG0 + 5];
REG7 = (REG5 < REG6) ? 1 : 0;
state = REG7 ? 3 : 5; break;
case 2: // basic block start for source line 2575
REG6 = 1;
REG7 = REG5 + REG6;
REG4 = REG8;
REG5 = REG7;
state = 1; break;
case 3: // basic block start for source line 2575
REG9 = REG2 + REG5;
REG6 = REG3[REG9 + 0];
REG7 = REG3[REG9 + 1];
REG8 = REG4;
state = REG7 ? 4 : 2; break;
case 4: // basic block start for source line 2576
REG9 = REG7[REG6 + 1];
REG10 = REG7[REG6 + 2];
REG11 = static_0_54_number_of_crossings3;
REG12 = REG11(sp, stack, REG6, REG7, REG9, REG10);
REG6 = REG1[REG0 + 27];
REG7 = REG1[REG0 + 28];
REG9 = REG6 + REG5;
REG7[REG9 + 0] = REG12;
REG6 = REG4 + REG12;
REG8 = REG6;
state = 2; break;
case 5: // basic block start for source line 2568
return REG4;
} } }

function static_0_56_make_matrix(fp, stack, REG0, REG1, REG2) {
var sp;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var REG16;
var REG17;
var REG18;
var REG19;
var REG20;
var REG21;
var REG22;
var REG23;
var REG24;
var REG25;
var REG26;
var REG27;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG7 = REG1[REG0 + 15];
REG8 = REG1[REG0 + 16];
REG5 = REG7;
REG6 = REG8;
state = 1; break;
case 1: // basic block start for source line 2600
state = REG6 ? 4 : 7; break;
case 2: // basic block start for source line 2611
REG7 = REG6[REG5 + 1];
REG8 = REG6[REG5 + 2];
REG5 = REG7;
REG6 = REG8;
state = 1; break;
case 3: // basic block start for source line 2604
REG9 = REG8[REG7 + 15];
REG10 = REG8[REG7 + 0];
REG7 = REG4[REG3 + 4];
REG8 = REG4[REG3 + 5];
REG11 = REG7 + REG9;
REG8[REG11 + 0] = REG10;
state = 2; break;
case 4: // basic block start for source line 2602
REG7 = REG6[REG5 + 0];
REG8 = REG6[REG5 + 1];
REG9 = REG8[REG7 + 16];
REG10 = (REG9 == REG2) ? 1 : 0;
state = REG10 ? 3 : 5; break;
case 5: // basic block start for source line 2606
REG10 = 1;
REG11 = REG2 + REG10;
REG10 = (REG9 == REG11) ? 1 : 0;
state = REG10 ? 6 : 2; break;
case 6: // basic block start for source line 2608
REG9 = REG8[REG7 + 15];
REG10 = REG8[REG7 + 0];
REG7 = REG4[REG3 + 6];
REG8 = REG4[REG3 + 7];
REG11 = REG7 + REG9;
REG8[REG11 + 0] = REG10;
state = 2; break;
case 7: // basic block start for source line 2615
REG10 = REG4[REG3 + 1];
REG11 = REG4[REG3 + 2];
REG12 = 1;
state = 8; break;
case 8: // basic block start for source line 2618
REG5 = (REG12 <= REG10) ? 1 : 0;
state = REG5 ? 11 : 15; break;
case 9: // basic block start for source line 2618
REG5 = 1;
REG6 = REG12 + REG5;
REG12 = REG6;
state = 8; break;
case 10: // basic block start for source line 2619
REG5 = (REG13 <= REG11) ? 1 : 0;
state = REG5 ? 14 : 9; break;
case 11: // basic block start for source line 2619
REG13 = 1;
state = 10; break;
case 12: // basic block start for source line 2619
REG5 = 1;
REG6 = REG13 + REG5;
REG13 = REG6;
state = 10; break;
case 13: // basic block start for source line 2462
REG5 = 8;
REG6 = REG16 % REG5;
REG5 = 1;
REG7 = REG5 << REG6;
REG5 = 8;
REG6 = REG16 / REG5;
REG6 = (REG6).toFixed();
REG5 = REG14 + REG6;
REG6 = REG15[REG5 + 0];
REG7 = REG6 & <no-name-for-reg>;
REG15[REG5 + 0] = REG7;
state = 12; break;
case 14: // basic block start for source line 2507
REG14 = REG4[REG3 + 10];
REG15 = REG4[REG3 + 11];
REG5 = REG4[REG3 + 2];
REG6 = REG12 * REG5;
REG16 = REG6 + REG13;
state = REG16 ? 13 : 12; break;
case 15: // basic block start for source line 2624
REG5 = REG1[REG0 + 15];
REG6 = REG1[REG0 + 16];
REG17 = REG5;
REG18 = REG6;
state = 16; break;
case 16: // basic block start for source line 2626
state = REG18 ? 18 : 25; break;
case 17: // basic block start for source line 2644
REG0 = REG18[REG17 + 1];
REG1 = REG18[REG17 + 2];
REG17 = REG0;
REG18 = REG1;
state = 16; break;
case 18: // basic block start for source line 2628
REG19 = REG18[REG17 + 0];
REG20 = REG18[REG17 + 1];
REG0 = REG20[REG19 + 16];
REG1 = (REG0 == REG2) ? 1 : 0;
state = REG1 ? 19 : 17; break;
case 19: // basic block start for source line 2630
REG0 = REG20[REG19 + 25];
REG1 = REG20[REG19 + 26];
REG21 = REG0;
REG22 = REG1;
state = 20; break;
case 20: // basic block start for source line 2631
state = REG22 ? 22 : 17; break;
case 21: // basic block start for source line 2641
REG0 = REG22[REG21 + 1];
REG1 = REG22[REG21 + 2];
REG21 = REG0;
REG22 = REG1;
state = 20; break;
case 22: // basic block start for source line 2633
REG23 = REG22[REG21 + 0];
REG24 = REG22[REG21 + 1];
REG0 = REG24[REG23 + 7];
state = REG0 ? 21 : 23; break;
case 23: // basic block start for source line 2635
REG0 = REG18[REG17 + 0];
REG1 = REG18[REG17 + 1];
REG5 = REG1[REG0 + 15];
REG0 = REG24[REG23 + 2];
REG1 = REG24[REG23 + 3];
REG6 = REG1[REG0 + 15];
REG25 = REG4[REG3 + 10];
REG26 = REG4[REG3 + 11];
REG0 = REG4[REG3 + 2];
REG1 = REG5 * REG0;
REG27 = REG1 + REG6;
state = REG27 ? 24 : 21; break;
case 24: // basic block start for source line 2453
REG0 = 8;
REG1 = REG27 % REG0;
REG0 = 1;
REG5 = REG0 << REG1;
REG0 = 8;
REG1 = REG27 / REG0;
REG1 = (REG1).toFixed();
REG0 = REG25 + REG1;
REG1 = REG26[REG0 + 0];
REG6 = REG1 | REG5;
REG26[REG0 + 0] = REG6;
state = 21; break;
case 25: // basic block start for source line 2587
return;
} } }

function static_0_60_su_find_node_with_number(fp, stack, REG0, REG1) {
var sp;
var REG2;
var REG3;
var REG4;
var REG5;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = static_0_25_uniqnode;
REG4 = REG3(sp, stack, REG0, REG1, REG2);
REG5 = REG4[1]
REG4 = REG4[0]
return [REG4, REG5];
} } }

function static_0_61_store_new_positions(fp, stack, REG0, REG1, REG2) {
var sp;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
state = REG3 ? 5 : 1; break;
case 1: // basic block start for source line 2656
return;
case 2: // basic block start for source line 2678
REG4 = REG3[REG2 + 2];
REG5 = (REG8 <= REG4) ? 1 : 0;
state = REG5 ? 11 : 1; break;
case 3: // basic block start for source line 2678
REG8 = 1;
state = 2; break;
case 4: // basic block start for source line 2668
REG4 = REG3[REG2 + 1];
REG6 = (REG5 <= REG4) ? 1 : 0;
state = REG6 ? 8 : 3; break;
case 5: // basic block start for source line 2668
REG5 = 1;
state = 4; break;
case 6: // basic block start for source line 2668
REG4 = 1;
REG6 = REG5 + REG4;
REG5 = REG6;
state = 4; break;
case 7: // basic block start for source line 2673
REG4 = -1;
REG8 = REG5 + REG4;
REG7[REG6 + 15] = REG8;
state = 6; break;
case 8: // basic block start for source line 2670
REG4 = REG3[REG2 + 4];
REG8 = REG3[REG2 + 5];
REG9 = REG4 + REG5;
REG4 = REG8[REG9 + 0];
REG8 = static_0_60_su_find_node_with_number;
REG6 = REG8(sp, stack, REG0, REG1, REG4);
REG7 = REG6[1]
REG6 = REG6[0]
state = REG7 ? 7 : 6; break;
case 9: // basic block start for source line 2678
REG4 = 1;
REG5 = REG8 + REG4;
REG8 = REG5;
state = 2; break;
case 10: // basic block start for source line 2683
REG4 = -1;
REG5 = REG8 + REG4;
REG10[REG9 + 15] = REG5;
state = 9; break;
case 11: // basic block start for source line 2680
REG4 = REG3[REG2 + 6];
REG5 = REG3[REG2 + 7];
REG6 = REG4 + REG8;
REG4 = REG5[REG6 + 0];
REG5 = static_0_60_su_find_node_with_number;
REG9 = REG5(sp, stack, REG0, REG1, REG4);
REG10 = REG9[1]
REG9 = REG9[0]
state = REG10 ? 10 : 9; break;
} } }

function static_0_62_copy_m(fp, stack, REG0, REG1) {
var sp;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = 0;
REG5 = (REG0 != REG4) ? 1 : 0;
REG4 = 0;
REG6 = (REG2 != REG4) ? 1 : 0;
REG4 = REG5 & REG6;
state = REG4 ? 1 : 2; break;
case 1: // basic block start for source line 2720
REG4 = REG1[REG0 + 0];
REG3[REG2 + 0] = REG4;
REG4 = REG1[REG0 + 1];
REG3[REG2 + 1] = REG4;
REG4 = REG1[REG0 + 2];
REG3[REG2 + 2] = REG4;
REG4 = REG1[REG0 + 3];
REG3[REG2 + 3] = REG4;
REG4 = REG3[REG2 + 10];
REG5 = REG3[REG2 + 11];
REG6 = REG1[REG0 + 10];
REG7 = REG1[REG0 + 11];
REG8 = REG1[REG0 + 3];
REG9 = do_memmove;
REG9(sp, stack, REG4, REG5, REG6, REG7, REG8);
REG4 = REG3[REG2 + 4];
REG5 = REG3[REG2 + 5];
REG6 = REG1[REG0 + 4];
REG7 = REG1[REG0 + 5];
REG8 = REG1[REG0 + 5];
REG9 = do_memmove;
REG9(sp, stack, REG4, REG5, REG6, REG7, REG8);
REG4 = REG1[REG0 + 5];
REG3[REG2 + 5] = REG4;
REG4 = REG3[REG2 + 6];
REG5 = REG3[REG2 + 7];
REG6 = REG1[REG0 + 6];
REG7 = REG1[REG0 + 7];
REG8 = REG1[REG0 + 7];
REG9 = do_memmove;
REG9(sp, stack, REG4, REG5, REG6, REG7, REG8);
REG4 = REG1[REG0 + 7];
REG3[REG2 + 7] = REG4;
REG4 = REG1[REG0 + 8];
REG3[REG2 + 8] = REG4;
REG4 = REG3[REG2 + 9];
REG5 = REG3[REG2 + 10];
REG6 = REG1[REG0 + 9];
REG7 = REG1[REG0 + 10];
REG8 = REG1[REG0 + 8];
REG9 = do_memmove;
REG9(sp, stack, REG4, REG5, REG6, REG7, REG8);
state = 2; break;
case 2: // basic block start for source line 2717
return;
} } }

function static_0_63_equal_m(fp, stack, REG0, REG1, REG2, REG3) {
var sp;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var REG16;
var REG17;
var REG18;
var REG19;
var REG20;
var REG21;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG6 = 1;
state = 1; break;
case 1: // basic block start for source line 2741
REG7 = (REG6 <= REG4) ? 1 : 0;
state = REG7 ? 4 : 15; break;
case 2: // basic block start for source line 2741
REG7 = 1;
REG8 = REG6 + REG7;
REG6 = REG8;
state = 1; break;
case 3: // basic block start for source line 2742
REG8 = (REG7 <= REG5) ? 1 : 0;
state = REG8 ? 10 : 2; break;
case 4: // basic block start for source line 2742
REG7 = 1;
state = 3; break;
case 5: // basic block start for source line 2742
REG8 = 1;
REG9 = REG7 + REG8;
REG7 = REG9;
state = 3; break;
case 6: // basic block start for source line 2490
REG8 = 8;
REG9 = REG17 / REG8;
REG9 = (REG9).toFixed();
REG8 = REG15 + REG9;
REG9 = REG16[REG8 + 0];
REG8 = REG9 & REG19;
REG9 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
REG10 = (REG14 != REG8) ? 1 : 0;
state = REG10 ? 13 : 5; break;
case 7: // basic block start for source line 2487
REG8 = (REG20 < REG18) ? 1 : 0;
state = REG8 ? 12 : 6; break;
case 8: // basic block start for source line 2490
REG11 = 8;
REG13 = REG10 / REG11;
REG13 = (REG13).toFixed();
REG10 = REG8 + REG13;
REG8 = REG9[REG10 + 0];
REG14 = REG8 & REG12;
REG8 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
REG15 = REG3[REG2 + 10];
REG16 = REG3[REG2 + 11];
REG9 = REG3[REG2 + 2];
REG10 = REG6 * REG9;
REG17 = REG10 + REG7;
REG9 = 8;
REG18 = REG17 % REG9;
REG19 = 1;
REG20 = 0;
state = 7; break;
case 9: // basic block start for source line 2487
REG14 = (REG13 < REG11) ? 1 : 0;
state = REG14 ? 11 : 8; break;
case 10: // basic block start for source line 2743
REG8 = REG1[REG0 + 10];
REG9 = REG1[REG0 + 11];
REG14 = REG1[REG0 + 2];
REG15 = REG6 * REG14;
REG10 = REG15 + REG7;
REG14 = 8;
REG11 = REG10 % REG14;
REG12 = 1;
REG13 = 0;
state = 9; break;
case 11: // basic block start for source line 2488
REG14 = REG12 * <no-name-for-reg>;
REG15 = 1;
REG16 = REG13 + REG15;
REG12 = REG14;
REG13 = REG16;
state = 9; break;
case 12: // basic block start for source line 2488
REG8 = REG19 * <no-name-for-reg>;
REG9 = 1;
REG10 = REG20 + REG9;
REG19 = REG8;
REG20 = REG10;
state = 7; break;
case 13: // basic block start for source line 2744
REG21 = 0;
state = 14; break;
case 14: // basic block start for source line 2736
return REG21;
case 15: // basic block start for source line 2749
REG21 = 1;
state = 14; break;
} } }

function static_0_64_equal_a(fp, stack, REG0, REG1, REG2) {
var sp;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG6 = 0;
REG7 = (REG2 == REG6) ? 1 : 0;
REG6 = 0;
REG8 = (REG4 == REG6) ? 1 : 0;
REG6 = REG7 | REG8;
state = REG6 ? 1 : 6; break;
case 1: // basic block start for source line 2758
REG6 = 0;
state = 2; break;
case 2: // basic block start for source line 2753
return REG6;
case 3: // basic block start for source line 2765
REG6 = 0;
state = 2; break;
case 4: // basic block start for source line 2762
REG6 = REG2 + REG7;
REG8 = REG3[REG6 + 0];
REG9 = REG3[REG6 + 1];
REG6 = REG4 + REG7;
REG10 = REG5[REG6 + 0];
REG11 = REG5[REG6 + 1];
REG6 = REG9[REG8 + 1];
REG12 = REG9[REG8 + 2];
REG13 = static_0_63_equal_m;
REG14 = REG13(sp, stack, REG8, REG9, REG10, REG11, REG6, REG12);
state = REG14 ? 7 : 3; break;
case 5: // basic block start for source line 2761
REG6 = REG1[REG0 + 5];
REG8 = (REG7 < REG6) ? 1 : 0;
state = REG8 ? 4 : 8; break;
case 6: // basic block start for source line 2761
REG7 = 0;
state = 5; break;
case 7: // basic block start for source line 2761
REG6 = 1;
REG8 = REG7 + REG6;
REG7 = REG8;
state = 5; break;
case 8: // basic block start for source line 2769
REG6 = 1;
state = 2; break;
} } }

function static_0_65_exch_rows(fp, stack, REG0, REG1, REG2) {
var sp;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var REG16;
var REG17;
var REG18;
var REG19;
var REG20;
var REG21;
var REG22;
var REG23;
var REG24;
var REG25;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG5 = REG1[REG0 + 4];
REG6 = REG1[REG0 + 5];
REG7 = REG5 + REG2;
REG8 = REG6[REG7 + 0];
REG9 = REG5 + REG3;
REG5 = REG6[REG9 + 0];
REG6[REG7 + 0] = REG5;
REG5 = REG1[REG0 + 4];
REG6 = REG1[REG0 + 5];
REG7 = REG5 + REG3;
REG6[REG7 + 0] = REG8;
REG4 = 1;
state = 1; break;
case 1: // basic block start for source line 2805
REG5 = REG1[REG0 + 2];
REG6 = (REG4 <= REG5) ? 1 : 0;
state = REG6 ? 12 : 19; break;
case 2: // basic block start for source line 2805
REG5 = 1;
REG6 = REG4 + REG5;
REG4 = REG6;
state = 1; break;
case 3: // basic block start for source line 2453
REG5 = 8;
REG6 = REG25 % REG5;
REG5 = 1;
REG7 = REG5 << REG6;
REG5 = 8;
REG6 = REG25 / REG5;
REG6 = (REG6).toFixed();
REG5 = REG23 + REG6;
REG6 = REG24[REG5 + 0];
REG8 = REG6 | REG7;
REG24[REG5 + 0] = REG8;
state = 2; break;
case 4: // basic block start for source line 2505
REG23 = REG1[REG0 + 10];
REG24 = REG1[REG0 + 11];
REG5 = REG1[REG0 + 2];
REG6 = REG3 * REG5;
REG25 = REG6 + REG4;
state = REG25 ? 3 : 2; break;
case 5: // basic block start for source line 2808
<no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
state = REG17 ? 4 : 17; break;
case 6: // basic block start for source line 2453
REG5 = 1;
REG6 = REG5 << REG11;
REG5 = REG16 | REG6;
REG15[REG14 + 0] = REG5;
state = 5; break;
case 7: // basic block start for source line 2505
state = REG10 ? 6 : 5; break;
case 8: // basic block start for source line 2490
REG5 = 8;
REG6 = REG18 / REG5;
REG6 = (REG6).toFixed();
REG5 = REG8 + REG6;
REG6 = REG9[REG5 + 0];
REG5 = REG6 & REG12;
REG6 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
state = REG5 ? 7 : 15; break;
case 9: // basic block start for source line 2487
REG5 = (REG13 < REG19) ? 1 : 0;
state = REG5 ? 14 : 8; break;
case 10: // basic block start for source line 2490
REG7 = 8;
REG20 = REG10 / REG7;
REG20 = (REG20).toFixed();
REG15 = REG9;
REG14 = REG8 + REG20;
REG16 = REG15[REG14 + 0];
REG17 = REG16 & REG6;
REG6 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
REG7 = REG3 * REG5;
REG18 = REG7 + REG4;
REG5 = 8;
REG19 = REG18 % REG5;
REG12 = 1;
REG13 = 0;
state = 9; break;
case 11: // basic block start for source line 2487
REG12 = (REG7 < REG11) ? 1 : 0;
state = REG12 ? 13 : 10; break;
case 12: // basic block start for source line 2806
REG8 = REG1[REG0 + 10];
REG9 = REG1[REG0 + 11];
REG12 = REG2 * REG5;
REG10 = REG12 + REG4;
REG12 = 8;
REG11 = REG10 % REG12;
REG6 = 1;
REG7 = 0;
state = 11; break;
case 13: // basic block start for source line 2488
REG12 = REG6 * <no-name-for-reg>;
REG13 = 1;
REG14 = REG7 + REG13;
REG6 = REG12;
REG7 = REG14;
state = 11; break;
case 14: // basic block start for source line 2488
REG5 = REG12 * <no-name-for-reg>;
REG6 = 1;
REG7 = REG13 + REG6;
REG12 = REG5;
REG13 = REG7;
state = 9; break;
case 15: // basic block start for source line 2507
state = REG10 ? 16 : 5; break;
case 16: // basic block start for source line 2462
REG5 = 1;
REG6 = REG5 << REG11;
REG5 = REG16 & <no-name-for-reg>;
REG15[REG14 + 0] = REG5;
state = 5; break;
case 17: // basic block start for source line 2507
REG20 = REG1[REG0 + 10];
REG21 = REG1[REG0 + 11];
REG5 = REG1[REG0 + 2];
REG6 = REG3 * REG5;
REG22 = REG6 + REG4;
state = REG22 ? 18 : 2; break;
case 18: // basic block start for source line 2462
REG5 = 8;
REG6 = REG22 % REG5;
REG5 = 1;
REG7 = REG5 << REG6;
REG5 = 8;
REG6 = REG22 / REG5;
REG6 = (REG6).toFixed();
REG5 = REG20 + REG6;
REG6 = REG21[REG5 + 0];
REG7 = REG6 & <no-name-for-reg>;
REG21[REG5 + 0] = REG7;
state = 2; break;
case 19: // basic block start for source line 2784
return;
} } }

function static_0_66_exch_columns(fp, stack, REG0, REG1, REG2) {
var sp;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var REG16;
var REG17;
var REG18;
var REG19;
var REG20;
var REG21;
var REG22;
var REG23;
var REG24;
var REG25;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG5 = REG1[REG0 + 6];
REG6 = REG1[REG0 + 7];
REG7 = REG5 + REG2;
REG8 = REG6[REG7 + 0];
REG9 = REG5 + REG3;
REG5 = REG6[REG9 + 0];
REG6[REG7 + 0] = REG5;
REG5 = REG1[REG0 + 6];
REG6 = REG1[REG0 + 7];
REG7 = REG5 + REG3;
REG6[REG7 + 0] = REG8;
REG4 = 1;
state = 1; break;
case 1: // basic block start for source line 2836
REG5 = REG1[REG0 + 1];
REG6 = (REG4 <= REG5) ? 1 : 0;
state = REG6 ? 12 : 19; break;
case 2: // basic block start for source line 2836
REG5 = 1;
REG6 = REG4 + REG5;
REG4 = REG6;
state = 1; break;
case 3: // basic block start for source line 2453
REG5 = 8;
REG6 = REG25 % REG5;
REG5 = 1;
REG7 = REG5 << REG6;
REG5 = 8;
REG6 = REG25 / REG5;
REG6 = (REG6).toFixed();
REG5 = REG23 + REG6;
REG6 = REG24[REG5 + 0];
REG8 = REG6 | REG7;
REG24[REG5 + 0] = REG8;
state = 2; break;
case 4: // basic block start for source line 2505
REG23 = REG1[REG0 + 10];
REG24 = REG1[REG0 + 11];
REG5 = REG1[REG0 + 2];
REG6 = REG4 * REG5;
REG25 = REG6 + REG3;
state = REG25 ? 3 : 2; break;
case 5: // basic block start for source line 2839
<no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
state = REG15 ? 4 : 17; break;
case 6: // basic block start for source line 2453
REG5 = 1;
REG6 = REG5 << REG9;
REG5 = REG14 | REG6;
REG13[REG12 + 0] = REG5;
state = 5; break;
case 7: // basic block start for source line 2505
state = REG8 ? 6 : 5; break;
case 8: // basic block start for source line 2490
REG7 = 8;
REG10 = REG16 / REG7;
REG10 = (REG10).toFixed();
REG7 = REG5 + REG10;
REG5 = REG6[REG7 + 0];
REG6 = REG5 & REG18;
REG5 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
state = REG6 ? 7 : 15; break;
case 9: // basic block start for source line 2487
REG7 = (REG19 < REG17) ? 1 : 0;
state = REG7 ? 14 : 8; break;
case 10: // basic block start for source line 2490
REG11 = 8;
REG20 = REG8 / REG11;
REG20 = (REG20).toFixed();
REG13 = REG6;
REG12 = REG5 + REG20;
REG14 = REG13[REG12 + 0];
REG15 = REG14 & REG10;
REG10 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
REG16 = REG7 + REG3;
REG7 = 8;
REG17 = REG16 % REG7;
REG18 = 1;
REG19 = 0;
state = 9; break;
case 11: // basic block start for source line 2487
REG12 = (REG11 < REG9) ? 1 : 0;
state = REG12 ? 13 : 10; break;
case 12: // basic block start for source line 2837
REG5 = REG1[REG0 + 10];
REG6 = REG1[REG0 + 11];
REG12 = REG1[REG0 + 2];
REG7 = REG4 * REG12;
REG8 = REG7 + REG2;
REG12 = 8;
REG9 = REG8 % REG12;
REG10 = 1;
REG11 = 0;
state = 11; break;
case 13: // basic block start for source line 2488
REG12 = REG10 * <no-name-for-reg>;
REG13 = 1;
REG14 = REG11 + REG13;
REG10 = REG12;
REG11 = REG14;
state = 11; break;
case 14: // basic block start for source line 2488
REG7 = REG18 * <no-name-for-reg>;
REG10 = 1;
REG11 = REG19 + REG10;
REG18 = REG7;
REG19 = REG11;
state = 9; break;
case 15: // basic block start for source line 2507
state = REG8 ? 16 : 5; break;
case 16: // basic block start for source line 2462
REG5 = 1;
REG6 = REG5 << REG9;
REG5 = REG14 & <no-name-for-reg>;
REG13[REG12 + 0] = REG5;
state = 5; break;
case 17: // basic block start for source line 2507
REG20 = REG1[REG0 + 10];
REG21 = REG1[REG0 + 11];
REG5 = REG1[REG0 + 2];
REG6 = REG4 * REG5;
REG22 = REG6 + REG3;
state = REG22 ? 18 : 2; break;
case 18: // basic block start for source line 2462
REG5 = 8;
REG6 = REG22 % REG5;
REG5 = 1;
REG7 = REG5 << REG6;
REG5 = 8;
REG6 = REG22 / REG5;
REG6 = (REG6).toFixed();
REG5 = REG20 + REG6;
REG6 = REG21[REG5 + 0];
REG7 = REG6 & <no-name-for-reg>;
REG21[REG5 + 0] = REG7;
state = 2; break;
case 19: // basic block start for source line 2815
return;
} } }

function static_0_67_reverse_r(fp, stack, REG0, REG1, REG2) {
var sp;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = REG2;
REG5 = REG3;
REG6 = 0;
state = 1; break;
case 1: // basic block start for source line 2852
REG2 = (REG4 < REG5) ? 1 : 0;
state = REG2 ? 2 : 3; break;
case 2: // basic block start for source line 2853
REG2 = 1;
REG3 = REG6 + REG2;
REG2 = static_0_65_exch_rows;
REG2(sp, stack, REG0, REG1, REG4, REG5);
REG2 = 1;
REG7 = REG4 + REG2;
REG2 = -1;
REG8 = REG5 + REG2;
REG4 = REG7;
REG5 = REG8;
REG6 = REG3;
state = 1; break;
case 3: // basic block start for source line 2846
return REG6;
} } }

function static_0_68_reverse_c(fp, stack, REG0, REG1, REG2) {
var sp;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = REG2;
REG5 = REG3;
REG6 = 0;
state = 1; break;
case 1: // basic block start for source line 2866
REG2 = (REG4 < REG5) ? 1 : 0;
state = REG2 ? 2 : 3; break;
case 2: // basic block start for source line 2867
REG2 = 1;
REG3 = REG6 + REG2;
REG2 = static_0_66_exch_columns;
REG2(sp, stack, REG0, REG1, REG4, REG5);
REG2 = 1;
REG7 = REG4 + REG2;
REG2 = -1;
REG8 = REG5 + REG2;
REG4 = REG7;
REG5 = REG8;
REG6 = REG3;
state = 1; break;
case 3: // basic block start for source line 2860
return REG6;
} } }

function static_0_69_row_barycenter(fp, stack, REG0, REG1, REG2) {
var sp;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = 1;
REG5 = 0;
REG6 = 0;
state = 1; break;
case 1: // basic block start for source line 2880
REG7 = (REG4 <= REG3) ? 1 : 0;
state = REG7 ? 5 : 8; break;
case 2: // basic block start for source line 2881
REG7 = 1;
REG8 = REG4 + REG7;
REG4 = REG8;
REG5 = REG13;
REG6 = REG14;
state = 1; break;
case 3: // basic block start for source line 2490
REG10 = 8;
REG12 = REG9 / REG10;
REG12 = (REG12).toFixed();
REG9 = REG7 + REG12;
REG7 = REG8[REG9 + 0];
REG8 = REG7 & REG11;
REG7 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
REG13 = REG5;
REG14 = REG6;
state = REG8 ? 7 : 2; break;
case 4: // basic block start for source line 2487
REG13 = (REG12 < REG10) ? 1 : 0;
state = REG13 ? 6 : 3; break;
case 5: // basic block start for source line 2881
REG7 = REG1[REG0 + 10];
REG8 = REG1[REG0 + 11];
REG13 = REG1[REG0 + 2];
REG14 = REG2 * REG13;
REG9 = REG14 + REG4;
REG13 = 8;
REG10 = REG9 % REG13;
REG11 = 1;
REG12 = 0;
state = 4; break;
case 6: // basic block start for source line 2488
REG13 = REG11 * <no-name-for-reg>;
REG14 = 1;
REG15 = REG12 + REG14;
REG11 = REG13;
REG12 = REG15;
state = 4; break;
case 7: // basic block start for source line 2882
REG7 = REG5 + REG4;
REG5 = 1;
REG8 = REG6 + REG5;
REG13 = REG7;
REG14 = REG8;
state = 2; break;
case 8: // basic block start for source line 2887
state = REG6 ? 11 : 9; break;
case 9: // basic block start for source line 2888
REG15 = REG0;
state = 10; break;
case 10: // basic block start for source line 2874
return REG15;
case 11: // basic block start for source line 2890
REG15 = REG0;
state = 10; break;
} } }

function static_0_70_column_barycenter(fp, stack, REG0, REG1, REG2) {
var sp;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = 1;
REG5 = 0;
REG6 = 0;
state = 1; break;
case 1: // basic block start for source line 2900
REG7 = (REG4 <= REG3) ? 1 : 0;
state = REG7 ? 5 : 8; break;
case 2: // basic block start for source line 2901
REG7 = 1;
REG8 = REG4 + REG7;
REG4 = REG8;
REG5 = REG13;
REG6 = REG14;
state = 1; break;
case 3: // basic block start for source line 2490
REG10 = 8;
REG12 = REG9 / REG10;
REG12 = (REG12).toFixed();
REG9 = REG7 + REG12;
REG7 = REG8[REG9 + 0];
REG8 = REG7 & REG11;
REG7 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
REG13 = REG5;
REG14 = REG6;
state = REG8 ? 7 : 2; break;
case 4: // basic block start for source line 2487
REG13 = (REG12 < REG10) ? 1 : 0;
state = REG13 ? 6 : 3; break;
case 5: // basic block start for source line 2901
REG7 = REG1[REG0 + 10];
REG8 = REG1[REG0 + 11];
REG13 = REG1[REG0 + 2];
REG14 = REG4 * REG13;
REG9 = REG14 + REG2;
REG13 = 8;
REG10 = REG9 % REG13;
REG11 = 1;
REG12 = 0;
state = 4; break;
case 6: // basic block start for source line 2488
REG13 = REG11 * <no-name-for-reg>;
REG14 = 1;
REG15 = REG12 + REG14;
REG11 = REG13;
REG12 = REG15;
state = 4; break;
case 7: // basic block start for source line 2902
REG7 = REG5 + REG4;
REG5 = 1;
REG8 = REG6 + REG5;
REG13 = REG7;
REG14 = REG8;
state = 2; break;
case 8: // basic block start for source line 2907
state = REG6 ? 11 : 9; break;
case 9: // basic block start for source line 2908
REG15 = REG0;
state = 10; break;
case 10: // basic block start for source line 2894
return REG15;
case 11: // basic block start for source line 2910
REG15 = REG0;
state = 10; break;
} } }

function static_0_71_r_r(fp, stack, REG0, REG1, REG2, REG3) {
var sp;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG6 = 1;
state = 1; break;
case 1: // basic block start for source line 2921
REG7 = (REG6 <= REG4) ? 1 : 0;
state = REG7 ? 2 : 3; break;
case 2: // basic block start for source line 2922
REG7 = static_0_69_row_barycenter;
REG8 = REG7(sp, stack, REG0, REG1, REG6, REG5);
REG7 = REG1[REG0 + 9];
REG9 = REG1[REG0 + 10];
REG10 = REG7 + REG6;
REG9[REG10 + 0] = REG8;
REG7 = 1;
REG8 = REG6 + REG7;
REG6 = REG8;
state = 1; break;
case 3: // basic block start for source line 2925
REG7 = 1;
REG8 = 0;
state = 4; break;
case 4: // basic block start for source line 2925
REG5 = (REG7 < REG4) ? 1 : 0;
state = REG5 ? 8 : 14; break;
case 5: // basic block start for source line 2932
REG5 = 1;
REG6 = REG11 + REG5;
REG7 = REG6;
REG8 = REG12;
state = 4; break;
case 6: // basic block start for source line 2932
REG5 = (REG9 > REG7) ? 1 : 0;
REG11 = REG7;
REG12 = REG8;
state = REG5 ? 11 : 5; break;
case 7: // basic block start for source line 2928
REG5 = (REG9 < REG4) ? 1 : 0;
state = REG5 ? 10 : 6; break;
case 8: // basic block start for source line 2926
REG9 = REG7;
state = 7; break;
case 9: // basic block start for source line 2928
REG9 = REG10;
state = 7; break;
case 10: // basic block start for source line 2928
REG5 = REG1[REG0 + 9];
REG6 = REG1[REG0 + 10];
REG11 = 1;
REG10 = REG9 + REG11;
REG11 = REG5 + REG10;
REG12 = REG6[REG11 + 0];
REG11 = REG5 + REG9;
REG5 = REG6[REG11 + 0];
state = <no-name-for-reg> ? 9 : 6; break;
case 11: // basic block start for source line 2933
REG5 = static_0_67_reverse_r;
REG6 = REG5(sp, stack, REG0, REG1, REG7, REG9);
REG13 = REG8 + REG6;
REG14 = REG13;
state = REG3 ? 12 : 13; break;
case 12: // basic block start for source line 2936
REG5 = static_0_68_reverse_c;
REG6 = REG5(sp, stack, REG2, REG3, REG7, REG9);
REG5 = REG13 + REG6;
REG14 = REG5;
state = 13; break;
case 13: // basic block start for source line 2939
REG11 = REG9;
REG12 = REG14;
state = 5; break;
case 14: // basic block start for source line 2915
return REG8;
} } }

function static_0_72_r_c(fp, stack, REG0, REG1, REG2, REG3) {
var sp;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG6 = 1;
state = 1; break;
case 1: // basic block start for source line 2954
REG7 = (REG6 <= REG5) ? 1 : 0;
state = REG7 ? 2 : 3; break;
case 2: // basic block start for source line 2955
REG7 = static_0_70_column_barycenter;
REG8 = REG7(sp, stack, REG0, REG1, REG6, REG4);
REG7 = REG1[REG0 + 9];
REG9 = REG1[REG0 + 10];
REG10 = REG7 + REG6;
REG9[REG10 + 0] = REG8;
REG7 = 1;
REG8 = REG6 + REG7;
REG6 = REG8;
state = 1; break;
case 3: // basic block start for source line 2958
REG7 = 1;
REG8 = 0;
state = 4; break;
case 4: // basic block start for source line 2958
REG4 = (REG7 < REG5) ? 1 : 0;
state = REG4 ? 8 : 14; break;
case 5: // basic block start for source line 2965
REG4 = 1;
REG6 = REG11 + REG4;
REG7 = REG6;
REG8 = REG12;
state = 4; break;
case 6: // basic block start for source line 2965
REG4 = (REG9 > REG7) ? 1 : 0;
REG11 = REG7;
REG12 = REG8;
state = REG4 ? 11 : 5; break;
case 7: // basic block start for source line 2961
REG4 = (REG9 < REG5) ? 1 : 0;
state = REG4 ? 10 : 6; break;
case 8: // basic block start for source line 2959
REG9 = REG7;
state = 7; break;
case 9: // basic block start for source line 2961
REG9 = REG10;
state = 7; break;
case 10: // basic block start for source line 2961
REG4 = REG1[REG0 + 9];
REG6 = REG1[REG0 + 10];
REG11 = 1;
REG10 = REG9 + REG11;
REG11 = REG4 + REG10;
REG12 = REG6[REG11 + 0];
REG11 = REG4 + REG9;
REG4 = REG6[REG11 + 0];
state = <no-name-for-reg> ? 9 : 6; break;
case 11: // basic block start for source line 2966
REG4 = static_0_68_reverse_c;
REG6 = REG4(sp, stack, REG0, REG1, REG7, REG9);
REG13 = REG8 + REG6;
REG14 = REG13;
state = REG3 ? 12 : 13; break;
case 12: // basic block start for source line 2969
REG4 = static_0_67_reverse_r;
REG6 = REG4(sp, stack, REG2, REG3, REG7, REG9);
REG4 = REG13 + REG6;
REG14 = REG4;
state = 13; break;
case 13: // basic block start for source line 2972
REG11 = REG9;
REG12 = REG14;
state = 5; break;
case 14: // basic block start for source line 2948
return REG8;
} } }

function static_0_73_b_r(fp, stack, REG0, REG1, REG2, REG3) {
var sp;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var REG16;
var REG17;
var REG18;
var REG19;
var REG20;
var REG21;
var REG22;
var REG23;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG6 = 1;
state = 1; break;
case 1: // basic block start for source line 2989
REG7 = (REG6 <= REG4) ? 1 : 0;
state = REG7 ? 2 : 3; break;
case 2: // basic block start for source line 2990
REG7 = static_0_69_row_barycenter;
REG8 = REG7(sp, stack, REG0, REG1, REG6, REG5);
REG7 = REG1[REG0 + 9];
REG9 = REG1[REG0 + 10];
REG10 = REG7 + REG6;
REG9[REG10 + 0] = REG8;
REG7 = 1;
REG8 = REG6 + REG7;
REG6 = REG8;
state = 1; break;
case 3: // basic block start for source line 2993
REG7 = REG4;
REG8 = 0;
state = 4; break;
case 4: // basic block start for source line 2993
REG4 = 1;
REG5 = (REG7 > REG4) ? 1 : 0;
state = REG5 ? 6 : 20; break;
case 5: // basic block start for source line 2994
REG4 = -1;
REG5 = REG7 + REG4;
REG7 = REG5;
REG8 = REG10;
state = 4; break;
case 6: // basic block start for source line 2994
REG4 = REG1[REG0 + 9];
REG5 = REG1[REG0 + 10];
REG6 = REG4 + REG7;
REG4 = REG5[REG6 + 0];
REG10 = REG8;
state = <no-name-for-reg> ? 7 : 5; break;
case 7: // basic block start for source line 2995
REG11 = 1;
REG12 = REG8;
state = 8; break;
case 8: // basic block start for source line 2995
REG4 = (REG11 < REG7) ? 1 : 0;
state = REG4 ? 10 : 19; break;
case 9: // basic block start for source line 2996
REG4 = 1;
REG5 = REG11 + REG4;
REG11 = REG5;
REG12 = REG16;
state = 8; break;
case 10: // basic block start for source line 2996
REG13 = REG1[REG0 + 9];
REG14 = REG1[REG0 + 10];
REG4 = REG13 + REG11;
REG15 = REG14[REG4 + 0];
REG16 = REG12;
state = <no-name-for-reg> ? 11 : 9; break;
case 11: // basic block start for source line 2997
REG4 = 1;
REG5 = REG11 + REG4;
REG17 = REG5;
state = 12; break;
case 12: // basic block start for source line 2998
REG19 = REG14;
REG18 = REG13 + REG17;
REG20 = REG19[REG18 + 0];
state = <no-name-for-reg> ? 13 : 14; break;
case 13: // basic block start for source line 2999
REG4 = 1;
REG5 = REG17 + REG4;
REG17 = REG5;
state = 12; break;
case 14: // basic block start for source line 3001
REG21 = REG12;
state = <no-name-for-reg> ? 15 : 18; break;
case 15: // basic block start for source line 3002
REG4 = 1;
REG22 = REG12 + REG4;
REG19[REG18 + 0] = REG15;
REG4 = REG1[REG0 + 9];
REG5 = REG1[REG0 + 10];
REG6 = REG4 + REG11;
REG5[REG6 + 0] = REG20;
REG4 = static_0_65_exch_rows;
REG4(sp, stack, REG0, REG1, REG11, REG17);
REG23 = REG22;
state = REG3 ? 16 : 17; break;
case 16: // basic block start for source line 3009
REG4 = 1;
REG5 = REG22 + REG4;
REG4 = static_0_66_exch_columns;
REG4(sp, stack, REG2, REG3, REG11, REG17);
REG23 = REG5;
state = 17; break;
case 17: // basic block start for source line 3008
REG21 = REG23;
state = 18; break;
case 18: // basic block start for source line 3001
REG16 = REG21;
state = 9; break;
case 19: // basic block start for source line 2995
REG10 = REG12;
state = 5; break;
case 20: // basic block start for source line 2981
return REG8;
} } }

function static_0_74_b_c(fp, stack, REG0, REG1, REG2, REG3) {
var sp;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var REG16;
var REG17;
var REG18;
var REG19;
var REG20;
var REG21;
var REG22;
var REG23;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG6 = 1;
state = 1; break;
case 1: // basic block start for source line 3031
REG7 = (REG6 <= REG5) ? 1 : 0;
state = REG7 ? 2 : 3; break;
case 2: // basic block start for source line 3032
REG7 = static_0_70_column_barycenter;
REG8 = REG7(sp, stack, REG0, REG1, REG6, REG4);
REG7 = REG1[REG0 + 9];
REG9 = REG1[REG0 + 10];
REG10 = REG7 + REG6;
REG9[REG10 + 0] = REG8;
REG7 = 1;
REG8 = REG6 + REG7;
REG6 = REG8;
state = 1; break;
case 3: // basic block start for source line 3035
REG7 = REG5;
REG8 = 0;
state = 4; break;
case 4: // basic block start for source line 3035
REG4 = 1;
REG5 = (REG7 > REG4) ? 1 : 0;
state = REG5 ? 6 : 20; break;
case 5: // basic block start for source line 3036
REG4 = -1;
REG5 = REG7 + REG4;
REG7 = REG5;
REG8 = REG10;
state = 4; break;
case 6: // basic block start for source line 3036
REG4 = REG1[REG0 + 9];
REG5 = REG1[REG0 + 10];
REG6 = REG4 + REG7;
REG4 = REG5[REG6 + 0];
REG10 = REG8;
state = <no-name-for-reg> ? 7 : 5; break;
case 7: // basic block start for source line 3037
REG11 = 1;
REG12 = REG8;
state = 8; break;
case 8: // basic block start for source line 3037
REG4 = (REG11 < REG7) ? 1 : 0;
state = REG4 ? 10 : 19; break;
case 9: // basic block start for source line 3038
REG4 = 1;
REG5 = REG11 + REG4;
REG11 = REG5;
REG12 = REG16;
state = 8; break;
case 10: // basic block start for source line 3038
REG13 = REG1[REG0 + 9];
REG14 = REG1[REG0 + 10];
REG4 = REG13 + REG11;
REG15 = REG14[REG4 + 0];
REG16 = REG12;
state = <no-name-for-reg> ? 11 : 9; break;
case 11: // basic block start for source line 3039
REG4 = 1;
REG5 = REG11 + REG4;
REG17 = REG5;
state = 12; break;
case 12: // basic block start for source line 3041
REG19 = REG14;
REG18 = REG13 + REG17;
REG20 = REG19[REG18 + 0];
state = <no-name-for-reg> ? 13 : 14; break;
case 13: // basic block start for source line 3042
REG4 = 1;
REG5 = REG17 + REG4;
REG17 = REG5;
state = 12; break;
case 14: // basic block start for source line 3045
REG21 = REG12;
state = <no-name-for-reg> ? 15 : 18; break;
case 15: // basic block start for source line 3046
REG4 = 1;
REG22 = REG12 + REG4;
REG19[REG18 + 0] = REG15;
REG4 = REG1[REG0 + 9];
REG5 = REG1[REG0 + 10];
REG6 = REG4 + REG11;
REG5[REG6 + 0] = REG20;
REG4 = static_0_66_exch_columns;
REG4(sp, stack, REG0, REG1, REG11, REG17);
REG23 = REG22;
state = REG3 ? 16 : 17; break;
case 16: // basic block start for source line 3054
REG4 = 1;
REG5 = REG22 + REG4;
REG4 = static_0_65_exch_rows;
REG4(sp, stack, REG2, REG3, REG11, REG17);
REG23 = REG5;
state = 17; break;
case 17: // basic block start for source line 3053
REG21 = REG23;
state = 18; break;
case 18: // basic block start for source line 3045
REG16 = REG21;
state = 9; break;
case 19: // basic block start for source line 3037
REG10 = REG12;
state = 5; break;
case 20: // basic block start for source line 3023
return REG8;
} } }

function static_0_75_sorted(fp, stack, REG0, REG1) {
var sp;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = 1;
state = 1; break;
case 1: // basic block start for source line 3071
REG4 = (REG3 < REG2) ? 1 : 0;
state = REG4 ? 3 : 7; break;
case 2: // basic block start for source line 3071
REG3 = REG4;
state = 1; break;
case 3: // basic block start for source line 3073
REG6 = REG0 + REG3;
REG7 = REG1[REG6 + 0];
REG6 = 1;
REG4 = REG3 + REG6;
REG3 = REG0 + REG4;
REG5 = REG1[REG3 + 0];
state = <no-name-for-reg> ? 4 : 2; break;
case 4: // basic block start for source line 3073
state = <no-name-for-reg> ? 5 : 2; break;
case 5: // basic block start for source line 3074
REG6 = 0;
state = 6; break;
case 6: // basic block start for source line 3067
return REG6;
case 7: // basic block start for source line 3078
REG6 = 1;
state = 6; break;
} } }

function static_0_76_bc_n(fp, stack, REG0, REG1, REG2) {
var sp;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var REG16;
var REG17;
var REG18;
var REG19;
var REG20;
var REG21;
var REG22;
var REG23;
var REG24;
var REG25;
var REG26;
var REG27;
var REG28;
var REG29;
var REG30;
var REG31;
var REG32;
var REG33;
var REG34;
var REG35;
var REG36;
var REG37;
var REG38;
var REG39;
var REG40;
var REG41;
var REG42;
var REG43;
var REG44;
var REG45;
var REG46;
var REG47;
var REG48;
var REG49;
var REG50;
var REG51;
var REG52;
var REG53;
var REG54;
var REG55;
var REG56;
var REG57;
var REG58;
var REG59;
var REG60;
var REG61;
var REG62;
var REG63;
var REG64;
var REG65;
var REG66;
var REG67;
var REG68;
var REG69;
var REG70;
var REG71;
var REG72;
var REG73;
var REG74;
var REG75;
var REG76;
var REG77;
var REG78;
var REG79;
var REG80;
var REG81;
var REG82;
var REG83;
var REG84;
var REG85;
var REG86;
var REG87;
var REG88;
var REG89;
var REG90;
var REG91;
var REG92;
var REG93;
var REG94;
var REG95;
var REG96;
var REG97;
var REG98;
var REG99;
var REG100;
var REG101;
var REG102;
var REG103;
var REG104;
var REG105;
var REG106;
var REG107;
var REG108;
var REG109;
var REG110;
var REG111;
var REG112;
var REG113;
var REG114;
var REG115;
var REG116;
var REG117;
var REG118;
var REG119;
var REG120;
var REG121;
var REG122;
var REG123;
var REG124;
var REG125;
var REG126;
var REG127;
var REG128;
var REG129;
var REG130;
var REG131;
var REG132;
var REG133;
var REG134;
var REG135;
var REG136;
var REG137;
var REG138;
var REG139;
var REG140;
var REG141;
var REG142;
var REG143;
var REG144;
var REG145;
var REG146;
var REG147;
var REG148;
var REG149;
var REG150;
var REG151;
var REG152;
var REG153;
var REG154;
var REG155;
var REG156;
var REG157;
var REG158;
var REG159;
var REG160;
var REG161;
var REG162;
var REG163;
var REG164;
var REG165;
var REG166;
var REG167;
var REG168;
var REG169;
var REG170;
var REG171;
var REG172;
var REG173;
var REG174;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG15 = 20;
if (REG2) { REG5 = REG2; } else { REG5 = REG15; }
REG15 = 40;
if (REG3) { REG6 = REG3; } else { REG6 = REG15; }
REG15 = REG1[REG0 + 5];
REG16 = 1;
REG17 = calloc;
REG18 = REG17(sp, stack, REG16, REG15);
REG19 = REG18[1]
REG18 = REG18[0]
REG7 = REG18;
REG8 = REG19;
REG15 = REG1[REG0 + 5];
REG16 = 1;
REG17 = calloc;
REG18 = REG17(sp, stack, REG16, REG15);
REG19 = REG18[1]
REG18 = REG18[0]
REG9 = REG18;
REG10 = REG19;
REG15 = REG1[REG0 + 5];
REG16 = 1;
REG17 = calloc;
REG18 = REG17(sp, stack, REG16, REG15);
REG19 = REG18[1]
REG18 = REG18[0]
REG11 = REG18;
REG12 = REG19;
REG15 = REG1[REG0 + 5];
REG16 = 1;
REG17 = calloc;
REG18 = REG17(sp, stack, REG16, REG15);
REG19 = REG18[1]
REG18 = REG18[0]
REG13 = REG18;
REG14 = REG19;
REG4 = 0;
state = 1; break;
case 1: // basic block start for source line 3242
REG2 = REG1[REG0 + 5];
REG3 = (REG4 < REG2) ? 1 : 0;
state = REG3 ? 2 : 3; break;
case 2: // basic block start for source line 3243
REG2 = 11;
REG3 = 1;
REG15 = calloc;
REG16 = REG15(sp, stack, REG3, REG2);
REG17 = REG16[1]
REG16 = REG16[0]
REG2 = REG16;
REG3 = REG17;
REG15 = REG7 + REG4;
REG8[REG15 + 0] = REG2;
REG8[REG15 + 1] = REG3;
REG2 = 11;
REG3 = 1;
REG15 = calloc;
REG16 = REG15(sp, stack, REG3, REG2);
REG17 = REG16[1]
REG16 = REG16[0]
REG2 = REG16;
REG3 = REG17;
REG15 = REG9 + REG4;
REG10[REG15 + 0] = REG2;
REG10[REG15 + 1] = REG3;
REG2 = 11;
REG3 = 1;
REG15 = calloc;
REG16 = REG15(sp, stack, REG3, REG2);
REG17 = REG16[1]
REG16 = REG16[0]
REG2 = REG16;
REG3 = REG17;
REG15 = REG11 + REG4;
REG12[REG15 + 0] = REG2;
REG12[REG15 + 1] = REG3;
REG2 = 11;
REG3 = 1;
REG15 = calloc;
REG16 = REG15(sp, stack, REG3, REG2);
REG17 = REG16[1]
REG16 = REG16[0]
REG2 = REG16;
REG3 = REG17;
REG15 = REG13 + REG4;
REG14[REG15 + 0] = REG2;
REG14[REG15 + 1] = REG3;
REG2 = 1;
REG3 = REG4 + REG2;
REG4 = REG3;
state = 1; break;
case 3: // basic block start for source line 3250
REG15 = 0;
state = 4; break;
case 4: // basic block start for source line 3250
REG2 = REG1[REG0 + 5];
REG3 = (REG15 < REG2) ? 1 : 0;
state = REG3 ? 7 : 9; break;
case 5: // basic block start for source line 3282
REG2 = REG17[REG16 + 0];
REG3 = REG17[REG16 + 1];
REG4 = REG3[REG2 + 8];
REG2 = 1;
REG3 = calloc;
REG25 = REG3(sp, stack, REG2, REG4);
REG26 = REG25[1]
REG25 = REG25[0]
REG2 = REG25;
REG3 = REG26;
REG4 = REG17[REG16 + 0];
REG25 = REG17[REG16 + 1];
REG25[REG4 + 9] = REG2;
REG25[REG4 + 10] = REG3;
REG2 = REG19[REG18 + 0];
REG3 = REG19[REG18 + 1];
REG4 = REG3[REG2 + 8];
REG2 = 1;
REG3 = calloc;
REG25 = REG3(sp, stack, REG2, REG4);
REG26 = REG25[1]
REG25 = REG25[0]
REG2 = REG25;
REG3 = REG26;
REG4 = REG19[REG18 + 0];
REG25 = REG19[REG18 + 1];
REG25[REG4 + 9] = REG2;
REG25[REG4 + 10] = REG3;
REG2 = REG21[REG20 + 0];
REG3 = REG21[REG20 + 1];
REG4 = REG3[REG2 + 8];
REG2 = 1;
REG3 = calloc;
REG25 = REG3(sp, stack, REG2, REG4);
REG26 = REG25[1]
REG25 = REG25[0]
REG2 = REG25;
REG3 = REG26;
REG4 = REG21[REG20 + 0];
REG25 = REG21[REG20 + 1];
REG25[REG4 + 9] = REG2;
REG25[REG4 + 10] = REG3;
REG2 = REG23[REG22 + 0];
REG3 = REG23[REG22 + 1];
REG4 = REG3[REG2 + 8];
REG2 = 1;
REG3 = calloc;
REG25 = REG3(sp, stack, REG2, REG4);
REG26 = REG25[1]
REG25 = REG25[0]
REG2 = REG25;
REG3 = REG26;
REG4 = REG23[REG22 + 0];
REG25 = REG23[REG22 + 1];
REG25[REG4 + 9] = REG2;
REG25[REG4 + 10] = REG3;
REG2 = REG17[REG16 + 0];
REG3 = REG17[REG16 + 1];
REG4 = REG3[REG2 + 1];
REG25 = 1;
REG26 = REG4 + REG25;
REG3[REG2 + 5] = REG26;
REG2 = REG17[REG16 + 0];
REG3 = REG17[REG16 + 1];
REG4 = REG3[REG2 + 1];
REG2 = 1;
REG3 = REG4 + REG2;
REG2 = REG19[REG18 + 0];
REG4 = REG19[REG18 + 1];
REG4[REG2 + 5] = REG3;
REG2 = REG17[REG16 + 0];
REG3 = REG17[REG16 + 1];
REG4 = REG3[REG2 + 1];
REG2 = 1;
REG3 = REG4 + REG2;
REG2 = REG21[REG20 + 0];
REG4 = REG21[REG20 + 1];
REG4[REG2 + 5] = REG3;
REG2 = REG17[REG16 + 0];
REG3 = REG17[REG16 + 1];
REG4 = REG3[REG2 + 1];
REG2 = 1;
REG3 = REG4 + REG2;
REG2 = REG23[REG22 + 0];
REG4 = REG23[REG22 + 1];
REG4[REG2 + 5] = REG3;
REG2 = REG17[REG16 + 0];
REG3 = REG17[REG16 + 1];
REG4 = REG3[REG2 + 5];
REG2 = 1;
REG3 = calloc;
REG25 = REG3(sp, stack, REG2, REG4);
REG26 = REG25[1]
REG25 = REG25[0]
REG2 = REG25;
REG3 = REG26;
REG4 = REG17[REG16 + 0];
REG25 = REG17[REG16 + 1];
REG25[REG4 + 4] = REG2;
REG25[REG4 + 5] = REG3;
REG2 = REG19[REG18 + 0];
REG3 = REG19[REG18 + 1];
REG4 = REG3[REG2 + 5];
REG2 = 1;
REG3 = calloc;
REG25 = REG3(sp, stack, REG2, REG4);
REG26 = REG25[1]
REG25 = REG25[0]
REG2 = REG25;
REG3 = REG26;
REG4 = REG19[REG18 + 0];
REG25 = REG19[REG18 + 1];
REG25[REG4 + 4] = REG2;
REG25[REG4 + 5] = REG3;
REG2 = REG21[REG20 + 0];
REG3 = REG21[REG20 + 1];
REG4 = REG3[REG2 + 5];
REG2 = 1;
REG3 = calloc;
REG25 = REG3(sp, stack, REG2, REG4);
REG26 = REG25[1]
REG25 = REG25[0]
REG2 = REG25;
REG3 = REG26;
REG4 = REG21[REG20 + 0];
REG25 = REG21[REG20 + 1];
REG25[REG4 + 4] = REG2;
REG25[REG4 + 5] = REG3;
REG2 = REG23[REG22 + 0];
REG3 = REG23[REG22 + 1];
REG4 = REG3[REG2 + 5];
REG2 = 1;
REG3 = calloc;
REG25 = REG3(sp, stack, REG2, REG4);
REG26 = REG25[1]
REG25 = REG25[0]
REG2 = REG25;
REG3 = REG26;
REG4 = REG23[REG22 + 0];
REG25 = REG23[REG22 + 1];
REG25[REG4 + 4] = REG2;
REG25[REG4 + 5] = REG3;
REG2 = REG17[REG16 + 0];
REG3 = REG17[REG16 + 1];
REG4 = REG3[REG2 + 2];
REG25 = 1;
REG26 = REG4 + REG25;
REG3[REG2 + 7] = REG26;
REG2 = REG17[REG16 + 0];
REG3 = REG17[REG16 + 1];
REG4 = REG3[REG2 + 2];
REG2 = 1;
REG3 = REG4 + REG2;
REG2 = REG19[REG18 + 0];
REG4 = REG19[REG18 + 1];
REG4[REG2 + 7] = REG3;
REG2 = REG17[REG16 + 0];
REG3 = REG17[REG16 + 1];
REG4 = REG3[REG2 + 2];
REG2 = 1;
REG3 = REG4 + REG2;
REG2 = REG21[REG20 + 0];
REG4 = REG21[REG20 + 1];
REG4[REG2 + 7] = REG3;
REG2 = REG17[REG16 + 0];
REG3 = REG17[REG16 + 1];
REG4 = REG3[REG2 + 2];
REG2 = 1;
REG3 = REG4 + REG2;
REG2 = REG23[REG22 + 0];
REG4 = REG23[REG22 + 1];
REG4[REG2 + 7] = REG3;
REG2 = REG17[REG16 + 0];
REG3 = REG17[REG16 + 1];
REG4 = REG3[REG2 + 7];
REG2 = 1;
REG3 = calloc;
REG25 = REG3(sp, stack, REG2, REG4);
REG26 = REG25[1]
REG25 = REG25[0]
REG2 = REG25;
REG3 = REG26;
REG4 = REG17[REG16 + 0];
REG25 = REG17[REG16 + 1];
REG25[REG4 + 6] = REG2;
REG25[REG4 + 7] = REG3;
REG2 = REG19[REG18 + 0];
REG3 = REG19[REG18 + 1];
REG4 = REG3[REG2 + 7];
REG2 = 1;
REG3 = calloc;
REG25 = REG3(sp, stack, REG2, REG4);
REG26 = REG25[1]
REG25 = REG25[0]
REG2 = REG25;
REG3 = REG26;
REG4 = REG19[REG18 + 0];
REG25 = REG19[REG18 + 1];
REG25[REG4 + 6] = REG2;
REG25[REG4 + 7] = REG3;
REG2 = REG21[REG20 + 0];
REG3 = REG21[REG20 + 1];
REG4 = REG3[REG2 + 7];
REG2 = 1;
REG3 = calloc;
REG25 = REG3(sp, stack, REG2, REG4);
REG26 = REG25[1]
REG25 = REG25[0]
REG2 = REG25;
REG3 = REG26;
REG4 = REG21[REG20 + 0];
REG25 = REG21[REG20 + 1];
REG25[REG4 + 6] = REG2;
REG25[REG4 + 7] = REG3;
REG2 = REG23[REG22 + 0];
REG3 = REG23[REG22 + 1];
REG4 = REG3[REG2 + 7];
REG2 = 1;
REG3 = calloc;
REG25 = REG3(sp, stack, REG2, REG4);
REG26 = REG25[1]
REG25 = REG25[0]
REG2 = REG25;
REG3 = REG26;
REG4 = REG23[REG22 + 0];
REG25 = REG23[REG22 + 1];
REG25[REG4 + 6] = REG2;
REG25[REG4 + 7] = REG3;
REG2 = REG17[REG16 + 0];
REG3 = REG17[REG16 + 1];
REG4 = REG3[REG2 + 1];
REG25 = 1;
REG26 = REG4 + REG25;
REG4 = REG3[REG2 + 2];
REG25 = 1;
REG27 = REG4 + REG25;
REG4 = REG26 * REG27;
REG25 = 8;
REG26 = REG4 + REG25;
REG4 = 8;
REG25 = REG26 / REG4;
REG25 = (REG25).toFixed();
REG4 = 1;
REG26 = REG25 + REG4;
REG3[REG2 + 3] = REG26;
REG2 = REG19[REG18 + 0];
REG3 = REG19[REG18 + 1];
REG4 = REG3[REG2 + 1];
REG25 = 1;
REG26 = REG4 + REG25;
REG4 = REG3[REG2 + 2];
REG25 = 1;
REG27 = REG4 + REG25;
REG4 = REG26 * REG27;
REG25 = 8;
REG26 = REG4 + REG25;
REG4 = 8;
REG25 = REG26 / REG4;
REG25 = (REG25).toFixed();
REG4 = 1;
REG26 = REG25 + REG4;
REG3[REG2 + 3] = REG26;
REG2 = REG21[REG20 + 0];
REG3 = REG21[REG20 + 1];
REG4 = REG3[REG2 + 1];
REG25 = 1;
REG26 = REG4 + REG25;
REG4 = REG3[REG2 + 2];
REG25 = 1;
REG27 = REG4 + REG25;
REG4 = REG26 * REG27;
REG25 = 8;
REG26 = REG4 + REG25;
REG4 = 8;
REG25 = REG26 / REG4;
REG25 = (REG25).toFixed();
REG4 = 1;
REG26 = REG25 + REG4;
REG3[REG2 + 3] = REG26;
REG2 = REG23[REG22 + 0];
REG3 = REG23[REG22 + 1];
REG4 = REG3[REG2 + 1];
REG25 = 1;
REG26 = REG4 + REG25;
REG4 = REG3[REG2 + 2];
REG25 = 1;
REG27 = REG4 + REG25;
REG4 = REG26 * REG27;
REG25 = 8;
REG26 = REG4 + REG25;
REG4 = 8;
REG25 = REG26 / REG4;
REG25 = (REG25).toFixed();
REG4 = 1;
REG26 = REG25 + REG4;
REG3[REG2 + 3] = REG26;
REG2 = REG17[REG16 + 0];
REG3 = REG17[REG16 + 1];
REG4 = REG3[REG2 + 3];
REG2 = 1;
REG3 = calloc;
REG25 = REG3(sp, stack, REG2, REG4);
REG26 = REG25[1]
REG25 = REG25[0]
REG2 = REG25;
REG3 = REG26;
REG4 = REG17[REG16 + 0];
REG25 = REG17[REG16 + 1];
REG25[REG4 + 10] = REG2;
REG25[REG4 + 11] = REG3;
REG2 = REG19[REG18 + 0];
REG3 = REG19[REG18 + 1];
REG4 = REG3[REG2 + 3];
REG2 = 1;
REG3 = calloc;
REG16 = REG3(sp, stack, REG2, REG4);
REG17 = REG16[1]
REG16 = REG16[0]
REG2 = REG16;
REG3 = REG17;
REG4 = REG19[REG18 + 0];
REG16 = REG19[REG18 + 1];
REG16[REG4 + 10] = REG2;
REG16[REG4 + 11] = REG3;
REG2 = REG21[REG20 + 0];
REG3 = REG21[REG20 + 1];
REG4 = REG3[REG2 + 3];
REG2 = 1;
REG3 = calloc;
REG16 = REG3(sp, stack, REG2, REG4);
REG17 = REG16[1]
REG16 = REG16[0]
REG2 = REG16;
REG3 = REG17;
REG4 = REG21[REG20 + 0];
REG16 = REG21[REG20 + 1];
REG16[REG4 + 10] = REG2;
REG16[REG4 + 11] = REG3;
REG2 = REG23[REG22 + 0];
REG3 = REG23[REG22 + 1];
REG4 = REG3[REG2 + 3];
REG2 = 1;
REG3 = calloc;
REG16 = REG3(sp, stack, REG2, REG4);
REG17 = REG16[1]
REG16 = REG16[0]
REG2 = REG16;
REG3 = REG17;
REG4 = REG23[REG22 + 0];
REG16 = REG23[REG22 + 1];
REG16[REG4 + 10] = REG2;
REG16[REG4 + 11] = REG3;
REG15 = REG24;
state = 4; break;
case 6: // basic block start for source line 3271
REG2 = REG26[REG25 + 1];
REG3 = 1;
REG4 = REG2 + REG3;
REG26[REG25 + 8] = REG4;
REG2 = REG19[REG18 + 0];
REG3 = REG19[REG18 + 1];
REG4 = REG3[REG2 + 1];
REG15 = 1;
REG25 = REG4 + REG15;
REG3[REG2 + 8] = REG25;
REG2 = REG21[REG20 + 0];
REG3 = REG21[REG20 + 1];
REG4 = REG3[REG2 + 1];
REG15 = 1;
REG25 = REG4 + REG15;
REG3[REG2 + 8] = REG25;
REG2 = REG23[REG22 + 0];
REG3 = REG23[REG22 + 1];
REG4 = REG3[REG2 + 1];
REG15 = 1;
REG25 = REG4 + REG15;
REG3[REG2 + 8] = REG25;
state = 5; break;
case 7: // basic block start for source line 3252
REG17 = REG8;
REG16 = REG7 + REG15;
REG2 = REG17[REG16 + 0];
REG3 = REG17[REG16 + 1];
REG3[REG2 + 0] = REG15;
REG19 = REG10;
REG18 = REG9 + REG15;
REG2 = REG19[REG18 + 0];
REG3 = REG19[REG18 + 1];
REG3[REG2 + 0] = REG15;
REG21 = REG12;
REG20 = REG11 + REG15;
REG2 = REG21[REG20 + 0];
REG3 = REG21[REG20 + 1];
REG3[REG2 + 0] = REG15;
REG23 = REG14;
REG22 = REG13 + REG15;
REG2 = REG23[REG22 + 0];
REG3 = REG23[REG22 + 1];
REG3[REG2 + 0] = REG15;
REG2 = REG1[REG0 + 21];
REG3 = REG1[REG0 + 22];
REG4 = REG2 + REG15;
REG2 = REG3[REG4 + 0];
REG3 = REG17[REG16 + 0];
REG4 = REG17[REG16 + 1];
REG4[REG3 + 1] = REG2;
REG2 = REG1[REG0 + 21];
REG3 = REG1[REG0 + 22];
REG4 = REG2 + REG15;
REG2 = REG3[REG4 + 0];
REG3 = REG19[REG18 + 0];
REG4 = REG19[REG18 + 1];
REG4[REG3 + 1] = REG2;
REG2 = REG1[REG0 + 21];
REG3 = REG1[REG0 + 22];
REG4 = REG2 + REG15;
REG2 = REG3[REG4 + 0];
REG3 = REG21[REG20 + 0];
REG4 = REG21[REG20 + 1];
REG4[REG3 + 1] = REG2;
REG2 = REG1[REG0 + 21];
REG3 = REG1[REG0 + 22];
REG4 = REG2 + REG15;
REG2 = REG3[REG4 + 0];
REG3 = REG23[REG22 + 0];
REG4 = REG23[REG22 + 1];
REG4[REG3 + 1] = REG2;
REG2 = REG1[REG0 + 21];
REG3 = REG1[REG0 + 22];
REG4 = 1;
REG24 = REG15 + REG4;
REG4 = REG2 + REG24;
REG2 = REG3[REG4 + 0];
REG3 = REG17[REG16 + 0];
REG4 = REG17[REG16 + 1];
REG4[REG3 + 2] = REG2;
REG2 = REG1[REG0 + 21];
REG3 = REG1[REG0 + 22];
REG4 = REG2 + REG24;
REG2 = REG3[REG4 + 0];
REG3 = REG19[REG18 + 0];
REG4 = REG19[REG18 + 1];
REG4[REG3 + 2] = REG2;
REG2 = REG1[REG0 + 21];
REG3 = REG1[REG0 + 22];
REG4 = REG2 + REG24;
REG2 = REG3[REG4 + 0];
REG3 = REG21[REG20 + 0];
REG4 = REG21[REG20 + 1];
REG4[REG3 + 2] = REG2;
REG2 = REG1[REG0 + 21];
REG3 = REG1[REG0 + 22];
REG4 = REG2 + REG24;
REG2 = REG3[REG4 + 0];
REG3 = REG23[REG22 + 0];
REG4 = REG23[REG22 + 1];
REG4[REG3 + 2] = REG2;
REG25 = REG17[REG16 + 0];
REG26 = REG17[REG16 + 1];
REG2 = REG26[REG25 + 1];
REG3 = REG26[REG25 + 2];
REG4 = (REG2 > REG3) ? 1 : 0;
state = REG4 ? 6 : 8; break;
case 8: // basic block start for source line 3276
REG2 = REG26[REG25 + 2];
REG3 = 1;
REG4 = REG2 + REG3;
REG26[REG25 + 8] = REG4;
REG2 = REG19[REG18 + 0];
REG3 = REG19[REG18 + 1];
REG4 = REG3[REG2 + 2];
REG15 = 1;
REG25 = REG4 + REG15;
REG3[REG2 + 8] = REG25;
REG2 = REG21[REG20 + 0];
REG3 = REG21[REG20 + 1];
REG4 = REG3[REG2 + 2];
REG15 = 1;
REG25 = REG4 + REG15;
REG3[REG2 + 8] = REG25;
REG2 = REG23[REG22 + 0];
REG3 = REG23[REG22 + 1];
REG4 = REG3[REG2 + 2];
REG15 = 1;
REG25 = REG4 + REG15;
REG3[REG2 + 8] = REG25;
state = 5; break;
case 9: // basic block start for source line 3324
REG27 = 0;
state = 10; break;
case 10: // basic block start for source line 3324
REG2 = REG1[REG0 + 5];
REG3 = (REG27 < REG2) ? 1 : 0;
state = REG3 ? 11 : 12; break;
case 11: // basic block start for source line 3325
REG2 = REG7 + REG27;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = static_0_56_make_matrix;
REG2(sp, stack, REG0, REG1, REG27, REG3, REG4);
REG2 = 1;
REG3 = REG27 + REG2;
REG27 = REG3;
state = 10; break;
case 12: // basic block start for source line 3328
REG28 = 0;
state = 13; break;
case 13: // basic block start for source line 2777
REG2 = REG1[REG0 + 5];
REG3 = (REG28 < REG2) ? 1 : 0;
state = REG3 ? 14 : 15; break;
case 14: // basic block start for source line 2778
REG2 = REG7 + REG28;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = REG13 + REG28;
REG15 = REG14[REG2 + 0];
REG16 = REG14[REG2 + 1];
REG2 = static_0_62_copy_m;
REG2(sp, stack, REG3, REG4, REG15, REG16);
REG2 = 1;
REG3 = REG28 + REG2;
REG28 = REG3;
state = 13; break;
case 15: // basic block start for source line 3328
<no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
REG2 = static_0_55_number_of_crossings_a;
REG31 = REG2(sp, stack, REG0, REG1, REG13, REG14);
REG1[REG0 + 24] = REG31;
REG2 = 0;
REG3 = (REG31 > REG2) ? 1 : 0;
REG29 = REG31;
REG30 = 0;
state = REG3 ? 16 : 165; break;
case 16: // basic block start for source line 3336
REG32 = 0;
REG33 = 0;
state = 17; break;
case 17: // basic block start for source line 3087
REG2 = REG1[REG0 + 5];
REG3 = -1;
REG34 = REG2 + REG3;
REG2 = (REG32 < REG34) ? 1 : 0;
state = REG2 ? 18 : 19; break;
case 18: // basic block start for source line 3088
REG2 = REG7 + REG32;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = 1;
REG15 = REG32 + REG2;
REG2 = REG7 + REG15;
REG16 = REG8[REG2 + 0];
REG17 = REG8[REG2 + 1];
REG2 = REG4[REG3 + 1];
REG18 = REG4[REG3 + 2];
REG19 = static_0_74_b_c;
REG20 = REG19(sp, stack, REG3, REG4, REG16, REG17, REG2, REG18);
REG2 = REG33 + REG20;
REG32 = REG15;
REG33 = REG2;
state = 17; break;
case 19: // basic block start for source line 3091
REG2 = REG7 + REG34;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = REG4[REG3 + 1];
REG15 = REG4[REG3 + 2];
REG18 = static_0_74_b_c;
REG19 = REG18(sp, stack, REG3, REG4, REG16, REG17, REG2, REG15);
REG36 = REG33 + REG19;
REG2 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>);
REG35 = 0;
state = 20; break;
case 20: // basic block start for source line 2777
REG37 = REG1[REG0 + 5];
REG2 = (REG35 < REG37) ? 1 : 0;
state = REG2 ? 21 : 22; break;
case 21: // basic block start for source line 2778
REG2 = REG7 + REG35;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = REG13 + REG35;
REG15 = REG14[REG2 + 0];
REG16 = REG14[REG2 + 1];
REG2 = static_0_62_copy_m;
REG2(sp, stack, REG3, REG4, REG15, REG16);
REG2 = 1;
REG3 = REG35 + REG2;
REG35 = REG3;
state = 20; break;
case 22: // basic block start for source line 3340
<no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
state = REG8 ? 27 : 23; break;
case 23: // basic block start for source line 3102
REG38 = 0;
state = 24; break;
case 24: // basic block start for source line 3096
REG38 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>);
REG42 = REG36 + REG38;
REG41 = 0;
state = 29; break;
case 25: // basic block start for source line 3111
REG2 = REG8[REG7 + 0];
REG3 = REG8[REG7 + 1];
REG4 = REG3[REG2 + 1];
REG15 = REG3[REG2 + 2];
REG18 = static_0_73_b_r;
REG19 = REG18(sp, stack, REG2, REG3, REG16, REG17, REG4, REG15);
REG2 = REG40 + REG19;
REG38 = REG2;
state = 24; break;
case 26: // basic block start for source line 3106
REG2 = 0;
REG3 = (REG39 > REG2) ? 1 : 0;
state = REG3 ? 28 : 25; break;
case 27: // basic block start for source line 3106
REG2 = -1;
REG3 = REG37 + REG2;
REG39 = REG3;
REG40 = 0;
state = 26; break;
case 28: // basic block start for source line 3107
REG2 = REG7 + REG39;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = -1;
REG15 = REG39 + REG2;
REG2 = REG7 + REG15;
REG16 = REG8[REG2 + 0];
REG17 = REG8[REG2 + 1];
REG2 = REG4[REG3 + 1];
REG18 = REG4[REG3 + 2];
REG19 = static_0_73_b_r;
REG20 = REG19(sp, stack, REG3, REG4, REG16, REG17, REG2, REG18);
REG2 = REG40 + REG20;
REG39 = REG15;
REG40 = REG2;
state = 26; break;
case 29: // basic block start for source line 2777
REG2 = REG1[REG0 + 5];
REG3 = (REG41 < REG2) ? 1 : 0;
state = REG3 ? 30 : 31; break;
case 30: // basic block start for source line 2778
REG2 = REG7 + REG41;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = REG13 + REG41;
REG15 = REG14[REG2 + 0];
REG16 = REG14[REG2 + 1];
REG2 = static_0_62_copy_m;
REG2(sp, stack, REG3, REG4, REG15, REG16);
REG2 = 1;
REG3 = REG41 + REG2;
REG41 = REG3;
state = 29; break;
case 31: // basic block start for source line 3342
<no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
REG43 = REG31;
REG44 = 0;
REG45 = 0;
REG46 = REG42;
REG47 = 0;
REG48 = 0;
state = 32; break;
case 32: // basic block start for source line 3348
REG49 = 0;
state = 43; break;
case 33: // basic block start for source line 3385
REG2 = static_0_64_equal_a;
REG3 = REG2(sp, stack, REG0, REG1, REG7, REG8, REG9, REG10);
REG43 = REG60;
REG44 = REG174;
REG45 = REG64;
REG46 = REG61;
REG47 = REG48;
REG48 = REG60;
REG65 = REG48;
REG66 = REG60;
state = REG3 ? 59 : 32; break;
case 34: // basic block start for source line 3346
REG2 = 1;
REG174 = REG44 + REG2;
REG2 = (REG174 < REG5) ? 1 : 0;
REG65 = REG48;
REG66 = REG60;
state = REG2 ? 33 : 59; break;
case 35: // basic block start for source line 3375
REG2 = (REG47 == REG48) ? 1 : 0;
state = REG2 ? 61 : 34; break;
case 36: // basic block start for source line 3368
REG64 = REG45 + REG61;
state = REG60 ? 35 : 58; break;
case 37: // basic block start for source line 3096
REG59 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>);
REG61 = REG54 + REG59;
REG2 = static_0_55_number_of_crossings_a;
REG62 = REG2(sp, stack, REG0, REG1, REG7, REG8);
REG2 = (REG62 < REG53) ? 1 : 0;
REG60 = REG53;
state = REG2 ? 54 : 36; break;
case 38: // basic block start for source line 3102
REG59 = 0;
state = 37; break;
case 39: // basic block start for source line 3359
state = REG8 ? 50 : 38; break;
case 40: // basic block start for source line 3091
REG2 = REG7 + REG52;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = REG4[REG3 + 1];
REG15 = REG4[REG3 + 2];
REG18 = static_0_74_b_c;
REG19 = REG18(sp, stack, REG3, REG4, REG16, REG17, REG2, REG15);
REG2 = REG51 + REG19;
REG3 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>);
REG54 = REG46 + REG2;
REG2 = static_0_55_number_of_crossings_a;
REG55 = REG2(sp, stack, REG0, REG1, REG7, REG8);
REG2 = (REG55 < REG43) ? 1 : 0;
REG53 = REG43;
state = REG2 ? 46 : 39; break;
case 41: // basic block start for source line 3087
REG2 = REG1[REG0 + 5];
REG3 = -1;
REG52 = REG2 + REG3;
REG2 = (REG50 < REG52) ? 1 : 0;
state = REG2 ? 45 : 40; break;
case 42: // basic block start for source line 3348
<no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
REG50 = 0;
REG51 = 0;
state = 41; break;
case 43: // basic block start for source line 2777
REG2 = REG1[REG0 + 5];
REG3 = (REG49 < REG2) ? 1 : 0;
state = REG3 ? 44 : 42; break;
case 44: // basic block start for source line 2778
REG2 = REG7 + REG49;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = REG9 + REG49;
REG15 = REG10[REG2 + 0];
REG16 = REG10[REG2 + 1];
REG2 = static_0_62_copy_m;
REG2(sp, stack, REG3, REG4, REG15, REG16);
REG2 = 1;
REG3 = REG49 + REG2;
REG49 = REG3;
state = 43; break;
case 45: // basic block start for source line 3088
REG2 = REG7 + REG50;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = 1;
REG15 = REG50 + REG2;
REG2 = REG7 + REG15;
REG16 = REG8[REG2 + 0];
REG17 = REG8[REG2 + 1];
REG2 = REG4[REG3 + 1];
REG18 = REG4[REG3 + 2];
REG19 = static_0_74_b_c;
REG20 = REG19(sp, stack, REG3, REG4, REG16, REG17, REG2, REG18);
REG2 = REG51 + REG20;
REG50 = REG15;
REG51 = REG2;
state = 41; break;
case 46: // basic block start for source line 3355
REG56 = 0;
state = 47; break;
case 47: // basic block start for source line 2777
REG2 = REG1[REG0 + 5];
REG3 = (REG56 < REG2) ? 1 : 0;
state = REG3 ? 48 : 49; break;
case 48: // basic block start for source line 2778
REG2 = REG7 + REG56;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = REG13 + REG56;
REG15 = REG14[REG2 + 0];
REG16 = REG14[REG2 + 1];
REG2 = static_0_62_copy_m;
REG2(sp, stack, REG3, REG4, REG15, REG16);
REG2 = 1;
REG3 = REG56 + REG2;
REG56 = REG3;
state = 47; break;
case 49: // basic block start for source line 3356
<no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
REG53 = REG55;
state = 39; break;
case 50: // basic block start for source line 3106
REG2 = REG1[REG0 + 5];
REG3 = -1;
REG4 = REG2 + REG3;
REG57 = REG4;
REG58 = 0;
state = 51; break;
case 51: // basic block start for source line 3106
REG2 = 0;
REG3 = (REG57 > REG2) ? 1 : 0;
state = REG3 ? 52 : 53; break;
case 52: // basic block start for source line 3107
REG2 = REG7 + REG57;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = -1;
REG15 = REG57 + REG2;
REG2 = REG7 + REG15;
REG16 = REG8[REG2 + 0];
REG17 = REG8[REG2 + 1];
REG2 = REG4[REG3 + 1];
REG18 = REG4[REG3 + 2];
REG19 = static_0_73_b_r;
REG20 = REG19(sp, stack, REG3, REG4, REG16, REG17, REG2, REG18);
REG2 = REG58 + REG20;
REG57 = REG15;
REG58 = REG2;
state = 51; break;
case 53: // basic block start for source line 3111
REG2 = REG8[REG7 + 0];
REG3 = REG8[REG7 + 1];
REG4 = REG3[REG2 + 1];
REG15 = REG3[REG2 + 2];
REG18 = static_0_73_b_r;
REG19 = REG18(sp, stack, REG2, REG3, REG16, REG17, REG4, REG15);
REG2 = REG58 + REG19;
REG59 = REG2;
state = 37; break;
case 54: // basic block start for source line 3364
REG63 = 0;
state = 55; break;
case 55: // basic block start for source line 2777
REG2 = REG1[REG0 + 5];
REG3 = (REG63 < REG2) ? 1 : 0;
state = REG3 ? 56 : 57; break;
case 56: // basic block start for source line 2778
REG2 = REG7 + REG63;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = REG13 + REG63;
REG15 = REG14[REG2 + 0];
REG16 = REG14[REG2 + 1];
REG2 = static_0_62_copy_m;
REG2(sp, stack, REG3, REG4, REG15, REG16);
REG2 = 1;
REG3 = REG63 + REG2;
REG63 = REG3;
state = 55; break;
case 57: // basic block start for source line 3365
<no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
REG60 = REG62;
state = 36; break;
case 58: // basic block start for source line 3371
REG65 = REG47;
REG66 = REG48;
state = 59; break;
case 59: // basic block start for source line 3388
REG2 = static_0_64_equal_a;
REG3 = REG2(sp, stack, REG0, REG1, REG7, REG8, REG13, REG14);
state = REG3 ? 65 : 62; break;
case 60: // basic block start for source line 3380
REG65 = REG48;
REG66 = REG60;
state = 59; break;
case 61: // basic block start for source line 3379
REG2 = (REG48 == REG60) ? 1 : 0;
state = REG2 ? 60 : 34; break;
case 62: // basic block start for source line 3389
REG67 = 0;
state = 63; break;
case 63: // basic block start for source line 2777
REG2 = REG1[REG0 + 5];
REG3 = (REG67 < REG2) ? 1 : 0;
state = REG3 ? 64 : 65; break;
case 64: // basic block start for source line 2778
REG2 = REG13 + REG67;
REG3 = REG14[REG2 + 0];
REG4 = REG14[REG2 + 1];
REG2 = REG7 + REG67;
REG15 = REG8[REG2 + 0];
REG16 = REG8[REG2 + 1];
REG2 = static_0_62_copy_m;
REG2(sp, stack, REG3, REG4, REG15, REG16);
REG2 = 1;
REG3 = REG67 + REG2;
REG67 = REG3;
state = 63; break;
case 65: // basic block start for source line 3392
REG2 = 0;
REG3 = (REG60 > REG2) ? 1 : 0;
REG68 = REG60;
REG69 = REG64;
state = REG3 ? 66 : 164; break;
case 66: // basic block start for source line 3394
REG2 = REG64 + REG61;
REG71 = 0;
REG73 = REG65;
REG74 = REG66;
REG70 = REG60;
REG75 = 0;
REG76 = 0;
REG72 = REG2;
state = 67; break;
case 67: // basic block start for source line 3398
REG77 = 0;
state = 106; break;
case 68: // basic block start for source line 3494
REG2 = static_0_64_equal_a;
REG3 = REG2(sp, stack, REG0, REG1, REG7, REG8, REG11, REG12);
REG71 = REG173;
REG73 = REG74;
REG74 = REG132;
REG70 = REG132;
REG75 = REG135;
REG76 = REG136;
REG72 = REG152;
state = REG3 ? 162 : 67; break;
case 69: // basic block start for source line 3397
REG2 = 1;
REG173 = REG71 + REG2;
REG2 = (REG173 < REG6) ? 1 : 0;
state = REG2 ? 68 : 162; break;
case 70: // basic block start for source line 3484
REG2 = (REG73 == REG74) ? 1 : 0;
state = REG2 ? 163 : 69; break;
case 71: // basic block start for source line 3476
REG2 = REG134 + REG133;
REG152 = REG2 + REG131;
state = REG132 ? 70 : 162; break;
case 72: // basic block start for source line 3460
REG135 = REG129;
REG136 = REG130;
state = 71; break;
case 73: // basic block start for source line 3457
REG134 = REG127 + REG133;
state = REG132 ? 145 : 72; break;
case 74: // basic block start for source line 3091
REG2 = REG7 + REG149;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = REG4[REG3 + 1];
REG15 = REG4[REG3 + 2];
REG18 = static_0_74_b_c;
REG19 = REG18(sp, stack, REG3, REG4, REG16, REG17, REG2, REG15);
REG2 = REG148 + REG19;
REG3 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>);
REG133 = REG144 + REG2;
REG2 = static_0_55_number_of_crossings_a;
REG150 = REG2(sp, stack, REG0, REG1, REG7, REG8);
REG2 = (REG150 < REG143) ? 1 : 0;
REG132 = REG143;
state = REG2 ? 158 : 73; break;
case 75: // basic block start for source line 3087
REG2 = REG1[REG0 + 5];
REG3 = -1;
REG149 = REG2 + REG3;
REG2 = (REG147 < REG149) ? 1 : 0;
state = REG2 ? 157 : 74; break;
case 76: // basic block start for source line 3450
REG147 = 0;
REG148 = 0;
state = 75; break;
case 77: // basic block start for source line 3096
REG142 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>);
REG144 = REG128 + REG142;
REG2 = static_0_55_number_of_crossings_a;
REG145 = REG2(sp, stack, REG0, REG1, REG7, REG8);
REG2 = (REG145 < REG125) ? 1 : 0;
REG143 = REG125;
state = REG2 ? 153 : 76; break;
case 78: // basic block start for source line 3102
REG142 = 0;
state = 77; break;
case 79: // basic block start for source line 3442
<no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
state = REG8 ? 149 : 78; break;
case 80: // basic block start for source line 2777
REG139 = REG1[REG0 + 5];
REG2 = (REG138 < REG139) ? 1 : 0;
state = REG2 ? 148 : 79; break;
case 81: // basic block start for source line 3442
REG138 = 0;
state = 80; break;
case 82: // basic block start for source line 3157
REG121 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>);
REG131 = REG86 + REG121;
REG125 = REG94;
REG126 = 0;
REG127 = REG72;
REG128 = REG95;
REG129 = REG96;
REG130 = REG97;
state = 81; break;
case 83: // basic block start for source line 3179
REG121 = REG113;
state = 82; break;
case 84: // basic block start for source line 3173
REG2 = REG124[REG123 + 9];
REG3 = REG124[REG123 + 10];
REG4 = REG124[REG123 + 1];
REG15 = static_0_75_sorted;
REG16 = REG15(sp, stack, REG2, REG3, REG4);
REG2 = 1;
REG3 = (REG16 == REG2) ? 1 : 0;
state = REG3 ? 135 : 83; break;
case 85: // basic block start for source line 3168
REG115 = REG8;
REG114 = REG7 + REG112;
REG123 = REG115[REG114 + 0];
REG124 = REG115[REG114 + 1];
REG2 = REG124[REG123 + 1];
REG3 = (REG122 <= REG2) ? 1 : 0;
state = REG3 ? 142 : 84; break;
case 86: // basic block start for source line 3168
REG122 = 1;
state = 85; break;
case 87: // basic block start for source line 3166
REG2 = 0;
REG3 = (REG112 > REG2) ? 1 : 0;
state = REG3 ? 86 : 136; break;
case 88: // basic block start for source line 3438
REG2 = REG1[REG0 + 5];
REG3 = -1;
REG4 = REG2 + REG3;
REG112 = REG4;
REG113 = 0;
state = 87; break;
case 89: // basic block start for source line 3422
REG96 = REG92;
REG97 = REG93;
state = 88; break;
case 90: // basic block start for source line 3421
state = REG94 ? 118 : 89; break;
case 91: // basic block start for source line 3096
REG109 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>);
REG95 = REG104 + REG109;
REG2 = static_0_55_number_of_crossings_a;
REG110 = REG2(sp, stack, REG0, REG1, REG7, REG8);
REG2 = (REG110 < REG103) ? 1 : 0;
REG94 = REG103;
state = REG2 ? 131 : 90; break;
case 92: // basic block start for source line 3102
REG109 = 0;
state = 91; break;
case 93: // basic block start for source line 3414
state = REG8 ? 127 : 92; break;
case 94: // basic block start for source line 3091
REG2 = REG7 + REG102;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = REG4[REG3 + 1];
REG15 = REG4[REG3 + 2];
REG18 = static_0_74_b_c;
REG19 = REG18(sp, stack, REG3, REG4, REG16, REG17, REG2, REG15);
REG104 = REG101 + REG19;
REG2 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>);
REG3 = static_0_55_number_of_crossings_a;
REG105 = REG3(sp, stack, REG0, REG1, REG7, REG8);
REG3 = (REG105 < REG90) ? 1 : 0;
REG103 = REG90;
state = REG3 ? 123 : 93; break;
case 95: // basic block start for source line 3087
REG2 = REG1[REG0 + 5];
REG3 = -1;
REG102 = REG2 + REG3;
REG2 = (REG100 < REG102) ? 1 : 0;
state = REG2 ? 122 : 94; break;
case 96: // basic block start for source line 3406
<no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
REG100 = 0;
REG101 = 0;
state = 95; break;
case 97: // basic block start for source line 2777
REG2 = REG1[REG0 + 5];
REG3 = (REG99 < REG2) ? 1 : 0;
state = REG3 ? 121 : 96; break;
case 98: // basic block start for source line 3405
REG99 = 0;
state = 97; break;
case 99: // basic block start for source line 3118
REG86 = <no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>);
REG90 = REG70;
REG91 = 0;
REG92 = REG75;
REG93 = REG76;
state = 98; break;
case 100: // basic block start for source line 3136
REG86 = REG79;
state = 99; break;
case 101: // basic block start for source line 3130
REG2 = REG89[REG88 + 9];
REG3 = REG89[REG88 + 10];
REG4 = REG89[REG88 + 2];
REG15 = static_0_75_sorted;
REG16 = REG15(sp, stack, REG2, REG3, REG4);
REG2 = 1;
REG3 = (REG16 == REG2) ? 1 : 0;
state = REG3 ? 108 : 100; break;
case 102: // basic block start for source line 3126
REG81 = REG8;
REG80 = REG7 + REG78;
REG88 = REG81[REG80 + 0];
REG89 = REG81[REG80 + 1];
REG2 = REG89[REG88 + 2];
REG3 = (REG87 <= REG2) ? 1 : 0;
state = REG3 ? 115 : 101; break;
case 103: // basic block start for source line 3126
REG87 = 1;
state = 102; break;
case 104: // basic block start for source line 3124
REG2 = REG1[REG0 + 5];
REG3 = -1;
REG4 = REG2 + REG3;
REG2 = (REG78 < REG4) ? 1 : 0;
state = REG2 ? 103 : 109; break;
case 105: // basic block start for source line 3400
<no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
REG78 = 0;
REG79 = 0;
state = 104; break;
case 106: // basic block start for source line 2777
REG2 = REG1[REG0 + 5];
REG3 = (REG77 < REG2) ? 1 : 0;
state = REG3 ? 107 : 105; break;
case 107: // basic block start for source line 2778
REG2 = REG7 + REG77;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = REG11 + REG77;
REG15 = REG12[REG2 + 0];
REG16 = REG12[REG2 + 1];
REG2 = static_0_62_copy_m;
REG2(sp, stack, REG3, REG4, REG15, REG16);
REG2 = 1;
REG3 = REG77 + REG2;
REG77 = REG3;
state = 106; break;
case 108: // basic block start for source line 3133
REG2 = REG81[REG80 + 0];
REG3 = REG81[REG80 + 1];
REG4 = 1;
REG15 = REG78 + REG4;
REG4 = REG7 + REG15;
REG16 = REG8[REG4 + 0];
REG17 = REG8[REG4 + 1];
REG4 = REG3[REG2 + 1];
REG18 = REG3[REG2 + 2];
REG19 = static_0_72_r_c;
REG20 = REG19(sp, stack, REG2, REG3, REG16, REG17, REG4, REG18);
REG2 = REG79 + REG20;
REG78 = REG15;
REG79 = REG2;
state = 104; break;
case 109: // basic block start for source line 3141
REG82 = 1;
state = 110; break;
case 110: // basic block start for source line 3141
REG2 = REG1[REG0 + 21];
REG3 = REG1[REG0 + 22];
REG4 = REG1[REG0 + 5];
REG15 = REG2 + REG4;
REG2 = REG3[REG15 + 0];
REG3 = (REG82 <= REG2) ? 1 : 0;
REG2 = -1;
REG15 = REG4 + REG2;
REG84 = REG8;
REG83 = REG7 + REG15;
state = REG3 ? 111 : 112; break;
case 111: // basic block start for source line 3142
REG2 = REG84[REG83 + 0];
REG3 = REG84[REG83 + 1];
REG4 = REG3[REG2 + 1];
REG15 = static_0_70_column_barycenter;
REG16 = REG15(sp, stack, REG2, REG3, REG82, REG4);
REG2 = REG1[REG0 + 5];
REG3 = -1;
REG4 = REG2 + REG3;
REG2 = REG7 + REG4;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = REG4[REG3 + 9];
REG15 = REG4[REG3 + 10];
REG3 = REG2 + REG82;
REG15[REG3 + 0] = REG16;
REG2 = 1;
REG3 = REG82 + REG2;
REG82 = REG3;
state = 110; break;
case 112: // basic block start for source line 3146
REG2 = REG84[REG83 + 0];
REG3 = REG84[REG83 + 1];
REG4 = REG3[REG2 + 9];
REG15 = REG3[REG2 + 10];
REG16 = REG3[REG2 + 2];
REG2 = static_0_75_sorted;
REG3 = REG2(sp, stack, REG4, REG15, REG16);
REG2 = 1;
REG4 = (REG3 == REG2) ? 1 : 0;
REG85 = REG79;
state = REG4 ? 113 : 114; break;
case 113: // basic block start for source line 3149
REG2 = REG1[REG0 + 5];
REG3 = -1;
REG4 = REG2 + REG3;
REG2 = REG7 + REG4;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = REG4[REG3 + 1];
REG15 = REG4[REG3 + 2];
REG18 = static_0_72_r_c;
REG19 = REG18(sp, stack, REG3, REG4, REG16, REG17, REG2, REG15);
REG2 = REG79 + REG19;
REG85 = REG2;
state = 114; break;
case 114: // basic block start for source line 3153
REG86 = REG85;
state = 99; break;
case 115: // basic block start for source line 3127
REG2 = REG89[REG88 + 1];
REG3 = static_0_70_column_barycenter;
REG4 = REG3(sp, stack, REG88, REG89, REG87, REG2);
REG2 = REG81[REG80 + 0];
REG3 = REG81[REG80 + 1];
REG15 = REG3[REG2 + 9];
REG16 = REG3[REG2 + 10];
REG2 = REG15 + REG87;
REG16[REG2 + 0] = REG4;
REG2 = 1;
REG3 = REG87 + REG2;
REG87 = REG3;
state = 102; break;
case 116: // basic block start for source line 3436
REG2 = static_0_64_equal_a;
REG3 = REG2(sp, stack, REG0, REG1, REG7, REG8, REG9, REG10);
REG90 = REG94;
REG91 = REG98;
REG92 = REG93;
REG93 = REG94;
REG96 = REG93;
REG97 = REG94;
state = REG3 ? 88 : 98; break;
case 117: // basic block start for source line 3404
REG2 = 1;
REG98 = REG91 + REG2;
REG2 = (REG98 < REG5) ? 1 : 0;
REG96 = REG93;
REG97 = REG94;
state = REG2 ? 116 : 88; break;
case 118: // basic block start for source line 3426
REG2 = (REG92 == REG93) ? 1 : 0;
state = REG2 ? 119 : 117; break;
case 119: // basic block start for source line 3430
REG2 = (REG93 == REG94) ? 1 : 0;
state = REG2 ? 120 : 117; break;
case 120: // basic block start for source line 3431
REG96 = REG93;
REG97 = REG94;
state = 88; break;
case 121: // basic block start for source line 2778
REG2 = REG7 + REG99;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = REG9 + REG99;
REG15 = REG10[REG2 + 0];
REG16 = REG10[REG2 + 1];
REG2 = static_0_62_copy_m;
REG2(sp, stack, REG3, REG4, REG15, REG16);
REG2 = 1;
REG3 = REG99 + REG2;
REG99 = REG3;
state = 97; break;
case 122: // basic block start for source line 3088
REG2 = REG7 + REG100;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = 1;
REG15 = REG100 + REG2;
REG2 = REG7 + REG15;
REG16 = REG8[REG2 + 0];
REG17 = REG8[REG2 + 1];
REG2 = REG4[REG3 + 1];
REG18 = REG4[REG3 + 2];
REG19 = static_0_74_b_c;
REG20 = REG19(sp, stack, REG3, REG4, REG16, REG17, REG2, REG18);
REG2 = REG101 + REG20;
REG100 = REG15;
REG101 = REG2;
state = 95; break;
case 123: // basic block start for source line 3410
REG106 = 0;
state = 124; break;
case 124: // basic block start for source line 2777
REG2 = REG1[REG0 + 5];
REG3 = (REG106 < REG2) ? 1 : 0;
state = REG3 ? 125 : 126; break;
case 125: // basic block start for source line 2778
REG2 = REG7 + REG106;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = REG13 + REG106;
REG15 = REG14[REG2 + 0];
REG16 = REG14[REG2 + 1];
REG2 = static_0_62_copy_m;
REG2(sp, stack, REG3, REG4, REG15, REG16);
REG2 = 1;
REG3 = REG106 + REG2;
REG106 = REG3;
state = 124; break;
case 126: // basic block start for source line 3411
<no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
REG103 = REG105;
state = 93; break;
case 127: // basic block start for source line 3106
REG2 = REG1[REG0 + 5];
REG3 = -1;
REG4 = REG2 + REG3;
REG107 = REG4;
REG108 = 0;
state = 128; break;
case 128: // basic block start for source line 3106
REG2 = 0;
REG3 = (REG107 > REG2) ? 1 : 0;
state = REG3 ? 129 : 130; break;
case 129: // basic block start for source line 3107
REG2 = REG7 + REG107;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = -1;
REG15 = REG107 + REG2;
REG2 = REG7 + REG15;
REG16 = REG8[REG2 + 0];
REG17 = REG8[REG2 + 1];
REG2 = REG4[REG3 + 1];
REG18 = REG4[REG3 + 2];
REG19 = static_0_73_b_r;
REG20 = REG19(sp, stack, REG3, REG4, REG16, REG17, REG2, REG18);
REG2 = REG108 + REG20;
REG107 = REG15;
REG108 = REG2;
state = 128; break;
case 130: // basic block start for source line 3111
REG2 = REG8[REG7 + 0];
REG3 = REG8[REG7 + 1];
REG4 = REG3[REG2 + 1];
REG15 = REG3[REG2 + 2];
REG18 = static_0_73_b_r;
REG19 = REG18(sp, stack, REG2, REG3, REG16, REG17, REG4, REG15);
REG2 = REG108 + REG19;
REG109 = REG2;
state = 91; break;
case 131: // basic block start for source line 3417
REG111 = 0;
state = 132; break;
case 132: // basic block start for source line 2777
REG2 = REG1[REG0 + 5];
REG3 = (REG111 < REG2) ? 1 : 0;
state = REG3 ? 133 : 134; break;
case 133: // basic block start for source line 2778
REG2 = REG7 + REG111;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = REG13 + REG111;
REG15 = REG14[REG2 + 0];
REG16 = REG14[REG2 + 1];
REG2 = static_0_62_copy_m;
REG2(sp, stack, REG3, REG4, REG15, REG16);
REG2 = 1;
REG3 = REG111 + REG2;
REG111 = REG3;
state = 132; break;
case 134: // basic block start for source line 3418
<no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
REG94 = REG110;
state = 90; break;
case 135: // basic block start for source line 3176
REG2 = REG115[REG114 + 0];
REG3 = REG115[REG114 + 1];
REG4 = -1;
REG15 = REG112 + REG4;
REG4 = REG7 + REG15;
REG16 = REG8[REG4 + 0];
REG17 = REG8[REG4 + 1];
REG4 = REG3[REG2 + 1];
REG18 = REG3[REG2 + 2];
REG19 = static_0_71_r_r;
REG20 = REG19(sp, stack, REG2, REG3, REG16, REG17, REG4, REG18);
REG2 = REG113 + REG20;
REG112 = REG15;
REG113 = REG2;
state = 87; break;
case 136: // basic block start for source line 3184
REG116 = 1;
state = 137; break;
case 137: // basic block start for source line 3184
REG117 = REG8[REG7 + 0];
REG118 = REG8[REG7 + 1];
REG119 = REG118[REG117 + 1];
REG2 = (REG116 <= REG119) ? 1 : 0;
state = REG2 ? 138 : 139; break;
case 138: // basic block start for source line 3185
REG2 = REG118[REG117 + 2];
REG3 = static_0_69_row_barycenter;
REG4 = REG3(sp, stack, REG117, REG118, REG116, REG2);
REG2 = REG8[REG7 + 0];
REG3 = REG8[REG7 + 1];
REG15 = REG3[REG2 + 9];
REG16 = REG3[REG2 + 10];
REG2 = REG15 + REG116;
REG16[REG2 + 0] = REG4;
REG2 = 1;
REG3 = REG116 + REG2;
REG116 = REG3;
state = 137; break;
case 139: // basic block start for source line 3189
REG2 = REG118[REG117 + 9];
REG3 = REG118[REG117 + 10];
REG4 = static_0_75_sorted;
REG15 = REG4(sp, stack, REG2, REG3, REG119);
REG2 = 1;
REG3 = (REG15 == REG2) ? 1 : 0;
REG120 = REG113;
state = REG3 ? 140 : 141; break;
case 140: // basic block start for source line 3192
REG2 = REG8[REG7 + 0];
REG3 = REG8[REG7 + 1];
REG4 = REG3[REG2 + 1];
REG15 = REG3[REG2 + 2];
REG18 = static_0_71_r_r;
REG19 = REG18(sp, stack, REG2, REG3, REG16, REG17, REG4, REG15);
REG2 = REG113 + REG19;
REG120 = REG2;
state = 141; break;
case 141: // basic block start for source line 3196
REG121 = REG120;
state = 82; break;
case 142: // basic block start for source line 3169
REG2 = REG124[REG123 + 2];
REG3 = static_0_69_row_barycenter;
REG4 = REG3(sp, stack, REG123, REG124, REG122, REG2);
REG2 = REG115[REG114 + 0];
REG3 = REG115[REG114 + 1];
REG15 = REG3[REG2 + 9];
REG16 = REG3[REG2 + 10];
REG2 = REG15 + REG122;
REG16[REG2 + 0] = REG4;
REG2 = 1;
REG3 = REG122 + REG2;
REG122 = REG3;
state = 85; break;
case 143: // basic block start for source line 3474
REG2 = static_0_64_equal_a;
REG3 = REG2(sp, stack, REG0, REG1, REG7, REG8, REG9, REG10);
REG125 = REG132;
REG126 = REG137;
REG127 = REG134;
REG128 = REG133;
REG129 = REG130;
REG130 = REG132;
REG135 = REG130;
REG136 = REG132;
state = REG3 ? 71 : 81; break;
case 144: // basic block start for source line 3441
REG2 = 1;
REG137 = REG126 + REG2;
REG2 = (REG137 < REG5) ? 1 : 0;
REG135 = REG130;
REG136 = REG132;
state = REG2 ? 143 : 71; break;
case 145: // basic block start for source line 3464
REG2 = (REG129 == REG130) ? 1 : 0;
state = REG2 ? 146 : 144; break;
case 146: // basic block start for source line 3468
REG2 = (REG130 == REG132) ? 1 : 0;
state = REG2 ? 147 : 144; break;
case 147: // basic block start for source line 3469
REG135 = REG130;
REG136 = REG132;
state = 71; break;
case 148: // basic block start for source line 2778
REG2 = REG7 + REG138;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = REG9 + REG138;
REG15 = REG10[REG2 + 0];
REG16 = REG10[REG2 + 1];
REG2 = static_0_62_copy_m;
REG2(sp, stack, REG3, REG4, REG15, REG16);
REG2 = 1;
REG3 = REG138 + REG2;
REG138 = REG3;
state = 80; break;
case 149: // basic block start for source line 3106
REG2 = -1;
REG3 = REG139 + REG2;
REG140 = REG3;
REG141 = 0;
state = 150; break;
case 150: // basic block start for source line 3106
REG2 = 0;
REG3 = (REG140 > REG2) ? 1 : 0;
state = REG3 ? 151 : 152; break;
case 151: // basic block start for source line 3107
REG2 = REG7 + REG140;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = -1;
REG15 = REG140 + REG2;
REG2 = REG7 + REG15;
REG16 = REG8[REG2 + 0];
REG17 = REG8[REG2 + 1];
REG2 = REG4[REG3 + 1];
REG18 = REG4[REG3 + 2];
REG19 = static_0_73_b_r;
REG20 = REG19(sp, stack, REG3, REG4, REG16, REG17, REG2, REG18);
REG2 = REG141 + REG20;
REG140 = REG15;
REG141 = REG2;
state = 150; break;
case 152: // basic block start for source line 3111
REG2 = REG8[REG7 + 0];
REG3 = REG8[REG7 + 1];
REG4 = REG3[REG2 + 1];
REG15 = REG3[REG2 + 2];
REG18 = static_0_73_b_r;
REG19 = REG18(sp, stack, REG2, REG3, REG16, REG17, REG4, REG15);
REG2 = REG141 + REG19;
REG142 = REG2;
state = 77; break;
case 153: // basic block start for source line 3446
REG146 = 0;
state = 154; break;
case 154: // basic block start for source line 2777
REG2 = REG1[REG0 + 5];
REG3 = (REG146 < REG2) ? 1 : 0;
state = REG3 ? 155 : 156; break;
case 155: // basic block start for source line 2778
REG2 = REG7 + REG146;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = REG13 + REG146;
REG15 = REG14[REG2 + 0];
REG16 = REG14[REG2 + 1];
REG2 = static_0_62_copy_m;
REG2(sp, stack, REG3, REG4, REG15, REG16);
REG2 = 1;
REG3 = REG146 + REG2;
REG146 = REG3;
state = 154; break;
case 156: // basic block start for source line 3447
<no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
REG143 = REG145;
state = 76; break;
case 157: // basic block start for source line 3088
REG2 = REG7 + REG147;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = 1;
REG15 = REG147 + REG2;
REG2 = REG7 + REG15;
REG16 = REG8[REG2 + 0];
REG17 = REG8[REG2 + 1];
REG2 = REG4[REG3 + 1];
REG18 = REG4[REG3 + 2];
REG19 = static_0_74_b_c;
REG20 = REG19(sp, stack, REG3, REG4, REG16, REG17, REG2, REG18);
REG2 = REG148 + REG20;
REG147 = REG15;
REG148 = REG2;
state = 75; break;
case 158: // basic block start for source line 3453
REG151 = 0;
state = 159; break;
case 159: // basic block start for source line 2777
REG2 = REG1[REG0 + 5];
REG3 = (REG151 < REG2) ? 1 : 0;
state = REG3 ? 160 : 161; break;
case 160: // basic block start for source line 2778
REG2 = REG7 + REG151;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = REG13 + REG151;
REG15 = REG14[REG2 + 0];
REG16 = REG14[REG2 + 1];
REG2 = static_0_62_copy_m;
REG2(sp, stack, REG3, REG4, REG15, REG16);
REG2 = 1;
REG3 = REG151 + REG2;
REG151 = REG3;
state = 159; break;
case 161: // basic block start for source line 3454
<no-name-for-reg>(sp, stack, <no-name-for-reg>, <no-name-for-reg>, <no-name-for-reg>);
REG132 = REG150;
state = 73; break;
case 162: // basic block start for source line 3397
REG68 = REG132;
REG69 = REG152;
state = 164; break;
case 163: // basic block start for source line 3488
REG2 = (REG74 == REG132) ? 1 : 0;
state = REG2 ? 162 : 69; break;
case 164: // basic block start for source line 3392
REG29 = REG68;
REG30 = REG69;
state = 165; break;
case 165: // basic block start for source line 3499
REG1[REG0 + 25] = REG29;
REG1[REG0 + 26] = REG30;
REG153 = 0;
state = 166; break;
case 166: // basic block start for source line 3504
REG154 = REG1[REG0 + 5];
REG2 = (REG153 < REG154) ? 1 : 0;
state = REG2 ? 167 : 168; break;
case 167: // basic block start for source line 3506
REG2 = REG13 + REG153;
REG3 = REG14[REG2 + 0];
REG4 = REG14[REG2 + 1];
REG2 = static_0_61_store_new_positions;
REG2(sp, stack, REG0, REG1, REG3, REG4, REG153);
REG2 = 2;
REG3 = REG153 + REG2;
REG153 = REG3;
state = 166; break;
case 168: // basic block start for source line 3509
REG2 = (REG153 == REG154) ? 1 : 0;
state = REG2 ? 169 : 170; break;
case 169: // basic block start for source line 3510
REG2 = -1;
REG3 = REG154 + REG2;
REG2 = REG13 + REG3;
REG4 = REG14[REG2 + 0];
REG5 = REG14[REG2 + 1];
REG2 = static_0_61_store_new_positions;
REG2(sp, stack, REG0, REG1, REG4, REG5, REG3);
state = 170; break;
case 170: // basic block start for source line 3513
REG155 = 0;
state = 171; break;
case 171: // basic block start for source line 3513
REG2 = REG1[REG0 + 5];
REG3 = (REG155 < REG2) ? 1 : 0;
state = REG3 ? 176 : 181; break;
case 172: // basic block start for source line 3513
REG2 = 1;
REG3 = REG155 + REG2;
REG155 = REG3;
state = 171; break;
case 173: // basic block start for source line 3532
REG169 = REG14;
REG168 = REG13 + REG155;
REG170 = REG169[REG168 + 0];
REG171 = REG169[REG168 + 1];
state = REG171 ? 180 : 172; break;
case 174: // basic block start for source line 3526
REG165 = REG12;
REG164 = REG11 + REG155;
REG166 = REG165[REG164 + 0];
REG167 = REG165[REG164 + 1];
state = REG167 ? 179 : 173; break;
case 175: // basic block start for source line 3520
REG161 = REG10;
REG160 = REG9 + REG155;
REG162 = REG161[REG160 + 0];
REG163 = REG161[REG160 + 1];
state = REG163 ? 178 : 174; break;
case 176: // basic block start for source line 3514
REG157 = REG8;
REG156 = REG7 + REG155;
REG158 = REG157[REG156 + 0];
REG159 = REG157[REG156 + 1];
state = REG159 ? 177 : 175; break;
case 177: // basic block start for source line 3515
REG2 = REG159[REG158 + 9];
REG3 = REG159[REG158 + 10];
REG4 = free;
REG4(sp, stack, REG2, REG3);
REG2 = REG157[REG156 + 0];
REG3 = REG157[REG156 + 1];
REG4 = REG3[REG2 + 4];
REG5 = REG3[REG2 + 5];
REG2 = free;
REG2(sp, stack, REG4, REG5);
REG2 = REG157[REG156 + 0];
REG3 = REG157[REG156 + 1];
REG4 = REG3[REG2 + 6];
REG5 = REG3[REG2 + 7];
REG2 = free;
REG2(sp, stack, REG4, REG5);
REG2 = REG157[REG156 + 0];
REG3 = REG157[REG156 + 1];
REG4 = REG3[REG2 + 10];
REG5 = REG3[REG2 + 11];
REG2 = free;
REG2(sp, stack, REG4, REG5);
state = 175; break;
case 178: // basic block start for source line 3521
REG2 = REG163[REG162 + 9];
REG3 = REG163[REG162 + 10];
REG4 = free;
REG4(sp, stack, REG2, REG3);
REG2 = REG161[REG160 + 0];
REG3 = REG161[REG160 + 1];
REG4 = REG3[REG2 + 4];
REG5 = REG3[REG2 + 5];
REG2 = free;
REG2(sp, stack, REG4, REG5);
REG2 = REG161[REG160 + 0];
REG3 = REG161[REG160 + 1];
REG4 = REG3[REG2 + 6];
REG5 = REG3[REG2 + 7];
REG2 = free;
REG2(sp, stack, REG4, REG5);
REG2 = REG161[REG160 + 0];
REG3 = REG161[REG160 + 1];
REG4 = REG3[REG2 + 10];
REG5 = REG3[REG2 + 11];
REG2 = free;
REG2(sp, stack, REG4, REG5);
state = 174; break;
case 179: // basic block start for source line 3527
REG2 = REG167[REG166 + 9];
REG3 = REG167[REG166 + 10];
REG4 = free;
REG4(sp, stack, REG2, REG3);
REG2 = REG165[REG164 + 0];
REG3 = REG165[REG164 + 1];
REG4 = REG3[REG2 + 4];
REG5 = REG3[REG2 + 5];
REG2 = free;
REG2(sp, stack, REG4, REG5);
REG2 = REG165[REG164 + 0];
REG3 = REG165[REG164 + 1];
REG4 = REG3[REG2 + 6];
REG5 = REG3[REG2 + 7];
REG2 = free;
REG2(sp, stack, REG4, REG5);
REG2 = REG165[REG164 + 0];
REG3 = REG165[REG164 + 1];
REG4 = REG3[REG2 + 10];
REG5 = REG3[REG2 + 11];
REG2 = free;
REG2(sp, stack, REG4, REG5);
state = 173; break;
case 180: // basic block start for source line 3533
REG2 = REG171[REG170 + 9];
REG3 = REG171[REG170 + 10];
REG4 = free;
REG4(sp, stack, REG2, REG3);
REG2 = REG169[REG168 + 0];
REG3 = REG169[REG168 + 1];
REG4 = REG3[REG2 + 4];
REG5 = REG3[REG2 + 5];
REG2 = free;
REG2(sp, stack, REG4, REG5);
REG2 = REG169[REG168 + 0];
REG3 = REG169[REG168 + 1];
REG4 = REG3[REG2 + 6];
REG5 = REG3[REG2 + 7];
REG2 = free;
REG2(sp, stack, REG4, REG5);
REG2 = REG169[REG168 + 0];
REG3 = REG169[REG168 + 1];
REG4 = REG3[REG2 + 10];
REG5 = REG3[REG2 + 11];
REG2 = free;
REG2(sp, stack, REG4, REG5);
state = 172; break;
case 181: // basic block start for source line 3543
REG172 = 0;
state = 182; break;
case 182: // basic block start for source line 3543
REG2 = REG1[REG0 + 5];
REG3 = (REG172 < REG2) ? 1 : 0;
state = REG3 ? 183 : 184; break;
case 183: // basic block start for source line 3544
REG2 = REG7 + REG172;
REG3 = REG8[REG2 + 0];
REG4 = REG8[REG2 + 1];
REG2 = free;
REG2(sp, stack, REG3, REG4);
REG2 = REG9 + REG172;
REG3 = REG10[REG2 + 0];
REG4 = REG10[REG2 + 1];
REG2 = free;
REG2(sp, stack, REG3, REG4);
REG2 = REG11 + REG172;
REG3 = REG12[REG2 + 0];
REG4 = REG12[REG2 + 1];
REG2 = free;
REG2(sp, stack, REG3, REG4);
REG2 = REG13 + REG172;
REG3 = REG14[REG2 + 0];
REG4 = REG14[REG2 + 1];
REG2 = free;
REG2(sp, stack, REG3, REG4);
REG2 = 1;
REG3 = REG172 + REG2;
REG172 = REG3;
state = 182; break;
case 184: // basic block start for source line 3550
REG0 = free;
REG0(sp, stack, REG7, REG8);
REG0 = free;
REG0(sp, stack, REG9, REG10);
REG0 = free;
REG0(sp, stack, REG11, REG12);
REG0 = free;
REG0(sp, stack, REG13, REG14);
return;
} } }

function static_0_82_barycenter(fp, stack, REG0, REG1, REG2) {
var sp;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = REG1[REG0 + 27];
REG5 = REG1[REG0 + 28];
state = REG5 ? 2 : 1; break;
case 1: // basic block start for source line 3824
REG4 = REG1[REG0 + 5];
REG5 = 1;
REG6 = REG4 + REG5;
REG4 = 1;
REG5 = calloc;
REG7 = REG5(sp, stack, REG4, REG6);
REG8 = REG7[1]
REG7 = REG7[0]
REG4 = REG7;
REG5 = REG8;
REG1[REG0 + 27] = REG4;
REG1[REG0 + 28] = REG5;
state = 2; break;
case 2: // basic block start for source line 3827
REG4 = REG1[REG0 + 5];
state = REG4 ? 6 : 3; break;
case 3: // basic block start for source line 3819
return;
case 4: // basic block start for source line 3840
REG4 = static_0_76_bc_n;
REG4(sp, stack, REG0, REG1, REG2, REG3);
state = 3; break;
case 5: // basic block start for source line 3836
REG4 = REG1[REG0 + 4];
REG5 = 2;
REG6 = (REG4 < REG5) ? 1 : 0;
state = REG6 ? 3 : 4; break;
case 6: // basic block start for source line 3832
REG4 = REG1[REG0 + 2];
REG5 = 2;
REG6 = (REG4 < REG5) ? 1 : 0;
state = REG6 ? 3 : 5; break;
} } }

function static_0_98_is_dummy(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG2 = REG1[REG0 + 5];
REG3 = 0;
REG4 = (REG2 != REG3) ? 1 : 0;
return REG4;
} } }

function static_0_99_upper_connectivity(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
state = REG1 ? 5 : 1; break;
case 1: // basic block start for source line 3910
REG2 = 0;
state = 2; break;
case 2: // basic block start for source line 3901
return REG2;
case 3: // basic block start for source line 3927
REG2 = REG5;
state = 2; break;
case 4: // basic block start for source line 3916
state = REG4 ? 7 : 3; break;
case 5: // basic block start for source line 3914
REG2 = REG1[REG0 + 27];
REG6 = REG1[REG0 + 28];
REG3 = REG2;
REG4 = REG6;
REG5 = 0;
state = 4; break;
case 6: // basic block start for source line 3924
REG0 = REG4[REG3 + 1];
REG1 = REG4[REG3 + 2];
REG3 = REG0;
REG4 = REG1;
REG5 = REG8;
state = 4; break;
case 7: // basic block start for source line 3918
REG6 = REG4[REG3 + 0];
REG7 = REG4[REG3 + 1];
REG0 = REG7[REG6 + 7];
REG8 = REG5;
state = REG0 ? 6 : 8; break;
case 8: // basic block start for source line 3920
REG0 = REG7[REG6 + 1];
REG1 = REG7[REG6 + 2];
REG2 = REG1[REG0 + 29];
REG1 = static_0_84_csn;
REG0 = 0;
REG6 = REG1[REG0 + 0];
REG0 = (REG2 == REG6) ? 1 : 0;
REG9 = REG5;
state = REG0 ? 9 : 10; break;
case 9: // basic block start for source line 3921
REG0 = 1;
REG1 = REG5 + REG0;
REG9 = REG1;
state = 10; break;
case 10: // basic block start for source line 3920
REG8 = REG9;
state = 6; break;
} } }

function static_0_100_lower_connectivity(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
state = REG1 ? 5 : 1; break;
case 1: // basic block start for source line 3940
REG2 = 0;
state = 2; break;
case 2: // basic block start for source line 3931
return REG2;
case 3: // basic block start for source line 3957
REG2 = REG5;
state = 2; break;
case 4: // basic block start for source line 3946
state = REG4 ? 7 : 3; break;
case 5: // basic block start for source line 3944
REG2 = REG1[REG0 + 25];
REG6 = REG1[REG0 + 26];
REG3 = REG2;
REG4 = REG6;
REG5 = 0;
state = 4; break;
case 6: // basic block start for source line 3954
REG0 = REG4[REG3 + 1];
REG1 = REG4[REG3 + 2];
REG3 = REG0;
REG4 = REG1;
REG5 = REG8;
state = 4; break;
case 7: // basic block start for source line 3948
REG6 = REG4[REG3 + 0];
REG7 = REG4[REG3 + 1];
REG0 = REG7[REG6 + 7];
REG8 = REG5;
state = REG0 ? 6 : 8; break;
case 8: // basic block start for source line 3950
REG0 = REG7[REG6 + 2];
REG1 = REG7[REG6 + 3];
REG2 = REG1[REG0 + 29];
REG1 = static_0_84_csn;
REG0 = 0;
REG6 = REG1[REG0 + 0];
REG0 = (REG2 == REG6) ? 1 : 0;
REG9 = REG5;
state = REG0 ? 9 : 10; break;
case 9: // basic block start for source line 3951
REG0 = 1;
REG1 = REG5 + REG0;
REG9 = REG1;
state = 10; break;
case 10: // basic block start for source line 3950
REG8 = REG9;
state = 6; break;
} } }

function static_0_101_do_floor(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
state = <no-name-for-reg> ? 1 : 3; break;
case 1: // basic block start for source line 3965
REG1 = REG2;
state = 2; break;
case 2: // basic block start for source line 3969
return REG1;
case 3: // basic block start for source line 3967
REG1 = REG2;
state = 2; break;
} } }

function static_0_102_upper_barycenter(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
state = REG1 ? 7 : 1; break;
case 1: // basic block start for source line 3981
REG2 = 0;
state = 2; break;
case 2: // basic block start for source line 3973
return REG2;
case 3: // basic block start for source line 4008
REG0 = static_0_101_do_floor;
REG1 = REG0(sp, stack, <no-name-for-reg>);
REG2 = REG0;
state = 2; break;
case 4: // basic block start for source line 3999
REG13 = REG0;
state = 3; break;
case 5: // basic block start for source line 3998
state = REG5 ? 13 : 4; break;
case 6: // basic block start for source line 3987
state = REG4 ? 9 : 5; break;
case 7: // basic block start for source line 3985
REG2 = REG1[REG0 + 27];
REG6 = REG1[REG0 + 28];
REG3 = REG2;
REG4 = REG6;
REG5 = 0;
state = 6; break;
case 8: // basic block start for source line 3995
REG2 = REG4[REG3 + 1];
REG6 = REG4[REG3 + 2];
REG3 = REG2;
REG4 = REG6;
REG5 = REG8;
state = 6; break;
case 9: // basic block start for source line 3989
REG6 = REG4[REG3 + 0];
REG7 = REG4[REG3 + 1];
REG2 = REG7[REG6 + 7];
REG8 = REG5;
state = REG2 ? 8 : 10; break;
case 10: // basic block start for source line 3991
REG9 = REG7[REG6 + 1];
REG10 = REG7[REG6 + 2];
REG2 = REG10[REG9 + 29];
REG7 = static_0_84_csn;
REG6 = 0;
REG8 = REG7[REG6 + 0];
REG6 = (REG2 == REG8) ? 1 : 0;
REG11 = REG5;
state = REG6 ? 11 : 12; break;
case 11: // basic block start for source line 3992
REG2 = REG10[REG9 + 17];
REG6 = REG5 + REG2;
REG11 = REG6;
state = 12; break;
case 12: // basic block start for source line 3991
REG8 = REG11;
state = 8; break;
case 13: // basic block start for source line 4001
REG2 = static_0_99_upper_connectivity;
REG3 = REG2(sp, stack, REG0, REG1);
state = REG3 ? 16 : 14; break;
case 14: // basic block start for source line 4002
REG12 = REG0;
state = 15; break;
case 15: // basic block start for source line 4001
REG13 = REG12;
state = 3; break;
case 16: // basic block start for source line 4004
REG2 = static_0_99_upper_connectivity;
REG3 = REG2(sp, stack, REG0, REG1);
REG2 = REG5 / REG3;
REG2 = (REG2).toFixed();
REG12 = REG2;
state = 15; break;
} } }

function static_0_103_lower_barycenter(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
state = REG1 ? 7 : 1; break;
case 1: // basic block start for source line 4022
REG2 = 0;
state = 2; break;
case 2: // basic block start for source line 4014
return REG2;
case 3: // basic block start for source line 4049
REG0 = static_0_101_do_floor;
REG1 = REG0(sp, stack, <no-name-for-reg>);
REG2 = REG0;
state = 2; break;
case 4: // basic block start for source line 4040
REG13 = REG0;
state = 3; break;
case 5: // basic block start for source line 4039
state = REG5 ? 13 : 4; break;
case 6: // basic block start for source line 4028
state = REG4 ? 9 : 5; break;
case 7: // basic block start for source line 4026
REG2 = REG1[REG0 + 25];
REG6 = REG1[REG0 + 26];
REG3 = REG2;
REG4 = REG6;
REG5 = 0;
state = 6; break;
case 8: // basic block start for source line 4036
REG2 = REG4[REG3 + 1];
REG6 = REG4[REG3 + 2];
REG3 = REG2;
REG4 = REG6;
REG5 = REG8;
state = 6; break;
case 9: // basic block start for source line 4030
REG6 = REG4[REG3 + 0];
REG7 = REG4[REG3 + 1];
REG2 = REG7[REG6 + 7];
REG8 = REG5;
state = REG2 ? 8 : 10; break;
case 10: // basic block start for source line 4032
REG9 = REG7[REG6 + 2];
REG10 = REG7[REG6 + 3];
REG2 = REG10[REG9 + 29];
REG7 = static_0_84_csn;
REG6 = 0;
REG8 = REG7[REG6 + 0];
REG6 = (REG2 == REG8) ? 1 : 0;
REG11 = REG5;
state = REG6 ? 11 : 12; break;
case 11: // basic block start for source line 4033
REG2 = REG10[REG9 + 17];
REG6 = REG5 + REG2;
REG11 = REG6;
state = 12; break;
case 12: // basic block start for source line 4032
REG8 = REG11;
state = 8; break;
case 13: // basic block start for source line 4042
REG2 = static_0_100_lower_connectivity;
REG3 = REG2(sp, stack, REG0, REG1);
state = REG3 ? 16 : 14; break;
case 14: // basic block start for source line 4043
REG12 = REG0;
state = 15; break;
case 15: // basic block start for source line 4042
REG13 = REG12;
state = 3; break;
case 16: // basic block start for source line 4045
REG2 = static_0_100_lower_connectivity;
REG3 = REG2(sp, stack, REG0, REG1);
REG2 = REG5 / REG3;
REG2 = (REG2).toFixed();
REG12 = REG2;
state = 15; break;
} } }

function static_0_104_sort(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG2 = -1;
REG3 = REG0 + REG2;
REG1 = REG3;
state = 1; break;
case 1: // basic block start for source line 4060
REG0 = 0;
REG2 = (REG1 > REG0) ? 1 : 0;
state = REG2 ? 4 : 10; break;
case 2: // basic block start for source line 4060
REG0 = -1;
REG2 = REG1 + REG0;
REG1 = REG2;
state = 1; break;
case 3: // basic block start for source line 4061
REG0 = (REG2 < REG1) ? 1 : 0;
state = REG0 ? 6 : 2; break;
case 4: // basic block start for source line 4061
REG2 = 0;
state = 3; break;
case 5: // basic block start for source line 4061
REG0 = 1;
REG3 = REG2 + REG0;
REG2 = REG3;
state = 3; break;
case 6: // basic block start for source line 4063
REG9 = static_0_97_nl;
REG0 = 0;
REG3 = REG9[REG0 + 0];
REG4 = REG9[REG0 + 1];
REG0 = REG2 * <no-name-for-reg>;
REG6 = REG4;
REG5 = REG3 + REG0;
REG7 = REG6[REG5 + 0];
REG8 = REG6[REG5 + 1];
state = REG8 ? 7 : 5; break;
case 7: // basic block start for source line 4063
REG0 = 1;
REG14 = REG2 + REG0;
REG9 = REG14 * <no-name-for-reg>;
REG11 = REG4;
REG10 = REG3 + REG9;
REG12 = REG11[REG10 + 0];
REG13 = REG11[REG10 + 1];
state = REG13 ? 8 : 5; break;
case 8: // basic block start for source line 4064
REG0 = REG8[REG7 + 15];
REG3 = REG13[REG12 + 15];
REG4 = (REG0 > REG3) ? 1 : 0;
state = REG4 ? 9 : 5; break;
case 9: // basic block start for source line 4066
memcpyimpl(sp, stack, REG5, REG6, REG10, REG11, 3);
REG3 = static_0_97_nl;
REG0 = 0;
REG4 = REG3[REG0 + 0];
REG5 = REG3[REG0 + 1];
REG0 = REG4 + REG9;
memcpyimpl(sp, stack, REG0, REG5, REG5, REG6, 3);
state = 5; break;
case 10: // basic block start for source line 4054
return;
} } }

function static_0_105_make_node_list_up(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG5 = static_0_85_cnodelist;
REG4 = 0;
REG6 = REG5[REG4 + 0];
REG7 = REG5[REG4 + 1];
REG1 = REG6;
REG2 = REG7;
REG3 = 0;
state = 1; break;
case 1: // basic block start for source line 4088
state = REG2 ? 3 : 8; break;
case 2: // basic block start for source line 4103
REG4 = REG2[REG1 + 1];
REG5 = REG2[REG1 + 2];
REG1 = REG4;
REG2 = REG5;
REG3 = REG6;
state = 1; break;
case 3: // basic block start for source line 4089
REG4 = REG2[REG1 + 0];
REG5 = REG2[REG1 + 1];
REG7 = REG5[REG4 + 18];
REG8 = (REG7 == REG0) ? 1 : 0;
REG6 = REG3;
state = REG8 ? 4 : 2; break;
case 4: // basic block start for source line 4092
REG8 = static_0_97_nl;
REG6 = 0;
REG9 = REG8[REG6 + 0];
REG10 = REG8[REG6 + 1];
REG7 = REG3 * <no-name-for-reg>;
REG6 = REG9 + REG7;
REG10[REG6 + 0] = REG4;
REG10[REG6 + 1] = REG5;
REG8 = static_0_97_nl;
REG6 = 0;
REG9 = REG8[REG6 + 0];
REG10 = REG8[REG6 + 1];
REG6 = REG9 + REG7;
REG8 = 0;
REG10[REG6 + 2] = REG8;
REG6 = static_0_98_is_dummy;
REG8 = REG6(sp, stack, REG4, REG5);
REG6 = 1;
REG9 = (REG8 == REG6) ? 1 : 0;
state = REG9 ? 5 : 7; break;
case 5: // basic block start for source line 4097
REG6 = REG5[REG4 + 15];
REG4 = 100000;
REG5 = REG4 - REG6;
REG6 = static_0_97_nl;
REG4 = 0;
REG8 = REG6[REG4 + 0];
REG9 = REG6[REG4 + 1];
REG4 = REG8 + REG7;
REG9[REG4 + 1] = REG5;
state = 6; break;
case 6: // basic block start for source line 4101
REG4 = 1;
REG5 = REG3 + REG4;
REG6 = REG5;
state = 2; break;
case 7: // basic block start for source line 4099
REG6 = static_0_100_lower_connectivity;
REG8 = REG6(sp, stack, REG4, REG5);
REG5 = static_0_97_nl;
REG4 = 0;
REG6 = REG5[REG4 + 0];
REG9 = REG5[REG4 + 1];
REG4 = REG6 + REG7;
REG9[REG4 + 1] = REG8;
state = 6; break;
case 8: // basic block start for source line 4106
REG2 = static_0_87_cnnodes_of_level;
REG1 = 0;
REG3 = REG2[REG1 + 0];
REG4 = REG2[REG1 + 1];
REG1 = REG3 + REG0;
REG2 = REG4[REG1 + 0];
REG1 = static_0_104_sort;
REG1(sp, stack, REG2);
return;
} } }

function static_0_106_make_node_list_down(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG5 = static_0_85_cnodelist;
REG4 = 0;
REG6 = REG5[REG4 + 0];
REG7 = REG5[REG4 + 1];
REG1 = REG6;
REG2 = REG7;
REG3 = 0;
state = 1; break;
case 1: // basic block start for source line 4121
state = REG2 ? 3 : 8; break;
case 2: // basic block start for source line 4135
REG4 = REG2[REG1 + 1];
REG5 = REG2[REG1 + 2];
REG1 = REG4;
REG2 = REG5;
REG3 = REG6;
state = 1; break;
case 3: // basic block start for source line 4122
REG4 = REG2[REG1 + 0];
REG5 = REG2[REG1 + 1];
REG7 = REG5[REG4 + 18];
REG8 = (REG7 == REG0) ? 1 : 0;
REG6 = REG3;
state = REG8 ? 4 : 2; break;
case 4: // basic block start for source line 4124
REG8 = static_0_97_nl;
REG6 = 0;
REG9 = REG8[REG6 + 0];
REG10 = REG8[REG6 + 1];
REG7 = REG3 * <no-name-for-reg>;
REG6 = REG9 + REG7;
REG10[REG6 + 0] = REG4;
REG10[REG6 + 1] = REG5;
REG8 = static_0_97_nl;
REG6 = 0;
REG9 = REG8[REG6 + 0];
REG10 = REG8[REG6 + 1];
REG6 = REG9 + REG7;
REG8 = 0;
REG10[REG6 + 2] = REG8;
REG6 = static_0_98_is_dummy;
REG8 = REG6(sp, stack, REG4, REG5);
REG6 = 1;
REG9 = (REG8 == REG6) ? 1 : 0;
state = REG9 ? 5 : 7; break;
case 5: // basic block start for source line 4129
REG6 = REG5[REG4 + 15];
REG4 = 100000;
REG5 = REG4 - REG6;
REG6 = static_0_97_nl;
REG4 = 0;
REG8 = REG6[REG4 + 0];
REG9 = REG6[REG4 + 1];
REG4 = REG8 + REG7;
REG9[REG4 + 1] = REG5;
state = 6; break;
case 6: // basic block start for source line 4133
REG4 = 1;
REG5 = REG3 + REG4;
REG6 = REG5;
state = 2; break;
case 7: // basic block start for source line 4131
REG6 = static_0_99_upper_connectivity;
REG8 = REG6(sp, stack, REG4, REG5);
REG5 = static_0_97_nl;
REG4 = 0;
REG6 = REG5[REG4 + 0];
REG9 = REG5[REG4 + 1];
REG4 = REG6 + REG7;
REG9[REG4 + 1] = REG8;
state = 6; break;
case 8: // basic block start for source line 4138
REG2 = static_0_87_cnnodes_of_level;
REG1 = 0;
REG3 = REG2[REG1 + 0];
REG4 = REG2[REG1 + 1];
REG1 = REG3 + REG0;
REG2 = REG4[REG1 + 0];
REG1 = static_0_104_sort;
REG1(sp, stack, REG2);
return;
} } }

function static_0_107_find_next(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG1 = 0;
REG2 = 0;
REG3 = 0;
state = 1; break;
case 1: // basic block start for source line 4150
REG4 = (REG2 < REG0) ? 1 : 0;
state = REG4 ? 3 : 6; break;
case 2: // basic block start for source line 4151
REG4 = 1;
REG5 = REG2 + REG4;
REG1 = REG7;
REG2 = REG5;
REG3 = REG8;
state = 1; break;
case 3: // basic block start for source line 4151
REG10 = static_0_97_nl;
REG9 = 0;
REG11 = REG10[REG9 + 0];
REG12 = REG10[REG9 + 1];
REG9 = REG2 * <no-name-for-reg>;
REG5 = REG12;
REG4 = REG11 + REG9;
REG6 = REG5[REG4 + 1];
REG9 = (REG6 >= REG3) ? 1 : 0;
REG7 = REG1;
REG8 = REG3;
state = REG9 ? 4 : 2; break;
case 4: // basic block start for source line 4152
REG9 = REG5[REG4 + 2];
REG7 = REG1;
REG8 = REG3;
state = REG9 ? 2 : 5; break;
case 5: // basic block start for source line 4153
REG7 = REG2;
REG8 = REG6;
state = 2; break;
case 6: // basic block start for source line 4144
return REG1;
} } }

function static_0_108_do_down(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var REG16;
var REG17;
var REG18;
var REG19;
var REG20;
var REG21;
var REG22;
var REG23;
var REG24;
var REG25;
var REG26;
var REG27;
var REG28;
var REG29;
var REG30;
var REG31;
var REG32;
var REG33;
var REG34;
var REG35;
var REG36;
var REG37;
var REG38;
var REG39;
var REG40;
var REG41;
var REG42;
var REG43;
var REG44;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG1 = 0;
state = 1; break;
case 1: // basic block start for source line 4170
REG4 = static_0_87_cnnodes_of_level;
REG3 = 0;
REG5 = REG4[REG3 + 0];
REG6 = REG4[REG3 + 1];
REG3 = REG5 + REG0;
REG2 = REG6[REG3 + 0];
REG3 = (REG1 < REG2) ? 1 : 0;
state = REG3 ? 3 : 44; break;
case 2: // basic block start for source line 4170
REG2 = 1;
REG3 = REG1 + REG2;
REG1 = REG3;
state = 1; break;
case 3: // basic block start for source line 4171
REG7 = static_0_107_find_next;
REG3 = REG7(sp, stack, REG2);
REG7 = static_0_97_nl;
REG2 = 0;
REG8 = REG7[REG2 + 0];
REG9 = REG7[REG2 + 1];
REG4 = REG3 * <no-name-for-reg>;
REG2 = REG8 + REG4;
REG5 = REG9[REG2 + 0];
REG6 = REG9[REG2 + 1];
state = REG6 ? 4 : 2; break;
case 4: // basic block start for source line 4175
REG2 = static_0_102_upper_barycenter;
REG8 = REG2(sp, stack, REG5, REG6);
REG7 = REG8;
state = REG8 ? 6 : 5; break;
case 5: // basic block start for source line 4178
REG5 = static_0_97_nl;
REG2 = 0;
REG6 = REG5[REG2 + 0];
REG8 = REG5[REG2 + 1];
REG2 = REG6 + REG4;
REG5 = REG8[REG2 + 0];
REG6 = REG8[REG2 + 1];
REG2 = REG6[REG5 + 17];
REG7 = REG2;
state = 6; break;
case 6: // basic block start for source line 4181
REG5 = static_0_97_nl;
REG2 = 0;
REG8 = REG5[REG2 + 0];
REG9 = REG5[REG2 + 1];
REG2 = REG8 + REG4;
REG10 = REG9[REG2 + 0];
REG11 = REG9[REG2 + 1];
REG2 = REG11[REG10 + 17];
REG5 = (REG7 < REG2) ? 1 : 0;
state = REG5 ? 7 : 31; break;
case 7: // basic block start for source line 4182
REG2 = REG11[REG10 + 17];
REG14 = REG2 - REG7;
REG12 = REG3;
REG13 = 0;
state = 8; break;
case 8: // basic block start for source line 4188
REG2 = 0;
REG5 = (REG12 > REG2) ? 1 : 0;
REG2 = REG12 * <no-name-for-reg>;
REG16 = REG9;
REG15 = REG8 + REG2;
state = REG5 ? 11 : 12; break;
case 9: // basic block start for source line 4196
REG2 = REG18 * <no-name-for-reg>;
REG5 = REG8 + REG2;
REG2 = REG9[REG5 + 2];
REG12 = REG18;
REG13 = REG17;
state = REG2 ? 13 : 8; break;
case 10: // basic block start for source line 4194
REG2 = -1;
REG18 = REG12 + REG2;
REG2 = 0;
REG5 = (REG18 >= REG2) ? 1 : 0;
state = REG5 ? 9 : 13; break;
case 11: // basic block start for source line 4189
REG2 = REG16[REG15 + 0];
REG5 = REG16[REG15 + 1];
REG6 = REG5[REG2 + 17];
REG2 = -1;
REG5 = REG12 + REG2;
REG2 = REG5 * <no-name-for-reg>;
REG5 = REG8 + REG2;
REG2 = REG9[REG5 + 0];
REG7 = REG9[REG5 + 1];
REG5 = REG7[REG2 + 17];
REG2 = REG6 - REG5;
REG6 = static_0_83_mindist;
REG5 = 0;
REG7 = REG6[REG5 + 0];
REG5 = REG2 - REG7;
REG2 = REG13 + REG5;
REG17 = REG2;
state = 10; break;
case 12: // basic block start for source line 4192
REG2 = REG16[REG15 + 0];
REG5 = REG16[REG15 + 1];
REG6 = REG5[REG2 + 17];
REG5 = static_0_83_mindist;
REG2 = 0;
REG7 = REG5[REG2 + 0];
REG2 = REG6 - REG7;
REG5 = REG13 + REG2;
REG17 = REG5;
state = 10; break;
case 13: // basic block start for source line 4198
REG2 = (REG17 < REG14) ? 1 : 0;
if (REG2) { REG5 = REG17; } else { REG5 = REG14; }
REG19 = REG3;
REG20 = REG5;
state = 14; break;
case 14: // basic block start for source line 4203
REG2 = 0;
REG5 = (REG20 > REG2) ? 1 : 0;
state = REG5 ? 19 : 25; break;
case 15: // basic block start for source line 4221
REG2 = -1;
REG5 = REG19 + REG2;
REG2 = REG20 - REG27;
REG19 = REG5;
REG20 = REG2;
state = 14; break;
case 16: // basic block start for source line 4217
REG2 = (REG28 <= REG3) ? 1 : 0;
state = REG2 ? 24 : 15; break;
case 17: // basic block start for source line 4217
REG28 = REG19;
state = 16; break;
case 18: // basic block start for source line 4208
REG27 = REG20;
state = 17; break;
case 19: // basic block start for source line 4204
state = REG19 ? 20 : 18; break;
case 20: // basic block start for source line 4210
REG5 = static_0_97_nl;
REG2 = 0;
REG6 = REG5[REG2 + 0];
REG7 = REG5[REG2 + 1];
REG2 = REG19 * <no-name-for-reg>;
REG5 = REG6 + REG2;
REG21 = REG7[REG5 + 0];
REG22 = REG7[REG5 + 1];
REG2 = REG22[REG21 + 17];
REG5 = -1;
REG8 = REG19 + REG5;
REG5 = REG8 * <no-name-for-reg>;
REG8 = REG6 + REG5;
REG23 = REG7[REG8 + 0];
REG24 = REG7[REG8 + 1];
REG5 = REG24[REG23 + 17];
REG6 = REG2 - REG5;
REG5 = static_0_83_mindist;
REG2 = 0;
REG25 = REG5[REG2 + 0];
REG2 = REG6 - REG25;
REG5 = (REG2 < REG20) ? 1 : 0;
state = REG5 ? 21 : 23; break;
case 21: // basic block start for source line 4211
REG2 = REG22[REG21 + 17];
REG5 = REG24[REG23 + 17];
REG6 = REG2 - REG5;
REG2 = REG6 - REG25;
REG26 = REG2;
state = 22; break;
case 22: // basic block start for source line 4210
REG27 = REG26;
state = 17; break;
case 23: // basic block start for source line 4213
REG26 = REG20;
state = 22; break;
case 24: // basic block start for source line 4218
REG5 = static_0_97_nl;
REG2 = 0;
REG6 = REG5[REG2 + 0];
REG7 = REG5[REG2 + 1];
REG2 = REG28 * <no-name-for-reg>;
REG5 = REG6 + REG2;
REG2 = REG7[REG5 + 0];
REG6 = REG7[REG5 + 1];
REG5 = REG6[REG2 + 17];
REG7 = REG5 - REG27;
REG6[REG2 + 17] = REG7;
REG2 = 1;
REG5 = REG28 + REG2;
REG28 = REG5;
state = 16; break;
case 25: // basic block start for source line 4268
REG3 = static_0_97_nl;
REG2 = 0;
REG5 = REG3[REG2 + 0];
REG6 = REG3[REG2 + 1];
REG2 = REG5 + REG4;
REG3 = 1;
REG6[REG2 + 2] = REG3;
state = 2; break;
case 26: // basic block start for source line 4246
REG2 = 0;
REG5 = (REG36 > REG2) ? 1 : 0;
state = REG5 ? 38 : 25; break;
case 27: // basic block start for source line 4241
REG2 = (REG33 < REG31) ? 1 : 0;
if (REG2) { REG5 = REG33; } else { REG5 = REG31; }
REG35 = REG3;
REG36 = REG5;
state = 26; break;
case 28: // basic block start for source line 4237
REG2 = 1;
REG32 = REG29 + REG2;
REG2 = (REG32 < REG34) ? 1 : 0;
state = REG2 ? 32 : 27; break;
case 29: // basic block start for source line 4232
REG2 = 1;
REG5 = REG29 + REG2;
REG2 = REG5 * <no-name-for-reg>;
REG5 = REG8 + REG2;
REG2 = REG9[REG5 + 0];
REG6 = REG9[REG5 + 1];
REG5 = REG6[REG2 + 17];
REG2 = REG29 * <no-name-for-reg>;
REG6 = REG8 + REG2;
REG2 = REG9[REG6 + 0];
REG7 = REG9[REG6 + 1];
REG6 = REG7[REG2 + 17];
REG2 = REG5 - REG6;
REG6 = static_0_83_mindist;
REG5 = 0;
REG7 = REG6[REG5 + 0];
REG5 = REG2 - REG7;
REG2 = REG30 + REG5;
REG33 = REG2;
state = 28; break;
case 30: // basic block start for source line 4231
REG5 = static_0_87_cnnodes_of_level;
REG2 = 0;
REG6 = REG5[REG2 + 0];
REG7 = REG5[REG2 + 1];
REG2 = REG6 + REG0;
REG34 = REG7[REG2 + 0];
REG2 = -1;
REG5 = REG34 + REG2;
REG2 = (REG29 < REG5) ? 1 : 0;
state = REG2 ? 29 : 33; break;
case 31: // basic block start for source line 4225
REG2 = REG11[REG10 + 17];
REG31 = REG7 - REG2;
REG29 = REG3;
REG30 = 0;
state = 30; break;
case 32: // basic block start for source line 4239
REG2 = REG32 * <no-name-for-reg>;
REG5 = REG8 + REG2;
REG2 = REG9[REG5 + 2];
REG29 = REG32;
REG30 = REG33;
state = REG2 ? 27 : 30; break;
case 33: // basic block start for source line 4235
REG2 = REG30 + REG31;
REG33 = REG2;
state = 28; break;
case 34: // basic block start for source line 4264
REG2 = 1;
REG5 = REG35 + REG2;
REG2 = REG36 - REG43;
REG35 = REG5;
REG36 = REG2;
state = 26; break;
case 35: // basic block start for source line 4260
REG2 = (REG44 <= REG35) ? 1 : 0;
state = REG2 ? 43 : 34; break;
case 36: // basic block start for source line 4260
REG44 = REG3;
state = 35; break;
case 37: // basic block start for source line 4251
REG43 = REG36;
state = 36; break;
case 38: // basic block start for source line 4247
REG5 = static_0_87_cnnodes_of_level;
REG2 = 0;
REG6 = REG5[REG2 + 0];
REG7 = REG5[REG2 + 1];
REG2 = REG6 + REG0;
REG5 = REG7[REG2 + 0];
REG2 = -1;
REG6 = REG5 + REG2;
REG2 = (REG35 == REG6) ? 1 : 0;
state = REG2 ? 37 : 39; break;
case 39: // basic block start for source line 4253
REG5 = static_0_97_nl;
REG2 = 0;
REG6 = REG5[REG2 + 0];
REG7 = REG5[REG2 + 1];
REG2 = 1;
REG5 = REG35 + REG2;
REG2 = REG5 * <no-name-for-reg>;
REG5 = REG6 + REG2;
REG37 = REG7[REG5 + 0];
REG38 = REG7[REG5 + 1];
REG2 = REG38[REG37 + 17];
REG5 = REG35 * <no-name-for-reg>;
REG8 = REG6 + REG5;
REG39 = REG7[REG8 + 0];
REG40 = REG7[REG8 + 1];
REG5 = REG40[REG39 + 17];
REG6 = REG2 - REG5;
REG5 = static_0_83_mindist;
REG2 = 0;
REG41 = REG5[REG2 + 0];
REG2 = REG6 - REG41;
REG5 = (REG2 < REG36) ? 1 : 0;
state = REG5 ? 40 : 42; break;
case 40: // basic block start for source line 4254
REG2 = REG38[REG37 + 17];
REG5 = REG40[REG39 + 17];
REG6 = REG2 - REG5;
REG2 = REG6 - REG41;
REG42 = REG2;
state = 41; break;
case 41: // basic block start for source line 4253
REG43 = REG42;
state = 36; break;
case 42: // basic block start for source line 4256
REG42 = REG36;
state = 41; break;
case 43: // basic block start for source line 4261
REG5 = static_0_97_nl;
REG2 = 0;
REG6 = REG5[REG2 + 0];
REG7 = REG5[REG2 + 1];
REG2 = REG44 * <no-name-for-reg>;
REG5 = REG6 + REG2;
REG2 = REG7[REG5 + 0];
REG6 = REG7[REG5 + 1];
REG5 = REG6[REG2 + 17];
REG7 = REG5 + REG43;
REG6[REG2 + 17] = REG7;
REG2 = 1;
REG5 = REG44 + REG2;
REG44 = REG5;
state = 35; break;
case 44: // basic block start for source line 4161
return;
} } }

function static_0_109_do_up(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var REG16;
var REG17;
var REG18;
var REG19;
var REG20;
var REG21;
var REG22;
var REG23;
var REG24;
var REG25;
var REG26;
var REG27;
var REG28;
var REG29;
var REG30;
var REG31;
var REG32;
var REG33;
var REG34;
var REG35;
var REG36;
var REG37;
var REG38;
var REG39;
var REG40;
var REG41;
var REG42;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG1 = 0;
state = 1; break;
case 1: // basic block start for source line 4284
REG4 = static_0_87_cnnodes_of_level;
REG3 = 0;
REG5 = REG4[REG3 + 0];
REG6 = REG4[REG3 + 1];
REG3 = REG5 + REG0;
REG2 = REG6[REG3 + 0];
REG3 = (REG1 < REG2) ? 1 : 0;
state = REG3 ? 3 : 44; break;
case 2: // basic block start for source line 4284
REG2 = 1;
REG3 = REG1 + REG2;
REG1 = REG3;
state = 1; break;
case 3: // basic block start for source line 4285
REG7 = static_0_107_find_next;
REG3 = REG7(sp, stack, REG2);
REG7 = static_0_97_nl;
REG2 = 0;
REG8 = REG7[REG2 + 0];
REG9 = REG7[REG2 + 1];
REG4 = REG3 * <no-name-for-reg>;
REG2 = REG8 + REG4;
REG5 = REG9[REG2 + 0];
REG6 = REG9[REG2 + 1];
state = REG6 ? 4 : 2; break;
case 4: // basic block start for source line 4288
REG2 = static_0_103_lower_barycenter;
REG8 = REG2(sp, stack, REG5, REG6);
REG7 = REG8;
state = REG8 ? 6 : 5; break;
case 5: // basic block start for source line 4291
REG5 = static_0_97_nl;
REG2 = 0;
REG6 = REG5[REG2 + 0];
REG8 = REG5[REG2 + 1];
REG2 = REG6 + REG4;
REG5 = REG8[REG2 + 0];
REG6 = REG8[REG2 + 1];
REG2 = REG6[REG5 + 17];
REG7 = REG2;
state = 6; break;
case 6: // basic block start for source line 4294
REG5 = static_0_97_nl;
REG2 = 0;
REG8 = REG5[REG2 + 0];
REG9 = REG5[REG2 + 1];
REG2 = REG8 + REG4;
REG10 = REG9[REG2 + 0];
REG11 = REG9[REG2 + 1];
REG2 = REG11[REG10 + 17];
REG5 = (REG7 < REG2) ? 1 : 0;
state = REG5 ? 7 : 31; break;
case 7: // basic block start for source line 4295
REG2 = REG11[REG10 + 17];
REG12 = REG2 - REG7;
REG13 = REG3;
REG14 = 0;
state = 8; break;
case 8: // basic block start for source line 4300
REG2 = 0;
REG5 = (REG13 > REG2) ? 1 : 0;
state = REG5 ? 11 : 12; break;
case 9: // basic block start for source line 4308
REG2 = REG16 * <no-name-for-reg>;
REG5 = REG8 + REG2;
REG2 = REG9[REG5 + 2];
REG13 = REG16;
REG14 = REG15;
state = REG2 ? 13 : 8; break;
case 10: // basic block start for source line 4306
REG2 = -1;
REG16 = REG13 + REG2;
REG2 = 0;
REG5 = (REG16 >= REG2) ? 1 : 0;
state = REG5 ? 9 : 13; break;
case 11: // basic block start for source line 4301
REG2 = REG13 * <no-name-for-reg>;
REG5 = REG8 + REG2;
REG2 = REG9[REG5 + 0];
REG6 = REG9[REG5 + 1];
REG5 = REG6[REG2 + 17];
REG2 = -1;
REG6 = REG13 + REG2;
REG2 = REG6 * <no-name-for-reg>;
REG6 = REG8 + REG2;
REG2 = REG9[REG6 + 0];
REG7 = REG9[REG6 + 1];
REG6 = REG7[REG2 + 17];
REG2 = REG5 - REG6;
REG6 = static_0_83_mindist;
REG5 = 0;
REG7 = REG6[REG5 + 0];
REG5 = REG2 - REG7;
REG2 = REG14 + REG5;
REG15 = REG2;
state = 10; break;
case 12: // basic block start for source line 4304
REG2 = REG9[REG8 + 0];
REG5 = REG9[REG8 + 1];
REG6 = REG5[REG2 + 17];
REG5 = static_0_83_mindist;
REG2 = 0;
REG7 = REG5[REG2 + 0];
REG2 = REG6 - REG7;
REG5 = REG14 + REG2;
REG15 = REG5;
state = 10; break;
case 13: // basic block start for source line 4310
REG2 = (REG15 < REG12) ? 1 : 0;
if (REG2) { REG5 = REG15; } else { REG5 = REG12; }
REG17 = REG3;
REG18 = REG5;
state = 14; break;
case 14: // basic block start for source line 4315
REG2 = 0;
REG5 = (REG18 > REG2) ? 1 : 0;
state = REG5 ? 19 : 25; break;
case 15: // basic block start for source line 4333
REG2 = -1;
REG5 = REG17 + REG2;
REG2 = REG18 - REG25;
REG17 = REG5;
REG18 = REG2;
state = 14; break;
case 16: // basic block start for source line 4329
REG2 = (REG26 <= REG3) ? 1 : 0;
state = REG2 ? 24 : 15; break;
case 17: // basic block start for source line 4329
REG26 = REG17;
state = 16; break;
case 18: // basic block start for source line 4320
REG25 = REG18;
state = 17; break;
case 19: // basic block start for source line 4316
state = REG17 ? 20 : 18; break;
case 20: // basic block start for source line 4322
REG5 = static_0_97_nl;
REG2 = 0;
REG6 = REG5[REG2 + 0];
REG7 = REG5[REG2 + 1];
REG2 = REG17 * <no-name-for-reg>;
REG5 = REG6 + REG2;
REG19 = REG7[REG5 + 0];
REG20 = REG7[REG5 + 1];
REG2 = REG20[REG19 + 17];
REG5 = -1;
REG8 = REG17 + REG5;
REG5 = REG8 * <no-name-for-reg>;
REG8 = REG6 + REG5;
REG21 = REG7[REG8 + 0];
REG22 = REG7[REG8 + 1];
REG5 = REG22[REG21 + 17];
REG6 = REG2 - REG5;
REG5 = static_0_83_mindist;
REG2 = 0;
REG23 = REG5[REG2 + 0];
REG2 = REG6 - REG23;
REG5 = (REG2 < REG18) ? 1 : 0;
state = REG5 ? 21 : 23; break;
case 21: // basic block start for source line 4323
REG2 = REG20[REG19 + 17];
REG5 = REG22[REG21 + 17];
REG6 = REG2 - REG5;
REG2 = REG6 - REG23;
REG24 = REG2;
state = 22; break;
case 22: // basic block start for source line 4322
REG25 = REG24;
state = 17; break;
case 23: // basic block start for source line 4325
REG24 = REG18;
state = 22; break;
case 24: // basic block start for source line 4330
REG5 = static_0_97_nl;
REG2 = 0;
REG6 = REG5[REG2 + 0];
REG7 = REG5[REG2 + 1];
REG2 = REG26 * <no-name-for-reg>;
REG5 = REG6 + REG2;
REG2 = REG7[REG5 + 0];
REG6 = REG7[REG5 + 1];
REG5 = REG6[REG2 + 17];
REG7 = REG5 - REG25;
REG6[REG2 + 17] = REG7;
REG2 = 1;
REG5 = REG26 + REG2;
REG26 = REG5;
state = 16; break;
case 25: // basic block start for source line 4380
REG3 = static_0_97_nl;
REG2 = 0;
REG5 = REG3[REG2 + 0];
REG6 = REG3[REG2 + 1];
REG2 = REG5 + REG4;
REG3 = 1;
REG6[REG2 + 2] = REG3;
state = 2; break;
case 26: // basic block start for source line 4358
REG2 = 0;
REG5 = (REG34 > REG2) ? 1 : 0;
state = REG5 ? 38 : 25; break;
case 27: // basic block start for source line 4353
REG2 = (REG31 < REG27) ? 1 : 0;
if (REG2) { REG5 = REG31; } else { REG5 = REG27; }
REG33 = REG3;
REG34 = REG5;
state = 26; break;
case 28: // basic block start for source line 4349
REG2 = 1;
REG30 = REG28 + REG2;
REG2 = (REG30 < REG32) ? 1 : 0;
state = REG2 ? 32 : 27; break;
case 29: // basic block start for source line 4344
REG2 = 1;
REG5 = REG28 + REG2;
REG2 = REG5 * <no-name-for-reg>;
REG5 = REG8 + REG2;
REG2 = REG9[REG5 + 0];
REG6 = REG9[REG5 + 1];
REG5 = REG6[REG2 + 17];
REG2 = REG28 * <no-name-for-reg>;
REG6 = REG8 + REG2;
REG2 = REG9[REG6 + 0];
REG7 = REG9[REG6 + 1];
REG6 = REG7[REG2 + 17];
REG2 = REG5 - REG6;
REG6 = static_0_83_mindist;
REG5 = 0;
REG7 = REG6[REG5 + 0];
REG5 = REG2 - REG7;
REG2 = REG29 + REG5;
REG31 = REG2;
state = 28; break;
case 30: // basic block start for source line 4343
REG5 = static_0_87_cnnodes_of_level;
REG2 = 0;
REG6 = REG5[REG2 + 0];
REG7 = REG5[REG2 + 1];
REG2 = REG6 + REG0;
REG32 = REG7[REG2 + 0];
REG2 = -1;
REG5 = REG32 + REG2;
REG2 = (REG28 < REG5) ? 1 : 0;
state = REG2 ? 29 : 33; break;
case 31: // basic block start for source line 4338
REG2 = REG11[REG10 + 17];
REG27 = REG7 - REG2;
REG28 = REG3;
REG29 = 0;
state = 30; break;
case 32: // basic block start for source line 4351
REG2 = REG30 * <no-name-for-reg>;
REG5 = REG8 + REG2;
REG2 = REG9[REG5 + 2];
REG28 = REG30;
REG29 = REG31;
state = REG2 ? 27 : 30; break;
case 33: // basic block start for source line 4347
REG2 = REG29 + REG27;
REG31 = REG2;
state = 28; break;
case 34: // basic block start for source line 4376
REG2 = 1;
REG5 = REG33 + REG2;
REG2 = REG34 - REG41;
REG33 = REG5;
REG34 = REG2;
state = 26; break;
case 35: // basic block start for source line 4372
REG2 = (REG42 <= REG33) ? 1 : 0;
state = REG2 ? 43 : 34; break;
case 36: // basic block start for source line 4372
REG42 = REG3;
state = 35; break;
case 37: // basic block start for source line 4363
REG41 = REG34;
state = 36; break;
case 38: // basic block start for source line 4359
REG5 = static_0_87_cnnodes_of_level;
REG2 = 0;
REG6 = REG5[REG2 + 0];
REG7 = REG5[REG2 + 1];
REG2 = REG6 + REG0;
REG5 = REG7[REG2 + 0];
REG2 = -1;
REG6 = REG5 + REG2;
REG2 = (REG33 == REG6) ? 1 : 0;
state = REG2 ? 37 : 39; break;
case 39: // basic block start for source line 4365
REG5 = static_0_97_nl;
REG2 = 0;
REG6 = REG5[REG2 + 0];
REG7 = REG5[REG2 + 1];
REG2 = 1;
REG5 = REG33 + REG2;
REG2 = REG5 * <no-name-for-reg>;
REG5 = REG6 + REG2;
REG35 = REG7[REG5 + 0];
REG36 = REG7[REG5 + 1];
REG2 = REG36[REG35 + 17];
REG5 = REG33 * <no-name-for-reg>;
REG8 = REG6 + REG5;
REG37 = REG7[REG8 + 0];
REG38 = REG7[REG8 + 1];
REG5 = REG38[REG37 + 17];
REG6 = REG2 - REG5;
REG5 = static_0_83_mindist;
REG2 = 0;
REG39 = REG5[REG2 + 0];
REG2 = REG6 - REG39;
REG5 = (REG2 < REG34) ? 1 : 0;
state = REG5 ? 40 : 42; break;
case 40: // basic block start for source line 4366
REG2 = REG36[REG35 + 17];
REG5 = REG38[REG37 + 17];
REG6 = REG2 - REG5;
REG2 = REG6 - REG39;
REG40 = REG2;
state = 41; break;
case 41: // basic block start for source line 4365
REG41 = REG40;
state = 36; break;
case 42: // basic block start for source line 4368
REG40 = REG34;
state = 41; break;
case 43: // basic block start for source line 4373
REG5 = static_0_97_nl;
REG2 = 0;
REG6 = REG5[REG2 + 0];
REG7 = REG5[REG2 + 1];
REG2 = REG42 * <no-name-for-reg>;
REG5 = REG6 + REG2;
REG2 = REG7[REG5 + 0];
REG6 = REG7[REG5 + 1];
REG5 = REG6[REG2 + 17];
REG7 = REG5 + REG41;
REG6[REG2 + 17] = REG7;
REG2 = 1;
REG5 = REG42 + REG2;
REG42 = REG5;
state = 35; break;
case 44: // basic block start for source line 4275
return;
} } }

function static_0_110_improve_positions2local(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = 1;
REG5 = static_0_83_mindist;
REG4 = 0;
REG5[REG4 + 0] = REG3;
REG2 = 0;
state = 1; break;
case 1: // basic block start for source line 4404
REG3 = 1;
REG4 = (REG2 < REG3) ? 1 : 0;
state = REG4 ? 6 : 13; break;
case 2: // basic block start for source line 4404
REG3 = 1;
REG4 = REG2 + REG3;
REG2 = REG4;
state = 1; break;
case 3: // basic block start for source line 4418
REG3 = 0;
REG4 = (REG6 >= REG3) ? 1 : 0;
state = REG4 ? 11 : 2; break;
case 4: // basic block start for source line 4418
REG3 = -1;
REG4 = REG5 + REG3;
REG6 = REG4;
state = 3; break;
case 5: // basic block start for source line 4407
REG5 = REG1[REG0 + 5];
REG4 = (REG3 < REG5) ? 1 : 0;
state = REG4 ? 8 : 4; break;
case 6: // basic block start for source line 4407
REG3 = 0;
state = 5; break;
case 7: // basic block start for source line 4407
REG4 = 1;
REG5 = REG3 + REG4;
REG3 = REG5;
state = 5; break;
case 8: // basic block start for source line 4408
REG6 = static_0_87_cnnodes_of_level;
REG5 = 0;
REG7 = REG6[REG5 + 0];
REG8 = REG6[REG5 + 1];
REG5 = REG7 + REG3;
REG4 = REG8[REG5 + 0];
state = REG4 ? 9 : 7; break;
case 9: // basic block start for source line 4409
REG5 = REG4 * <no-name-for-reg>;
REG4 = 1;
REG6 = calloc;
REG7 = REG6(sp, stack, REG4, REG5);
REG8 = REG7[1]
REG7 = REG7[0]
REG4 = REG7;
REG5 = REG8;
REG7 = static_0_97_nl;
REG6 = 0;
REG7[REG6 + 0] = REG4;
REG7[REG6 + 1] = REG5;
REG4 = static_0_106_make_node_list_down;
REG4(sp, stack, REG3);
REG4 = static_0_108_do_down;
REG4(sp, stack, REG3);
REG5 = static_0_97_nl;
REG4 = 0;
REG6 = REG5[REG4 + 0];
REG7 = REG5[REG4 + 1];
REG4 = free;
REG4(sp, stack, REG6, REG7);
REG4 = 0;
REG6 = static_0_97_nl;
REG5 = 0;
REG6[REG5 + 0] = REG4;
state = 7; break;
case 10: // basic block start for source line 4418
REG3 = -1;
REG4 = REG6 + REG3;
REG6 = REG4;
state = 3; break;
case 11: // basic block start for source line 4419
REG4 = static_0_87_cnnodes_of_level;
REG3 = 0;
REG5 = REG4[REG3 + 0];
REG8 = REG4[REG3 + 1];
REG3 = REG5 + REG6;
REG7 = REG8[REG3 + 0];
state = REG7 ? 12 : 10; break;
case 12: // basic block start for source line 4420
REG3 = REG7 * <no-name-for-reg>;
REG4 = 1;
REG5 = calloc;
REG7 = REG5(sp, stack, REG4, REG3);
REG8 = REG7[1]
REG7 = REG7[0]
REG3 = REG7;
REG4 = REG8;
REG7 = static_0_97_nl;
REG5 = 0;
REG7[REG5 + 0] = REG3;
REG7[REG5 + 1] = REG4;
REG3 = static_0_105_make_node_list_up;
REG3(sp, stack, REG6);
REG3 = static_0_109_do_up;
REG3(sp, stack, REG6);
REG4 = static_0_97_nl;
REG3 = 0;
REG5 = REG4[REG3 + 0];
REG7 = REG4[REG3 + 1];
REG3 = free;
REG3(sp, stack, REG5, REG7);
REG3 = 0;
REG5 = static_0_97_nl;
REG4 = 0;
REG5[REG4 + 0] = REG3;
state = 10; break;
case 13: // basic block start for source line 4431
REG2 = REG1[REG0 + 5];
REG3 = 2;
REG4 = (REG2 > REG3) ? 1 : 0;
state = REG4 ? 14 : 19; break;
case 14: // basic block start for source line 4433
REG8 = 2;
state = 15; break;
case 15: // basic block start for source line 4433
REG2 = 0;
REG3 = (REG8 >= REG2) ? 1 : 0;
state = REG3 ? 17 : 19; break;
case 16: // basic block start for source line 4433
REG2 = -1;
REG3 = REG8 + REG2;
REG8 = REG3;
state = 15; break;
case 17: // basic block start for source line 4434
REG3 = static_0_87_cnnodes_of_level;
REG2 = 0;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG2 = REG4 + REG8;
REG9 = REG5[REG2 + 0];
state = REG9 ? 18 : 16; break;
case 18: // basic block start for source line 4435
REG2 = REG9 * <no-name-for-reg>;
REG3 = 1;
REG4 = calloc;
REG5 = REG4(sp, stack, REG3, REG2);
REG6 = REG5[1]
REG5 = REG5[0]
REG2 = REG5;
REG3 = REG6;
REG5 = static_0_97_nl;
REG4 = 0;
REG5[REG4 + 0] = REG2;
REG5[REG4 + 1] = REG3;
REG2 = static_0_105_make_node_list_up;
REG2(sp, stack, REG8);
REG2 = static_0_109_do_up;
REG2(sp, stack, REG8);
REG3 = static_0_97_nl;
REG2 = 0;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG2 = free;
REG2(sp, stack, REG4, REG5);
REG2 = 0;
REG4 = static_0_97_nl;
REG3 = 0;
REG4[REG3 + 0] = REG2;
state = 16; break;
case 19: // basic block start for source line 4444
REG2 = REG1[REG0 + 5];
REG3 = -2;
REG4 = REG2 + REG3;
REG10 = REG4;
state = 20; break;
case 20: // basic block start for source line 4444
REG2 = REG1[REG0 + 5];
REG3 = (REG10 <= REG2) ? 1 : 0;
state = REG3 ? 22 : 25; break;
case 21: // basic block start for source line 4444
REG2 = 1;
REG3 = REG10 + REG2;
REG10 = REG3;
state = 20; break;
case 22: // basic block start for source line 4445
REG2 = 0;
REG3 = (REG10 >= REG2) ? 1 : 0;
state = REG3 ? 23 : 21; break;
case 23: // basic block start for source line 4446
REG3 = static_0_87_cnnodes_of_level;
REG2 = 0;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG2 = REG4 + REG10;
REG11 = REG5[REG2 + 0];
state = REG11 ? 24 : 21; break;
case 24: // basic block start for source line 4447
REG2 = REG11 * <no-name-for-reg>;
REG3 = 1;
REG4 = calloc;
REG5 = REG4(sp, stack, REG3, REG2);
REG6 = REG5[1]
REG5 = REG5[0]
REG2 = REG5;
REG3 = REG6;
REG5 = static_0_97_nl;
REG4 = 0;
REG5[REG4 + 0] = REG2;
REG5[REG4 + 1] = REG3;
REG2 = static_0_106_make_node_list_down;
REG2(sp, stack, REG10);
REG2 = static_0_108_do_down;
REG2(sp, stack, REG10);
REG3 = static_0_97_nl;
REG2 = 0;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG2 = free;
REG2(sp, stack, REG4, REG5);
REG2 = 0;
REG4 = static_0_97_nl;
REG3 = 0;
REG4[REG3 + 0] = REG2;
state = 21; break;
case 25: // basic block start for source line 4388
return;
} } }

function static_0_111_make_cnnodes_at_level(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = REG1[REG0 + 5];
REG5 = 1;
REG6 = REG4 + REG5;
REG4 = 1;
REG5 = calloc;
REG7 = REG5(sp, stack, REG4, REG6);
REG8 = REG7[1]
REG7 = REG7[0]
REG4 = REG7;
REG5 = REG8;
REG7 = static_0_87_cnnodes_of_level;
REG6 = 0;
REG7[REG6 + 0] = REG4;
REG7[REG6 + 1] = REG5;
REG5 = static_0_85_cnodelist;
REG4 = 0;
REG6 = REG5[REG4 + 0];
REG7 = REG5[REG4 + 1];
REG2 = REG6;
REG3 = REG7;
state = 1; break;
case 1: // basic block start for source line 4468
state = REG3 ? 2 : 3; break;
case 2: // basic block start for source line 4469
REG1 = static_0_87_cnnodes_of_level;
REG0 = 0;
REG4 = REG1[REG0 + 0];
REG5 = REG1[REG0 + 1];
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
REG6 = REG1[REG0 + 16];
REG0 = REG4 + REG6;
REG1 = REG5[REG0 + 0];
REG4 = 1;
REG6 = REG1 + REG4;
REG5[REG0 + 0] = REG6;
REG0 = REG3[REG2 + 1];
REG1 = REG3[REG2 + 2];
REG2 = REG0;
REG3 = REG1;
state = 1; break;
case 3: // basic block start for source line 4460
return;
} } }

function static_0_112_clear_cnnodes_at_level(fp, stack) {
var sp;
var REG0;
var REG1;
var REG2;
var REG3;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = static_0_87_cnnodes_of_level;
REG2 = 0;
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
state = REG1 ? 1 : 2; break;
case 1: // basic block start for source line 4482
REG2 = free;
REG2(sp, stack, REG0, REG1);
state = 2; break;
case 2: // basic block start for source line 4486
REG0 = 0;
REG2 = static_0_87_cnnodes_of_level;
REG1 = 0;
REG2[REG1 + 0] = REG0;
return;
} } }

function static_0_113_make_cnodelist(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = REG1[REG0 + 15];
REG5 = REG1[REG0 + 16];
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 1: // basic block start for source line 4499
state = REG3 ? 3 : 7; break;
case 2: // basic block start for source line 4515
REG0 = REG3[REG2 + 1];
REG1 = REG3[REG2 + 2];
REG2 = REG0;
REG3 = REG1;
state = 1; break;
case 3: // basic block start for source line 4502
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
REG4 = REG1[REG0 + 29];
REG1 = static_0_84_csn;
REG0 = 0;
REG5 = REG1[REG0 + 0];
REG0 = (REG4 == REG5) ? 1 : 0;
state = REG0 ? 4 : 2; break;
case 4: // basic block start for source line 4504
REG0 = 2;
REG1 = 1;
REG6 = calloc;
REG7 = REG6(sp, stack, REG1, REG0);
REG8 = REG7[1]
REG7 = REG7[0]
REG4 = REG7;
REG5 = REG8;
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
REG5[REG4 + 0] = REG0;
REG5[REG4 + 1] = REG1;
REG1 = static_0_85_cnodelist;
REG0 = 0;
REG6 = REG1[REG0 + 0];
REG7 = REG1[REG0 + 1];
state = REG7 ? 6 : 5; break;
case 5: // basic block start for source line 4507
REG1 = static_0_85_cnodelist;
REG0 = 0;
REG1[REG0 + 0] = REG4;
REG1[REG0 + 1] = REG5;
REG1 = static_0_86_cnodelisttail;
REG0 = 0;
REG1[REG0 + 0] = REG4;
REG1[REG0 + 1] = REG5;
state = 2; break;
case 6: // basic block start for source line 4510
REG1 = static_0_86_cnodelisttail;
REG0 = 0;
REG6 = REG1[REG0 + 0];
REG7 = REG1[REG0 + 1];
REG7[REG6 + 1] = REG4;
REG7[REG6 + 2] = REG5;
REG1 = static_0_86_cnodelisttail;
REG0 = 0;
REG1[REG0 + 0] = REG4;
REG1[REG0 + 1] = REG5;
state = 2; break;
case 7: // basic block start for source line 4492
return;
} } }

function static_0_114_clear_cnodelist(fp, stack) {
var sp;
var REG0;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = static_0_85_cnodelist;
REG2 = 0;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG0 = REG4;
REG1 = REG5;
state = 1; break;
case 1: // basic block start for source line 4529
state = REG1 ? 2 : 3; break;
case 2: // basic block start for source line 4530
REG2 = REG1[REG0 + 1];
REG3 = REG1[REG0 + 2];
REG4 = free;
REG4(sp, stack, REG0, REG1);
REG0 = REG2;
REG1 = REG3;
state = 1; break;
case 3: // basic block start for source line 4536
REG0 = 0;
REG2 = static_0_85_cnodelist;
REG1 = 0;
REG2[REG1 + 0] = REG0;
REG0 = 0;
REG2 = static_0_86_cnodelisttail;
REG1 = 0;
REG2[REG1 + 0] = REG0;
return;
} } }

function static_0_115_move0(fp, stack) {
var sp;
var REG0;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG6 = static_0_85_cnodelist;
REG5 = 0;
REG0 = REG6[REG5 + 0];
REG1 = REG6[REG5 + 1];
REG2 = REG0;
REG3 = REG1;
REG4 = 1000000;
state = 1; break;
case 1: // basic block start for source line 4553
state = REG3 ? 2 : 3; break;
case 2: // basic block start for source line 4554
REG5 = REG3[REG2 + 0];
REG6 = REG3[REG2 + 1];
REG7 = REG6[REG5 + 17];
REG5 = (REG7 < REG4) ? 1 : 0;
if (REG5) { REG6 = REG7; } else { REG6 = REG4; }
REG5 = REG3[REG2 + 1];
REG7 = REG3[REG2 + 2];
REG2 = REG5;
REG3 = REG7;
REG4 = REG6;
state = 1; break;
case 3: // basic block start for source line 4561
REG5 = REG0;
REG6 = REG1;
state = 4; break;
case 4: // basic block start for source line 4563
state = REG6 ? 5 : 6; break;
case 5: // basic block start for source line 4564
REG0 = REG6[REG5 + 0];
REG1 = REG6[REG5 + 1];
REG2 = REG1[REG0 + 17];
REG3 = REG2 - REG4;
REG1[REG0 + 17] = REG3;
REG0 = REG6[REG5 + 1];
REG1 = REG6[REG5 + 2];
REG5 = REG0;
REG6 = REG1;
state = 4; break;
case 6: // basic block start for source line 4543
return;
} } }

function static_0_116_make_cposnodes(fp, stack) {
var sp;
var REG0;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = 0;
REG5 = static_0_90_cwidestnnodes;
REG4 = 0;
REG5[REG4 + 0] = REG3;
REG3 = 0;
REG5 = static_0_91_cwpos;
REG4 = 0;
REG5[REG4 + 0] = REG3;
REG3 = 0;
REG5 = static_0_92_cposnodes;
REG4 = 0;
REG5[REG4 + 0] = REG3;
REG4 = static_0_85_cnodelist;
REG3 = 0;
REG5 = REG4[REG3 + 0];
REG6 = REG4[REG3 + 1];
REG0 = REG5;
REG1 = REG6;
REG2 = 0;
state = 1; break;
case 1: // basic block start for source line 4592
state = REG1 ? 2 : 3; break;
case 2: // basic block start for source line 4593
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG5 = REG4[REG3 + 17];
REG3 = (REG5 > REG2) ? 1 : 0;
if (REG3) { REG4 = REG5; } else { REG4 = REG2; }
REG3 = REG1[REG0 + 1];
REG5 = REG1[REG0 + 2];
REG0 = REG3;
REG1 = REG5;
REG2 = REG4;
state = 1; break;
case 3: // basic block start for source line 4600
REG1 = static_0_90_cwidestnnodes;
REG0 = 0;
REG1[REG0 + 0] = REG2;
REG0 = 1;
REG1 = REG2 + REG0;
REG0 = 1;
REG2 = calloc;
REG3 = REG2(sp, stack, REG0, REG1);
REG4 = REG3[1]
REG3 = REG3[0]
REG0 = REG3;
REG1 = REG4;
REG3 = static_0_91_cwpos;
REG2 = 0;
REG3[REG2 + 0] = REG0;
REG3[REG2 + 1] = REG1;
state = REG1 ? 5 : 4; break;
case 4: // basic block start for source line 4572
return;
case 5: // basic block start for source line 4610
REG1 = static_0_90_cwidestnnodes;
REG0 = 0;
REG2 = REG1[REG0 + 0];
REG0 = 1;
REG1 = REG2 + REG0;
REG0 = 1;
REG2 = calloc;
REG3 = REG2(sp, stack, REG0, REG1);
REG4 = REG3[1]
REG3 = REG3[0]
REG0 = REG3;
REG1 = REG4;
REG3 = static_0_92_cposnodes;
REG2 = 0;
REG3[REG2 + 0] = REG0;
REG3[REG2 + 1] = REG1;
state = REG1 ? 6 : 4; break;
case 6: // basic block start for source line 4617
REG1 = static_0_85_cnodelist;
REG0 = 0;
REG2 = REG1[REG0 + 0];
REG5 = REG1[REG0 + 1];
REG3 = REG2;
REG4 = REG5;
state = 7; break;
case 7: // basic block start for source line 4619
state = REG4 ? 11 : 13; break;
case 8: // basic block start for source line 4638
REG0 = REG4[REG3 + 1];
REG1 = REG4[REG3 + 2];
REG3 = REG0;
REG4 = REG1;
state = 7; break;
case 9: // basic block start for source line 4631
REG9[REG8 + 0] = REG6;
REG9[REG8 + 1] = REG7;
REG0 = 0;
REG7[REG6 + 1] = REG0;
state = 8; break;
case 10: // basic block start for source line 4628
REG0 = REG4[REG3 + 0];
REG1 = REG4[REG3 + 1];
REG7[REG6 + 0] = REG0;
REG7[REG6 + 1] = REG1;
REG1 = static_0_92_cposnodes;
REG0 = 0;
REG2 = REG1[REG0 + 0];
REG12 = REG1[REG0 + 1];
REG9 = REG12;
REG8 = REG2 + REG5;
REG10 = REG9[REG8 + 0];
REG11 = REG9[REG8 + 1];
state = REG11 ? 12 : 9; break;
case 11: // basic block start for source line 4620
REG0 = REG4[REG3 + 0];
REG1 = REG4[REG3 + 1];
REG5 = REG1[REG0 + 17];
REG0 = 2;
REG1 = 1;
REG2 = calloc;
REG8 = REG2(sp, stack, REG1, REG0);
REG9 = REG8[1]
REG8 = REG8[0]
REG6 = REG8;
REG7 = REG9;
state = REG7 ? 10 : 4; break;
case 12: // basic block start for source line 4634
REG7[REG6 + 1] = REG10;
REG7[REG6 + 2] = REG11;
REG1 = static_0_92_cposnodes;
REG0 = 0;
REG2 = REG1[REG0 + 0];
REG8 = REG1[REG0 + 1];
REG0 = REG2 + REG5;
REG8[REG0 + 0] = REG6;
REG8[REG0 + 1] = REG7;
state = 8; break;
case 13: // basic block start for source line 4642
REG12 = 0;
state = 14; break;
case 14: // basic block start for source line 4642
REG1 = static_0_90_cwidestnnodes;
REG0 = 0;
REG2 = REG1[REG0 + 0];
REG0 = 1;
REG1 = REG2 + REG0;
REG0 = (REG12 < REG1) ? 1 : 0;
state = REG0 ? 17 : 4; break;
case 15: // basic block start for source line 4655
REG1 = static_0_91_cwpos;
REG0 = 0;
REG2 = REG1[REG0 + 0];
REG3 = REG1[REG0 + 1];
REG0 = REG2 + REG12;
REG3[REG0 + 0] = REG15;
REG0 = 1;
REG1 = REG12 + REG0;
REG12 = REG1;
state = 14; break;
case 16: // basic block start for source line 4648
state = REG14 ? 18 : 15; break;
case 17: // basic block start for source line 4643
REG1 = static_0_92_cposnodes;
REG0 = 0;
REG2 = REG1[REG0 + 0];
REG3 = REG1[REG0 + 1];
REG0 = REG2 + REG12;
REG1 = REG3[REG0 + 0];
REG2 = REG3[REG0 + 1];
REG13 = REG1;
REG14 = REG2;
REG15 = 0;
state = 16; break;
case 18: // basic block start for source line 4649
REG0 = REG14[REG13 + 0];
REG1 = REG14[REG13 + 1];
REG2 = REG1[REG0 + 3];
REG0 = (REG2 > REG15) ? 1 : 0;
if (REG0) { REG1 = REG2; } else { REG1 = REG15; }
REG0 = REG14[REG13 + 1];
REG2 = REG14[REG13 + 2];
REG13 = REG0;
REG14 = REG2;
REG15 = REG1;
state = 16; break;
} } }

function static_0_117_clear_cposnodes(fp, stack) {
var sp;
var REG0;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = static_0_91_cwpos;
REG2 = 0;
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
state = REG1 ? 1 : 2; break;
case 1: // basic block start for source line 4670
REG2 = free;
REG2(sp, stack, REG0, REG1);
REG0 = 0;
REG2 = static_0_91_cwpos;
REG1 = 0;
REG2[REG1 + 0] = REG0;
state = 2; break;
case 2: // basic block start for source line 4674
REG2 = 0;
state = 3; break;
case 3: // basic block start for source line 4674
REG1 = static_0_90_cwidestnnodes;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG0 = 1;
REG1 = REG3 + REG0;
REG0 = (REG2 < REG1) ? 1 : 0;
state = REG0 ? 6 : 8; break;
case 4: // basic block start for source line 4684
REG1 = static_0_92_cposnodes;
REG0 = 0;
REG3 = REG1[REG0 + 0];
REG4 = REG1[REG0 + 1];
REG0 = REG3 + REG2;
REG1 = 0;
REG4[REG0 + 0] = REG1;
REG0 = 1;
REG1 = REG2 + REG0;
REG2 = REG1;
state = 3; break;
case 5: // basic block start for source line 4678
state = REG4 ? 7 : 4; break;
case 6: // basic block start for source line 4676
REG1 = static_0_92_cposnodes;
REG0 = 0;
REG5 = REG1[REG0 + 0];
REG6 = REG1[REG0 + 1];
REG0 = REG5 + REG2;
REG1 = REG6[REG0 + 0];
REG5 = REG6[REG0 + 1];
REG3 = REG1;
REG4 = REG5;
state = 5; break;
case 7: // basic block start for source line 4679
REG0 = REG4[REG3 + 1];
REG1 = REG4[REG3 + 2];
REG5 = free;
REG5(sp, stack, REG3, REG4);
REG3 = REG0;
REG4 = REG1;
state = 5; break;
case 8: // basic block start for source line 4687
REG1 = static_0_92_cposnodes;
REG0 = 0;
REG2 = REG1[REG0 + 0];
REG3 = REG1[REG0 + 1];
REG0 = free;
REG0(sp, stack, REG2, REG3);
REG0 = 0;
REG2 = static_0_92_cposnodes;
REG1 = 0;
REG2[REG1 + 0] = REG0;
return;
} } }

function static_0_118_make_clevelnodes(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG2 = REG1[REG0 + 5];
REG3 = 1;
REG4 = REG2 + REG3;
REG2 = 1;
REG3 = calloc;
REG5 = REG3(sp, stack, REG2, REG4);
REG6 = REG5[1]
REG5 = REG5[0]
REG2 = REG5;
REG3 = REG6;
REG5 = static_0_93_chpos;
REG4 = 0;
REG5[REG4 + 0] = REG2;
REG5[REG4 + 1] = REG3;
state = REG3 ? 2 : 1; break;
case 1: // basic block start for source line 4694
return;
case 2: // basic block start for source line 4707
REG2 = REG1[REG0 + 5];
REG3 = 1;
REG4 = REG2 + REG3;
REG2 = 1;
REG3 = calloc;
REG5 = REG3(sp, stack, REG2, REG4);
REG6 = REG5[1]
REG5 = REG5[0]
REG2 = REG5;
REG3 = REG6;
REG5 = static_0_94_clevelnodes;
REG4 = 0;
REG5[REG4 + 0] = REG2;
REG5[REG4 + 1] = REG3;
state = REG3 ? 3 : 1; break;
case 3: // basic block start for source line 4713
REG5 = static_0_85_cnodelist;
REG4 = 0;
REG6 = REG5[REG4 + 0];
REG7 = REG5[REG4 + 1];
REG2 = REG6;
REG3 = REG7;
state = 4; break;
case 4: // basic block start for source line 4715
state = REG3 ? 8 : 10; break;
case 5: // basic block start for source line 4734
REG4 = REG3[REG2 + 1];
REG5 = REG3[REG2 + 2];
REG2 = REG4;
REG3 = REG5;
state = 4; break;
case 6: // basic block start for source line 4727
REG8[REG7 + 0] = REG5;
REG8[REG7 + 1] = REG6;
REG4 = 0;
REG6[REG5 + 1] = REG4;
state = 5; break;
case 7: // basic block start for source line 4724
REG11 = REG3[REG2 + 0];
REG12 = REG3[REG2 + 1];
REG6[REG5 + 0] = REG11;
REG6[REG5 + 1] = REG12;
REG12 = static_0_94_clevelnodes;
REG11 = 0;
REG13 = REG12[REG11 + 0];
REG14 = REG12[REG11 + 1];
REG8 = REG14;
REG7 = REG13 + REG4;
REG9 = REG8[REG7 + 0];
REG10 = REG8[REG7 + 1];
state = REG10 ? 9 : 6; break;
case 8: // basic block start for source line 4716
REG7 = REG3[REG2 + 0];
REG8 = REG3[REG2 + 1];
REG4 = REG8[REG7 + 18];
REG7 = 2;
REG8 = 1;
REG9 = calloc;
REG10 = REG9(sp, stack, REG8, REG7);
REG11 = REG10[1]
REG10 = REG10[0]
REG5 = REG10;
REG6 = REG11;
state = REG6 ? 7 : 1; break;
case 9: // basic block start for source line 4730
REG6[REG5 + 1] = REG9;
REG6[REG5 + 2] = REG10;
REG8 = static_0_94_clevelnodes;
REG7 = 0;
REG9 = REG8[REG7 + 0];
REG10 = REG8[REG7 + 1];
REG7 = REG9 + REG4;
REG10[REG7 + 0] = REG5;
REG10[REG7 + 1] = REG6;
state = 5; break;
case 10: // basic block start for source line 4738
REG11 = 0;
state = 11; break;
case 11: // basic block start for source line 4738
REG2 = REG1[REG0 + 5];
REG3 = 1;
REG4 = REG2 + REG3;
REG2 = (REG11 < REG4) ? 1 : 0;
state = REG2 ? 14 : 1; break;
case 12: // basic block start for source line 4752
REG3 = static_0_93_chpos;
REG2 = 0;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG2 = REG4 + REG11;
REG5[REG2 + 0] = REG14;
REG2 = 1;
REG3 = REG11 + REG2;
REG11 = REG3;
state = 11; break;
case 13: // basic block start for source line 4745
state = REG13 ? 15 : 12; break;
case 14: // basic block start for source line 4740
REG3 = static_0_94_clevelnodes;
REG2 = 0;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG2 = REG4 + REG11;
REG3 = REG5[REG2 + 0];
REG4 = REG5[REG2 + 1];
REG12 = REG3;
REG13 = REG4;
REG14 = 0;
state = 13; break;
case 15: // basic block start for source line 4746
REG2 = REG13[REG12 + 0];
REG3 = REG13[REG12 + 1];
REG4 = REG3[REG2 + 4];
REG2 = (REG4 > REG14) ? 1 : 0;
if (REG2) { REG3 = REG4; } else { REG3 = REG14; }
REG2 = REG13[REG12 + 1];
REG4 = REG13[REG12 + 2];
REG12 = REG2;
REG13 = REG4;
REG14 = REG3;
state = 13; break;
} } }

function static_0_119_clear_clevelnodes(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG5 = static_0_93_chpos;
REG4 = 0;
REG2 = REG5[REG4 + 0];
REG3 = REG5[REG4 + 1];
state = REG3 ? 1 : 2; break;
case 1: // basic block start for source line 4766
REG4 = free;
REG4(sp, stack, REG2, REG3);
REG2 = 0;
REG4 = static_0_93_chpos;
REG3 = 0;
REG4[REG3 + 0] = REG2;
state = 2; break;
case 2: // basic block start for source line 4770
REG4 = 0;
state = 3; break;
case 3: // basic block start for source line 4770
REG2 = REG1[REG0 + 5];
REG3 = 1;
REG5 = REG2 + REG3;
REG2 = (REG4 < REG5) ? 1 : 0;
state = REG2 ? 6 : 8; break;
case 4: // basic block start for source line 4780
REG3 = static_0_94_clevelnodes;
REG2 = 0;
REG5 = REG3[REG2 + 0];
REG6 = REG3[REG2 + 1];
REG2 = REG5 + REG4;
REG3 = 0;
REG6[REG2 + 0] = REG3;
REG2 = 1;
REG3 = REG4 + REG2;
REG4 = REG3;
state = 3; break;
case 5: // basic block start for source line 4774
state = REG6 ? 7 : 4; break;
case 6: // basic block start for source line 4772
REG3 = static_0_94_clevelnodes;
REG2 = 0;
REG7 = REG3[REG2 + 0];
REG8 = REG3[REG2 + 1];
REG2 = REG7 + REG4;
REG3 = REG8[REG2 + 0];
REG7 = REG8[REG2 + 1];
REG5 = REG3;
REG6 = REG7;
state = 5; break;
case 7: // basic block start for source line 4775
REG2 = REG6[REG5 + 1];
REG3 = REG6[REG5 + 2];
REG7 = free;
REG7(sp, stack, REG5, REG6);
REG5 = REG2;
REG6 = REG3;
state = 5; break;
case 8: // basic block start for source line 4783
REG1 = static_0_94_clevelnodes;
REG0 = 0;
REG2 = REG1[REG0 + 0];
REG3 = REG1[REG0 + 1];
REG0 = free;
REG0(sp, stack, REG2, REG3);
REG0 = 0;
REG2 = static_0_94_clevelnodes;
REG1 = 0;
REG2[REG1 + 0] = REG0;
return;
} } }

function static_0_120_cfinalxy(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var REG16;
var REG17;
var REG18;
var REG19;
var REG20;
var REG21;
var REG22;
var REG23;
var REG24;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_116_make_cposnodes;
REG4(sp, stack);
REG4 = 0;
REG6 = static_0_88_cmaxx;
REG5 = 0;
REG6[REG5 + 0] = REG4;
REG2 = 0;
REG3 = 0;
state = 1; break;
case 1: // basic block start for source line 4806
REG5 = static_0_90_cwidestnnodes;
REG4 = 0;
REG6 = REG5[REG4 + 0];
REG4 = 1;
REG5 = REG6 + REG4;
REG4 = (REG3 < REG5) ? 1 : 0;
state = REG4 ? 8 : 14; break;
case 2: // basic block start for source line 4849
REG5 = static_0_95_xspacing;
REG4 = 0;
REG6 = REG5[REG4 + 0];
REG4 = REG2 + REG6;
REG6 = static_0_91_cwpos;
REG5 = 0;
REG7 = REG6[REG5 + 0];
REG8 = REG6[REG5 + 1];
REG5 = REG7 + REG3;
REG6 = REG8[REG5 + 0];
REG5 = REG4 + REG6;
REG4 = 1;
REG6 = REG3 + REG4;
REG2 = REG5;
REG3 = REG6;
state = 1; break;
case 3: // basic block start for source line 4841
state = REG11 ? 13 : 2; break;
case 4: // basic block start for source line 4838
REG5 = static_0_92_cposnodes;
REG4 = 0;
REG6 = REG5[REG4 + 0];
REG7 = REG5[REG4 + 1];
REG4 = REG6 + REG3;
REG5 = REG7[REG4 + 0];
REG6 = REG7[REG4 + 1];
REG10 = REG5;
REG11 = REG6;
state = 3; break;
case 5: // basic block start for source line 4826
state = REG7 ? 11 : 4; break;
case 6: // basic block start for source line 4821
REG8 = REG5 + REG2;
REG5 = static_0_92_cposnodes;
REG4 = 0;
REG9 = REG5[REG4 + 0];
REG10 = REG5[REG4 + 1];
REG4 = REG9 + REG3;
REG5 = REG10[REG4 + 0];
REG9 = REG10[REG4 + 1];
REG6 = REG5;
REG7 = REG9;
state = 5; break;
case 7: // basic block start for source line 4815
REG6 = static_0_95_xspacing;
REG4 = 0;
REG7 = REG6[REG4 + 0];
REG4 = 2;
REG6 = REG7 / REG4;
REG6 = (REG6).toFixed();
REG5 = REG6;
state = 6; break;
case 8: // basic block start for source line 4813
REG6 = static_0_91_cwpos;
REG5 = 0;
REG7 = REG6[REG5 + 0];
REG8 = REG6[REG5 + 1];
REG5 = REG7 + REG3;
REG4 = REG8[REG5 + 0];
state = REG4 ? 9 : 7; break;
case 9: // basic block start for source line 4817
REG6 = 2;
REG7 = REG4 / REG6;
REG7 = (REG7).toFixed();
REG5 = REG7;
state = 6; break;
case 10: // basic block start for source line 4834
REG4 = REG7[REG6 + 1];
REG5 = REG7[REG6 + 2];
REG6 = REG4;
REG7 = REG5;
state = 5; break;
case 11: // basic block start for source line 4828
REG4 = REG7[REG6 + 0];
REG5 = REG7[REG6 + 1];
REG10 = REG5[REG4 + 3];
REG11 = 2;
REG12 = REG10 / REG11;
REG12 = (REG12).toFixed();
REG10 = REG8 - REG12;
REG5[REG4 + 23] = REG10;
REG4 = REG7[REG6 + 0];
REG5 = REG7[REG6 + 1];
REG10 = REG5[REG4 + 23];
REG11 = REG5[REG4 + 3];
REG9 = REG10 + REG11;
REG5 = static_0_88_cmaxx;
REG4 = 0;
REG10 = REG5[REG4 + 0];
REG4 = (REG9 > REG10) ? 1 : 0;
state = REG4 ? 12 : 10; break;
case 12: // basic block start for source line 4831
REG5 = static_0_88_cmaxx;
REG4 = 0;
REG5[REG4 + 0] = REG9;
state = 10; break;
case 13: // basic block start for source line 4843
REG4 = REG11[REG10 + 0];
REG5 = REG11[REG10 + 1];
REG5[REG4 + 19] = REG2;
REG5 = static_0_91_cwpos;
REG4 = 0;
REG6 = REG5[REG4 + 0];
REG7 = REG5[REG4 + 1];
REG4 = REG6 + REG3;
REG5 = REG7[REG4 + 0];
REG4 = REG2 + REG5;
REG5 = REG11[REG10 + 0];
REG6 = REG11[REG10 + 1];
REG6[REG5 + 21] = REG4;
REG4 = REG11[REG10 + 1];
REG5 = REG11[REG10 + 2];
REG10 = REG4;
REG11 = REG5;
state = 3; break;
case 14: // basic block start for source line 4856
REG2 = static_0_117_clear_cposnodes;
REG2(sp, stack);
REG2 = static_0_118_make_clevelnodes;
REG2(sp, stack, REG0, REG1);
REG2 = 0;
REG4 = static_0_89_cmaxy;
REG3 = 0;
REG4[REG3 + 0] = REG2;
REG2 = REG1[REG0 + 5];
REG3 = 1;
REG4 = REG2 + REG3;
REG2 = 1;
REG3 = calloc;
REG5 = REG3(sp, stack, REG2, REG4);
REG6 = REG5[1]
REG5 = REG5[0]
REG2 = REG5;
REG3 = REG6;
REG1[REG0 + 28] = REG2;
REG1[REG0 + 29] = REG3;
REG12 = 0;
REG13 = 0;
state = 15; break;
case 15: // basic block start for source line 4868
REG2 = REG1[REG0 + 5];
REG3 = 1;
REG4 = REG2 + REG3;
REG2 = (REG13 < REG4) ? 1 : 0;
state = REG2 ? 20 : 28; break;
case 16: // basic block start for source line 4918
REG2 = REG1[REG0 + 28];
REG3 = REG1[REG0 + 29];
REG4 = REG2 + REG13;
REG3[REG4 + 0] = REG19;
REG3 = static_0_96_yspacing;
REG2 = 0;
REG4 = REG3[REG2 + 0];
REG2 = REG12 + REG4;
REG3 = REG1[REG0 + 27];
REG4 = REG1[REG0 + 28];
REG5 = REG3 + REG13;
REG3 = REG4[REG5 + 0];
REG4 = 16;
REG5 = REG3 / REG4;
REG5 = (REG5).toFixed();
REG3 = REG2 + REG5;
REG4 = static_0_93_chpos;
REG2 = 0;
REG5 = REG4[REG2 + 0];
REG6 = REG4[REG2 + 1];
REG2 = REG5 + REG13;
REG4 = REG6[REG2 + 0];
REG2 = REG3 + REG4;
REG3 = 1;
REG4 = REG13 + REG3;
REG12 = REG2;
REG13 = REG4;
state = 15; break;
case 17: // basic block start for source line 4890
state = REG18 ? 24 : 16; break;
case 18: // basic block start for source line 4883
REG16 = REG15 + REG12;
REG3 = static_0_94_clevelnodes;
REG2 = 0;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG2 = REG4 + REG13;
REG3 = REG5[REG2 + 0];
REG4 = REG5[REG2 + 1];
REG17 = REG3;
REG18 = REG4;
REG19 = 0;
state = 17; break;
case 19: // basic block start for source line 4877
REG3 = static_0_96_yspacing;
REG2 = 0;
REG4 = REG3[REG2 + 0];
REG2 = 2;
REG3 = REG4 / REG2;
REG3 = (REG3).toFixed();
REG15 = REG3;
state = 18; break;
case 20: // basic block start for source line 4875
REG3 = static_0_93_chpos;
REG2 = 0;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG2 = REG4 + REG13;
REG14 = REG5[REG2 + 0];
state = REG14 ? 21 : 19; break;
case 21: // basic block start for source line 4879
REG2 = 2;
REG3 = REG14 / REG2;
REG3 = (REG3).toFixed();
REG15 = REG3;
state = 18; break;
case 22: // basic block start for source line 4913
REG2 = REG18[REG17 + 0];
REG3 = REG18[REG17 + 1];
REG4 = REG3[REG2 + 12];
REG2 = REG19 + REG4;
REG3 = REG18[REG17 + 1];
REG4 = REG18[REG17 + 2];
REG17 = REG3;
REG18 = REG4;
REG19 = REG2;
state = 17; break;
case 23: // basic block start for source line 4904
REG21 = REG18[REG17 + 0];
REG22 = REG18[REG17 + 1];
REG2 = REG22[REG21 + 5];
state = REG2 ? 26 : 22; break;
case 24: // basic block start for source line 4892
REG2 = REG18[REG17 + 0];
REG3 = REG18[REG17 + 1];
REG3[REG2 + 20] = REG12;
REG3 = static_0_93_chpos;
REG2 = 0;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG2 = REG4 + REG13;
REG3 = REG5[REG2 + 0];
REG2 = REG12 + REG3;
REG3 = REG18[REG17 + 0];
REG4 = REG18[REG17 + 1];
REG4[REG3 + 22] = REG2;
REG2 = REG18[REG17 + 0];
REG3 = REG18[REG17 + 1];
REG4 = REG3[REG2 + 4];
REG5 = 2;
REG6 = REG4 / REG5;
REG6 = (REG6).toFixed();
REG4 = REG16 - REG6;
REG3[REG2 + 24] = REG4;
REG2 = REG18[REG17 + 0];
REG3 = REG18[REG17 + 1];
REG4 = REG3[REG2 + 24];
REG5 = REG3[REG2 + 4];
REG20 = REG4 + REG5;
REG3 = static_0_89_cmaxy;
REG2 = 0;
REG4 = REG3[REG2 + 0];
REG2 = (REG20 > REG4) ? 1 : 0;
state = REG2 ? 25 : 23; break;
case 25: // basic block start for source line 4900
REG3 = static_0_89_cmaxy;
REG2 = 0;
REG3[REG2 + 0] = REG20;
state = 23; break;
case 26: // basic block start for source line 4905
REG3 = static_0_93_chpos;
REG2 = 0;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG2 = REG4 + REG13;
REG3 = REG5[REG2 + 0];
REG22[REG21 + 4] = REG3;
REG3 = static_0_93_chpos;
REG2 = 0;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG2 = REG4 + REG13;
REG3 = REG5[REG2 + 0];
state = REG3 ? 22 : 27; break;
case 27: // basic block start for source line 4908
REG3 = static_0_96_yspacing;
REG2 = 0;
REG4 = REG3[REG2 + 0];
REG2 = REG18[REG17 + 0];
REG3 = REG18[REG17 + 1];
REG3[REG2 + 4] = REG4;
state = 22; break;
case 28: // basic block start for source line 4936
REG2 = static_0_119_clear_clevelnodes;
REG2(sp, stack, REG0, REG1);
REG23 = REG1[REG0 + 28];
REG24 = REG1[REG0 + 29];
state = REG24 ? 29 : 30; break;
case 29: // basic block start for source line 4940
REG2 = free;
REG2(sp, stack, REG23, REG24);
REG2 = 0;
REG1[REG0 + 28] = REG2;
state = 30; break;
case 30: // basic block start for source line 4790
return;
} } }

function static_0_121_movefinal(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_85_cnodelist;
REG3 = 0;
REG5 = REG4[REG3 + 0];
REG6 = REG4[REG3 + 1];
REG1 = REG5;
REG2 = REG6;
state = 1; break;
case 1: // basic block start for source line 4953
state = REG2 ? 2 : 3; break;
case 2: // basic block start for source line 4954
REG3 = REG2[REG1 + 0];
REG4 = REG2[REG1 + 1];
REG5 = REG4[REG3 + 23];
REG6 = REG5 + REG0;
REG4[REG3 + 23] = REG6;
REG3 = REG2[REG1 + 0];
REG4 = REG2[REG1 + 1];
REG5 = REG4[REG3 + 19];
REG6 = REG5 + REG0;
REG4[REG3 + 19] = REG6;
REG3 = REG2[REG1 + 0];
REG4 = REG2[REG1 + 1];
REG5 = REG4[REG3 + 21];
REG6 = REG5 + REG0;
REG4[REG3 + 21] = REG6;
REG3 = REG2[REG1 + 1];
REG4 = REG2[REG1 + 2];
REG1 = REG3;
REG2 = REG4;
state = 1; break;
case 3: // basic block start for source line 4947
return;
} } }

function static_0_122_tunedummy(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = REG1[REG0 + 15];
REG5 = REG1[REG0 + 16];
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 1: // basic block start for source line 4973
state = REG3 ? 3 : 9; break;
case 2: // basic block start for source line 4991
REG0 = REG3[REG2 + 1];
REG1 = REG3[REG2 + 2];
REG2 = REG0;
REG3 = REG1;
state = 1; break;
case 3: // basic block start for source line 4974
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG0 = REG5[REG4 + 5];
state = REG0 ? 4 : 2; break;
case 4: // basic block start for source line 4975
REG6 = REG5[REG4 + 23];
REG0 = REG5[REG4 + 27];
REG1 = REG5[REG4 + 28];
REG9 = REG1[REG0 + 0];
REG10 = REG1[REG0 + 1];
REG11 = REG10[REG9 + 1];
REG12 = REG10[REG9 + 2];
REG9 = REG12[REG11 + 23];
REG10 = REG1[REG0 + 0];
REG11 = REG1[REG0 + 1];
REG0 = REG11[REG10 + 1];
REG1 = REG11[REG10 + 2];
REG10 = REG1[REG0 + 3];
REG0 = 2;
REG1 = REG10 / REG0;
REG1 = (REG1).toFixed();
REG7 = REG9 + REG1;
REG0 = REG5[REG4 + 25];
REG1 = REG5[REG4 + 26];
REG9 = REG1[REG0 + 0];
REG10 = REG1[REG0 + 1];
REG11 = REG10[REG9 + 2];
REG12 = REG10[REG9 + 3];
REG9 = REG12[REG11 + 23];
REG10 = REG1[REG0 + 0];
REG11 = REG1[REG0 + 1];
REG0 = REG11[REG10 + 2];
REG1 = REG11[REG10 + 3];
REG10 = REG1[REG0 + 3];
REG0 = 2;
REG1 = REG10 / REG0;
REG1 = (REG1).toFixed();
REG8 = REG9 + REG1;
REG0 = (REG6 == REG7) ? 1 : 0;
REG1 = (REG6 == REG8) ? 1 : 0;
REG9 = REG0 & REG1;
state = REG9 ? 2 : 5; break;
case 5: // basic block start for source line 4981
REG0 = (REG7 < REG6) ? 1 : 0;
REG1 = (REG8 < REG6) ? 1 : 0;
REG9 = REG0 & REG1;
state = REG9 ? 6 : 7; break;
case 6: // basic block start for source line 4983
REG0 = REG5[REG4 + 19];
REG5[REG4 + 23] = REG0;
state = 7; break;
case 7: // basic block start for source line 4985
REG0 = (REG7 > REG6) ? 1 : 0;
REG1 = (REG8 > REG6) ? 1 : 0;
REG4 = REG0 & REG1;
state = REG4 ? 8 : 2; break;
case 8: // basic block start for source line 4987
REG0 = REG3[REG2 + 0];
REG1 = REG3[REG2 + 1];
REG4 = REG1[REG0 + 21];
REG1[REG0 + 23] = REG4;
state = 2; break;
case 9: // basic block start for source line 4964
return;
} } }

function static_0_123_tunenodes(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = REG1[REG0 + 15];
REG5 = REG1[REG0 + 16];
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 1: // basic block start for source line 5004
state = REG3 ? 3 : 18; break;
case 2: // basic block start for source line 5036
REG0 = REG3[REG2 + 1];
REG1 = REG3[REG2 + 2];
REG2 = REG0;
REG3 = REG1;
state = 1; break;
case 3: // basic block start for source line 5006
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG0 = REG5[REG4 + 5];
state = REG0 ? 2 : 4; break;
case 4: // basic block start for source line 5007
REG0 = REG5[REG4 + 13];
state = REG0 ? 2 : 5; break;
case 5: // basic block start for source line 5010
REG0 = REG5[REG4 + 11];
REG1 = 0;
REG6 = (REG0 > REG1) ? 1 : 0;
state = REG6 ? 6 : 8; break;
case 6: // basic block start for source line 5010
REG0 = REG5[REG4 + 12];
state = REG0 ? 8 : 7; break;
case 7: // basic block start for source line 5012
REG0 = REG5[REG4 + 20];
REG5[REG4 + 24] = REG0;
state = 8; break;
case 8: // basic block start for source line 5014
REG6 = REG3[REG2 + 0];
REG7 = REG3[REG2 + 1];
REG0 = REG7[REG6 + 11];
state = REG0 ? 11 : 9; break;
case 9: // basic block start for source line 5014
REG0 = REG7[REG6 + 12];
REG1 = 0;
REG4 = (REG0 > REG1) ? 1 : 0;
state = REG4 ? 10 : 11; break;
case 10: // basic block start for source line 5016
REG0 = REG7[REG6 + 22];
REG1 = REG7[REG6 + 4];
REG4 = REG0 - REG1;
REG7[REG6 + 24] = REG4;
state = 11; break;
case 11: // basic block start for source line 5018
REG8 = REG3[REG2 + 0];
REG9 = REG3[REG2 + 1];
REG10 = REG9[REG8 + 11];
REG0 = 0;
REG1 = (REG10 > REG0) ? 1 : 0;
state = REG1 ? 12 : 2; break;
case 12: // basic block start for source line 5018
REG11 = REG9[REG8 + 12];
REG0 = 0;
REG1 = (REG11 > REG0) ? 1 : 0;
state = REG1 ? 13 : 2; break;
case 13: // basic block start for source line 5019
REG0 = (REG10 == REG11) ? 1 : 0;
state = REG0 ? 2 : 14; break;
case 14: // basic block start for source line 5024
REG0 = (REG10 > REG11) ? 1 : 0;
state = REG0 ? 15 : 16; break;
case 15: // basic block start for source line 5026
REG0 = REG9[REG8 + 20];
REG9[REG8 + 24] = REG0;
state = 16; break;
case 16: // basic block start for source line 5028
REG12 = REG3[REG2 + 0];
REG13 = REG3[REG2 + 1];
REG0 = REG13[REG12 + 12];
REG1 = REG13[REG12 + 11];
REG4 = (REG0 > REG1) ? 1 : 0;
state = REG4 ? 17 : 2; break;
case 17: // basic block start for source line 5030
REG0 = REG13[REG12 + 22];
REG1 = REG13[REG12 + 4];
REG4 = REG0 - REG1;
REG13[REG12 + 24] = REG4;
state = 2; break;
case 18: // basic block start for source line 4998
return;
} } }

function static_0_124_improve_positions(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = REG1[REG0 + 13];
REG6 = static_0_95_xspacing;
REG5 = 0;
REG6[REG5 + 0] = REG4;
REG4 = REG1[REG0 + 14];
REG6 = static_0_96_yspacing;
REG5 = 0;
REG6[REG5 + 0] = REG4;
REG4 = REG1[REG0 + 15];
REG5 = REG1[REG0 + 16];
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 1: // basic block start for source line 5055
state = REG3 ? 2 : 3; break;
case 2: // basic block start for source line 5056
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG6 = REG5[REG4 + 1];
REG5[REG4 + 3] = REG6;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG6 = REG5[REG4 + 2];
REG5[REG4 + 4] = REG6;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG6 = REG5[REG4 + 15];
REG5[REG4 + 17] = REG6;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG6 = REG5[REG4 + 16];
REG5[REG4 + 18] = REG6;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG6 = 0;
REG5[REG4 + 23] = REG6;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG6 = 0;
REG5[REG4 + 24] = REG6;
REG4 = REG3[REG2 + 1];
REG5 = REG3[REG2 + 2];
REG2 = REG4;
REG3 = REG5;
state = 1; break;
case 3: // basic block start for source line 5066
REG4 = 0;
REG5 = 0;
state = 4; break;
case 4: // basic block start for source line 5068
REG2 = REG1[REG0 + 11];
REG3 = (REG4 < REG2) ? 1 : 0;
state = REG3 ? 5 : 6; break;
case 5: // basic block start for source line 5070
REG2 = REG1[REG0 + 12];
REG3 = REG1[REG0 + 13];
REG6 = REG2 + REG4;
REG2 = REG3[REG6 + 0];
REG6 = static_0_84_csn;
REG3 = 0;
REG6[REG3 + 0] = REG2;
REG2 = 0;
REG6 = static_0_88_cmaxx;
REG3 = 0;
REG6[REG3 + 0] = REG2;
REG2 = static_0_113_make_cnodelist;
REG2(sp, stack, REG0, REG1);
REG2 = static_0_111_make_cnnodes_at_level;
REG2(sp, stack, REG0, REG1);
REG2 = static_0_110_improve_positions2local;
REG2(sp, stack, REG0, REG1);
REG2 = static_0_115_move0;
REG2(sp, stack);
REG2 = static_0_120_cfinalxy;
REG2(sp, stack, REG0, REG1);
REG2 = static_0_122_tunedummy;
REG2(sp, stack, REG0, REG1);
REG2 = static_0_123_tunenodes;
REG2(sp, stack, REG0, REG1);
REG2 = static_0_121_movefinal;
REG2(sp, stack, REG5);
REG3 = static_0_88_cmaxx;
REG2 = 0;
REG6 = REG3[REG2 + 0];
REG2 = REG5 + REG6;
REG6 = static_0_95_xspacing;
REG3 = 0;
REG7 = REG6[REG3 + 0];
REG3 = REG2 + REG7;
REG2 = static_0_112_clear_cnnodes_at_level;
REG2(sp, stack);
REG2 = static_0_114_clear_cnodelist;
REG2(sp, stack);
REG2 = 1;
REG6 = REG4 + REG2;
REG4 = REG6;
REG5 = REG3;
state = 4; break;
case 6: // basic block start for source line 5114
return;
} } }

function static_0_125_finalxy(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var REG16;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG3 = REG1[REG0 + 8];
REG2 = 0;
state = REG3 ? 1 : 8; break;
case 1: // basic block start for source line 5132
REG7 = static_0_0_maingraph;
REG2 = 0;
REG8 = REG7[REG2 + 0];
REG9 = REG7[REG2 + 1];
REG2 = REG9[REG8 + 17];
REG7 = REG9[REG8 + 18];
REG3 = REG2;
REG4 = REG7;
REG5 = 0;
REG6 = 0;
state = 2; break;
case 2: // basic block start for source line 5133
state = REG4 ? 3 : 4; break;
case 3: // basic block start for source line 5134
REG2 = REG4[REG3 + 0];
REG7 = REG4[REG3 + 1];
REG7[REG2 + 23] = REG5;
REG2 = REG1[REG0 + 13];
REG7 = REG5 + REG2;
REG2 = REG4[REG3 + 0];
REG8 = REG4[REG3 + 1];
REG9 = REG8[REG2 + 3];
REG10 = REG7 + REG9;
REG7 = REG8[REG2 + 4];
REG2 = (REG7 > REG6) ? 1 : 0;
if (REG2) { REG8 = REG7; } else { REG8 = REG6; }
REG2 = REG4[REG3 + 1];
REG7 = REG4[REG3 + 2];
REG3 = REG2;
REG4 = REG7;
REG5 = REG10;
REG6 = REG8;
state = 2; break;
case 4: // basic block start for source line 5141
REG2 = REG1[REG0 + 14];
REG7 = REG6 + REG2;
REG3 = static_0_0_maingraph;
REG2 = 0;
REG4 = REG3[REG2 + 0];
REG5 = REG3[REG2 + 1];
REG2 = REG5[REG4 + 17];
REG3 = REG5[REG4 + 18];
REG8 = REG2;
REG9 = REG3;
state = 5; break;
case 5: // basic block start for source line 5144
state = REG9 ? 6 : 7; break;
case 6: // basic block start for source line 5145
REG2 = REG9[REG8 + 0];
REG3 = REG9[REG8 + 1];
REG4 = 0;
REG3[REG2 + 20] = REG4;
REG2 = REG9[REG8 + 0];
REG3 = REG9[REG8 + 1];
REG3[REG2 + 22] = REG7;
REG2 = REG9[REG8 + 1];
REG3 = REG9[REG8 + 2];
REG8 = REG2;
REG9 = REG3;
state = 5; break;
case 7: // basic block start for source line 5144
REG2 = REG7;
state = 8; break;
case 8: // basic block start for source line 5152
REG4 = static_0_0_maingraph;
REG3 = 0;
REG5 = REG4[REG3 + 0];
REG6 = REG4[REG3 + 1];
REG3 = REG6[REG5 + 15];
REG4 = REG6[REG5 + 16];
REG10 = REG3;
REG11 = REG4;
REG12 = 0;
REG13 = 0;
state = 9; break;
case 9: // basic block start for source line 5153
state = REG11 ? 12 : 14; break;
case 10: // basic block start for source line 5165
REG3 = REG11[REG10 + 0];
REG4 = REG11[REG10 + 1];
REG5 = REG4[REG3 + 24];
REG6 = REG4[REG3 + 4];
REG3 = REG5 + REG6;
REG4 = (REG3 > REG13) ? 1 : 0;
if (REG4) { REG5 = REG3; } else { REG5 = REG13; }
REG3 = REG11[REG10 + 1];
REG4 = REG11[REG10 + 2];
REG10 = REG3;
REG11 = REG4;
REG12 = REG16;
REG13 = REG5;
state = 9; break;
case 11: // basic block start for source line 5160
REG3 = REG15[REG14 + 12];
state = REG3 ? 13 : 10; break;
case 12: // basic block start for source line 5155
REG14 = REG11[REG10 + 0];
REG15 = REG11[REG10 + 1];
REG3 = REG15[REG14 + 23];
REG4 = REG15[REG14 + 3];
REG5 = REG3 + REG4;
REG3 = (REG5 > REG12) ? 1 : 0;
if (REG3) { REG16 = REG5; } else { REG16 = REG12; }
REG3 = REG15[REG14 + 11];
state = REG3 ? 13 : 11; break;
case 13: // basic block start for source line 5161
REG3 = REG15[REG14 + 24];
REG4 = REG3 + REG2;
REG15[REG14 + 24] = REG4;
state = 10; break;
case 14: // basic block start for source line 5172
REG1[REG0 + 29] = REG12;
REG1[REG0 + 30] = REG13;
return;
} } }

function static_0_126_findedge(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG4 = static_0_0_maingraph;
REG3 = 0;
REG1 = REG4[REG3 + 0];
REG2 = REG4[REG3 + 1];
state = REG2 ? 5 : 1; break;
case 1: // basic block start for source line 5183
REG3 = 0;
state = 2; break;
case 2: // basic block start for source line 5178
return [REG3, REG4];
case 3: // basic block start for source line 5193
REG3 = REG11;
REG4 = REG12;
state = 2; break;
case 4: // basic block start for source line 5186
REG11 = REG7;
REG12 = REG8;
state = REG6 ? 7 : 3; break;
case 5: // basic block start for source line 5185
REG3 = REG2[REG1 + 19];
REG4 = REG2[REG1 + 20];
REG5 = REG3;
REG6 = REG4;
REG7 = 0;
state = 4; break;
case 6: // basic block start for source line 5191
REG1 = REG6[REG5 + 1];
REG2 = REG6[REG5 + 2];
REG5 = REG1;
REG6 = REG2;
REG7 = REG9;
REG8 = REG10;
state = 4; break;
case 7: // basic block start for source line 5187
REG9 = REG6[REG5 + 0];
REG10 = REG6[REG5 + 1];
REG1 = REG10[REG9 + 0];
REG2 = (REG1 == REG0) ? 1 : 0;
state = REG2 ? 8 : 6; break;
case 8: // basic block start for source line 5189
REG11 = REG9;
REG12 = REG10;
state = 3; break;
} } }

function static_0_127_setminmax(fp, stack, REG0) {
var sp;
var REG1;
var REG2;
var REG3;
var REG4;
var REG5;
var REG6;
var REG7;
var REG8;
var REG9;
var REG10;
var REG11;
var REG12;
var REG13;
var REG14;
var REG15;
var state = 0;
for (;;) {
switch (state) {
case 0:
sp = 0;
sp = fp + sp;
REG9 = 0;
REG1[REG0 + 31] = REG9;
REG9 = 0;
REG1[REG0 + 32] = REG9;
REG9 = 0;
REG1[REG0 + 33] = REG9;
REG9 = 0;
REG1[REG0 + 34] = REG9;
REG9 = REG1[REG0 + 15];
REG10 = REG1[REG0 + 16];
REG6 = REG9;
REG7 = REG10;
REG8 = 0;
REG5 = 0;
REG4 = 0;
REG3 = 0;
REG2 = 0;
state = 1; break;
case 1: // basic block start for source line 5210
state = REG7 ? 4 : 9; break;
case 2: // basic block start for source line 5222
REG9 = 1;
REG10 = REG8 + REG9;
REG9 = REG7[REG6 + 1];
REG11 = REG7[REG6 + 2];
REG6 = REG9;
REG7 = REG11;
REG8 = REG10;
state = 1; break;
case 3: // basic block start for source line 5212
REG9 = REG7[REG6 + 0];
REG10 = REG7[REG6 + 1];
REG11 = REG10[REG9 + 0];
REG1[REG0 + 31] = REG11;
REG9 = REG7[REG6 + 0];
REG10 = REG7[REG6 + 1];
REG12 = REG10[REG9 + 0];
REG1[REG0 + 32] = REG12;
REG3 = REG12;
REG2 = REG11;
state = 2; break;
case 4: // basic block start for source line 5211
state = REG8 ? 5 : 3; break;
case 5: // basic block start for source line 5215
REG10 = REG7[REG6 + 0];
REG11 = REG7[REG6 + 1];
REG9 = REG11[REG10 + 0];
REG10 = (REG9 < REG2) ? 1 : 0;
state = REG10 ? 6 : 7; break;
case 6: // basic block start for source line 5216
REG1[REG0 + 31] = REG9;
REG2 = REG9;
state = 7; break;
case 7: // basic block start for source line 5218
REG9 = REG7[REG6 + 0];
REG11 = REG7[REG6 + 1];
REG10 = REG11[REG9 + 0];
REG9 = (REG10 > REG3) ? 1 : 0;
state = REG9 ? 8 : 2; break;
case 8: // basic block start for source line 5219
REG1[REG0 + 32] = REG10;
REG3 = REG10;
state = 2; break;
case 9: // basic block start for source line 5226
REG2 = REG1[REG0 + 19];
REG3 = REG1[REG0 + 20];
REG11 = REG2;
REG12 = REG3;
REG13 = 0;
state = 10; break;
case 10: // basic block start for source line 5228
state = REG12 ? 13 : 18; break;
case 11: // basic block start for source line 5240
REG2 = 1;
REG3 = REG13 + REG2;
REG2 = REG12[REG11 + 1];
REG6 = REG12[REG11 + 2];
REG11 = REG2;
REG12 = REG6;
REG13 = REG3;
state = 10; break;
case 12: // basic block start for source line 5230
REG2 = REG12[REG11 + 0];
REG3 = REG12[REG11 + 1];
REG6 = REG3[REG2 + 0];
REG1[REG0 + 33] = REG6;
REG2 = REG12[REG11 + 0];
REG3 = REG12[REG11 + 1];
REG7 = REG3[REG2 + 0];
REG1[REG0 + 34] = REG7;
REG5 = REG7;
REG4 = REG6;
state = 11; break;
case 13: // basic block start for source line 5229
state = REG13 ? 14 : 12; break;
case 14: // basic block start for source line 5233
REG2 = REG12[REG11 + 0];
REG3 = REG12[REG11 + 1];
REG14 = REG3[REG2 + 0];
REG2 = (REG14 < REG4) ? 1 : 0;
state = REG2 ? 15 : 16; break;
case 15: // basic block start for source line 5234
REG1[REG0 + 33] = REG14;
REG4 = REG14;
state = 16; break;
case 16: // basic block start for source line 5236
REG2 = REG12[REG11 + 0];
REG3 = REG12[REG11 + 1];
REG15 = REG3[REG2 + 0];
REG2 = (REG15 > REG5) ? 1 : 0;
state = REG2 ? 17 : 11; break;
case 17: // basic block start for source line 5237
REG1[REG0 + 34] = REG15;
REG5 = REG15;
state = 11; break;
case 18: // basic block start for source line 5197
return;
} } }


function initializer() {
var REG0;
var REG1;
var state = 0;
for (;;) {
switch (state) {
case 0:
static_0_0_maingraph = []; // create storage size 1
REG0 = static_0_0_maingraph;
// cg_export for sfg_version
// cg_export for sfg_init
// cg_export for sfg_deinit
// cg_export for sfg_addnode
// cg_export for sfg_addedge
// cg_export for sfg_layout
// cg_export for sfg_crossings
// cg_export for sfg_initialcrossings
// cg_export for sfg_edgelabels
// cg_export for sfg_nodexpos
// cg_export for sfg_nodeypos
// cg_export for sfg_noderelxpos
// cg_export for sfg_noderelypos
// cg_export for sfg_nodely0
// cg_export for sfg_nodely1
// cg_export for sfg_nodexsize
// cg_export for sfg_nodeysize
// cg_export for sfg_xspacing
// cg_export for sfg_yspacing
// cg_export for sfg_maxx
// cg_export for sfg_maxy
// cg_export for sfg_nodemin
// cg_export for sfg_nodemax
// cg_export for sfg_edgemin
// cg_export for sfg_edgemax
// cg_export for sfg_nlevels
// cg_export for sfg_nnodes
// cg_export for sfg_nedges
// cg_export for sfg_nodetype
// cg_export for sfg_nodeselfedges
// cg_export for sfg_nodeindegree
// cg_export for sfg_nodeoutdegree
// cg_export for sfg_nodeenum
// cg_export for sfg_nodedata
// cg_export for sfg_setnodedata
// cg_export for sfg_edgefrom
// cg_export for sfg_edgeto
// cg_export for sfg_edgetype
// cg_export for sfg_edgerev
static_0_83_mindist = []; // create storage size 1
REG0 = static_0_83_mindist;
static_0_84_csn = []; // create storage size 1
REG0 = static_0_84_csn;
static_0_85_cnodelist = []; // create storage size 1
REG0 = static_0_85_cnodelist;
static_0_86_cnodelisttail = []; // create storage size 1
REG0 = static_0_86_cnodelisttail;
static_0_87_cnnodes_of_level = []; // create storage size 1
REG0 = static_0_87_cnnodes_of_level;
static_0_88_cmaxx = []; // create storage size 1
REG0 = static_0_88_cmaxx;
static_0_89_cmaxy = []; // create storage size 1
REG0 = static_0_89_cmaxy;
static_0_90_cwidestnnodes = []; // create storage size 1
REG0 = static_0_90_cwidestnnodes;
static_0_91_cwpos = []; // create storage size 1
REG0 = static_0_91_cwpos;
static_0_92_cposnodes = []; // create storage size 1
REG0 = static_0_92_cposnodes;
static_0_93_chpos = []; // create storage size 1
REG0 = static_0_93_chpos;
static_0_94_clevelnodes = []; // create storage size 1
REG0 = static_0_94_clevelnodes;
static_0_95_xspacing = []; // create storage size 1
REG0 = static_0_95_xspacing;
static_0_96_yspacing = []; // create storage size 1
REG0 = static_0_96_yspacing;
static_0_97_nl = []; // create storage size 1
REG0 = static_0_97_nl;
return;
} } }

clue_add_initializer(initializer);
