#-----------------------------------------------------------
# Vivado v2023.1 (64-bit)
# SW Build 3865809 on Sun May  7 15:05:29 MDT 2023
# IP Build 3864474 on Sun May  7 20:36:21 MDT 2023
# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
# Start of session at: Thu Jun  8 10:53:46 2023
# Process ID: 15312
# Current directory: C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.runs/impl_1
# Command line: vivado.exe -log basys3top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source basys3top.tcl -notrace
# Log file: C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.runs/impl_1/basys3top.vdi
# Journal file: C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.runs/impl_1\vivado.jou
# Running On: DESKTOP-5QEHRRG, OS: Windows, CPU Frequency: 3693 MHz, CPU Physical cores: 12, Host memory: 34281 MB
#-----------------------------------------------------------
source basys3top.tcl -notrace
Command: link_design -top basys3top -part xc7a35tcpg236-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 842.500 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2023.1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/constrs_1/new/basys3.xdc]
Finished Parsing XDC File [C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/constrs_1/new/basys3.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 973.996 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.788 . Memory (MB): peak = 996.988 ; gain = 18.988

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: be8f9ab6

Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1511.156 ; gain = 514.168

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: be8f9ab6

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1853.645 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: be8f9ab6

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1853.645 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: df2e2438

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1853.645 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: df2e2438

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.044 . Memory (MB): peak = 1853.645 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 5 Shift Register Optimization | Checksum: 1114c802e

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1853.645 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 1114c802e

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.051 . Memory (MB): peak = 1853.645 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |               0  |                                              0  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               0  |               0  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1853.645 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 1114c802e

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1853.645 ; gain = 0.000

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 1114c802e

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1853.645 ; gain = 0.000

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 1114c802e

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1853.645 ; gain = 0.000

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1853.645 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 1114c802e

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1853.645 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1853.645 ; gain = 875.645
INFO: [runtcl-4] Executing : report_drc -file basys3top_drc_opted.rpt -pb basys3top_drc_opted.pb -rpx basys3top_drc_opted.rpx
Command: report_drc -file basys3top_drc_opted.rpt -pb basys3top_drc_opted.pb -rpx basys3top_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2023.1/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.runs/impl_1/basys3top_drc_opted.rpt.
report_drc completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1853.645 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.runs/impl_1/basys3top_opt.dcp' has been generated.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1853.645 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 10e0a9a6d

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1853.645 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1853.645 ; gain = 0.000

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fce2f43b

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.157 . Memory (MB): peak = 1853.645 ; gain = 0.000

Phase 1.3 Build Placer Netlist Model
WARNING: [Place 30-2953] Timing driven mode will be turned off because no critical terminals were found.
Phase 1.3 Build Placer Netlist Model | Checksum: 1b83f5412

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.235 . Memory (MB): peak = 1853.645 ; gain = 0.000

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1b83f5412

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.237 . Memory (MB): peak = 1853.645 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 1b83f5412

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.240 . Memory (MB): peak = 1853.645 ; gain = 0.000

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1b83f5412

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.247 . Memory (MB): peak = 1853.645 ; gain = 0.000

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1b83f5412

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.247 . Memory (MB): peak = 1853.645 ; gain = 0.000

Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 1b83f5412

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.247 . Memory (MB): peak = 1853.645 ; gain = 0.000

Phase 2.4 Global Placement Core
WARNING: [Place 46-29] Timing had been disabled during Placer and, therefore, physical synthesis in Placer will be skipped.
Phase 2.4 Global Placement Core | Checksum: 1c5fbef28

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.622 . Memory (MB): peak = 1853.645 ; gain = 0.000
Phase 2 Global Placement | Checksum: 1c5fbef28

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.624 . Memory (MB): peak = 1853.645 ; gain = 0.000

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1c5fbef28

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.625 . Memory (MB): peak = 1853.645 ; gain = 0.000

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 14df374bb

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.629 . Memory (MB): peak = 1853.645 ; gain = 0.000

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1d3742cdf

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.635 . Memory (MB): peak = 1853.645 ; gain = 0.000

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1d3742cdf

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.635 . Memory (MB): peak = 1853.645 ; gain = 0.000

Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 26216978c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.702 . Memory (MB): peak = 1853.645 ; gain = 0.000

Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 26216978c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.703 . Memory (MB): peak = 1853.645 ; gain = 0.000

Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 26216978c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.704 . Memory (MB): peak = 1853.645 ; gain = 0.000
Phase 3 Detail Placement | Checksum: 26216978c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.704 . Memory (MB): peak = 1853.645 ; gain = 0.000

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
Phase 4.1 Post Commit Optimization | Checksum: 26216978c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.731 . Memory (MB): peak = 1853.645 ; gain = 0.000

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 26216978c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.732 . Memory (MB): peak = 1853.645 ; gain = 0.000

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
|           | Global Congestion | Short Congestion  |
| Direction | Region Size       | Region Size       |
|___________|___________________|___________________|
|      North|                1x1|                1x1|
|___________|___________________|___________________|
|      South|                1x1|                1x1|
|___________|___________________|___________________|
|       East|                1x1|                1x1|
|___________|___________________|___________________|
|       West|                1x1|                1x1|
|___________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: 26216978c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.733 . Memory (MB): peak = 1853.645 ; gain = 0.000
Phase 4.3 Placer Reporting | Checksum: 26216978c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.733 . Memory (MB): peak = 1853.645 ; gain = 0.000

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1853.645 ; gain = 0.000

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.734 . Memory (MB): peak = 1853.645 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 26216978c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.734 . Memory (MB): peak = 1853.645 ; gain = 0.000
Ending Placer Task | Checksum: 16d7f79d4

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.734 . Memory (MB): peak = 1853.645 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
43 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
INFO: [runtcl-4] Executing : report_io -file basys3top_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1853.645 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file basys3top_utilization_placed.rpt -pb basys3top_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file basys3top_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1853.645 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1853.645 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.runs/impl_1/basys3top_placed.dcp' has been generated.
Command: phys_opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'

Starting Initial Update Timing Task
INFO: [Timing 38-35] Done setting XDC timing constraints.

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1853.645 ; gain = 0.000
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
INFO: [Common 17-83] Releasing license: Implementation
53 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1864.074 ; gain = 10.430
INFO: [Common 17-1381] The checkpoint 'C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.runs/impl_1/basys3top_physopt.dcp' has been generated.
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs

Phase 1 Build RT Design
Checksum: PlaceDB: 7548f48e ConstDB: 0 ShapeSum: f8368546 RouteDB: 0
Post Restoration Checksum: NetGraph: a029b6ca | NumContArr: bbf5f8cc | Constraints: 190a55ad | Timing: 0
Phase 1 Build RT Design | Checksum: 1752a0543

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1946.852 ; gain = 69.730

Phase 2 Router Initialization

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 1752a0543

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1946.852 ; gain = 69.730

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 1752a0543

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1946.852 ; gain = 69.730
 Number of Nodes with overlaps = 0

Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 211839185

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1950.641 ; gain = 73.520
INFO: [Route 35-416] Intermediate Timing Summary | WNS=7.990  | TNS=0.000  | WHS=-0.015 | THS=-0.079 |


Router Utilization Summary
  Global Vertical Routing Utilization    = 0 %
  Global Horizontal Routing Utilization  = 0 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 24
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 24
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 2 Router Initialization | Checksum: 2300fed4b

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1950.703 ; gain = 73.582

Phase 3 Initial Routing

Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 2300fed4b

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1950.703 ; gain = 73.582
Phase 3 Initial Routing | Checksum: 133732278

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1950.703 ; gain = 73.582

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=7.715  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: fe941326

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1950.703 ; gain = 73.582
Phase 4 Rip-up And Reroute | Checksum: fe941326

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1950.703 ; gain = 73.582

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: fe941326

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1950.703 ; gain = 73.582

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: fe941326

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1950.703 ; gain = 73.582
Phase 5 Delay and Skew Optimization | Checksum: fe941326

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1950.703 ; gain = 73.582

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 14a1c9c7d

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1950.703 ; gain = 73.582
INFO: [Route 35-416] Intermediate Timing Summary | WNS=7.808  | TNS=0.000  | WHS=0.238  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 14a1c9c7d

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1950.703 ; gain = 73.582
Phase 6 Post Hold Fix | Checksum: 14a1c9c7d

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1950.703 ; gain = 73.582

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.00390656 %
  Global Horizontal Routing Utilization  = 0.00351379 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 14a1c9c7d

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1950.703 ; gain = 73.582

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 14a1c9c7d

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1951.395 ; gain = 74.273

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 182cb4b3e

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1951.395 ; gain = 74.273

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=7.808  | TNS=0.000  | WHS=0.238  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 182cb4b3e

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1951.395 ; gain = 74.273
INFO: [Route 35-16] Router Completed Successfully

Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 1aa023b93

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1951.395 ; gain = 74.273

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1951.395 ; gain = 74.273

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
67 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1951.395 ; gain = 87.320
INFO: [runtcl-4] Executing : report_drc -file basys3top_drc_routed.rpt -pb basys3top_drc_routed.pb -rpx basys3top_drc_routed.rpx
Command: report_drc -file basys3top_drc_routed.rpt -pb basys3top_drc_routed.pb -rpx basys3top_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.runs/impl_1/basys3top_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file basys3top_methodology_drc_routed.rpt -pb basys3top_methodology_drc_routed.pb -rpx basys3top_methodology_drc_routed.rpx
Command: report_methodology -file basys3top_methodology_drc_routed.rpt -pb basys3top_methodology_drc_routed.pb -rpx basys3top_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.runs/impl_1/basys3top_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file basys3top_power_routed.rpt -pb basys3top_power_summary_routed.pb -rpx basys3top_power_routed.rpx
Command: report_power -file basys3top_power_routed.rpt -pb basys3top_power_summary_routed.pb -rpx basys3top_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
77 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file basys3top_route_status.rpt -pb basys3top_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file basys3top_timing_summary_routed.rpt -pb basys3top_timing_summary_routed.pb -rpx basys3top_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [runtcl-4] Executing : report_incremental_reuse -file basys3top_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file basys3top_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file basys3top_bus_skew_routed.rpt -pb basys3top_bus_skew_routed.pb -rpx basys3top_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1990.594 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.runs/impl_1/basys3top_routed.dcp' has been generated.
Command: write_bitstream -force basys3top.bit -bin_file
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Bitstream compression saved 15936096 bits.
Writing bitstream ./basys3top.bit...
Writing bitstream ./basys3top.bin...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2488.621 ; gain = 498.027
INFO: [Common 17-206] Exiting Vivado at Thu Jun  8 10:54:28 2023...
