README-DEVELOPERS.lyx 20 KB

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  40. \index Index
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  57. \end_header
  58. \begin_body
  59. \begin_layout Title
  60. Toprammer - Developers guide
  61. \end_layout
  62. \begin_layout Section
  63. Definitions
  64. \end_layout
  65. \begin_layout Description
  66. DUT Device Under Test.
  67. The device put into the ZIF socket of the programmer
  68. \end_layout
  69. \begin_layout Description
  70. VPP Programming voltage for the DUT (usually 12V)
  71. \end_layout
  72. \begin_layout Description
  73. VCC Supply voltage for the DUT
  74. \end_layout
  75. \begin_layout Description
  76. GND Ground for the DUT
  77. \end_layout
  78. \begin_layout Description
  79. ZIF Zero Insert Force socket of the programmer.
  80. \end_layout
  81. \begin_layout Section
  82. TOP2049 device hardware
  83. \end_layout
  84. \begin_layout Standard
  85. The TOP2049 consists of four basic hardware parts
  86. \end_layout
  87. \begin_layout Itemize
  88. USB interface (PDIUSBD12 chip)
  89. \end_layout
  90. \begin_layout Itemize
  91. Microcontroller (Megawin MPC89E52A)
  92. \end_layout
  93. \begin_layout Itemize
  94. FPGA (Xilinx Spartan2 XC2S15)
  95. \end_layout
  96. \begin_layout Itemize
  97. VCC/GND/VPP supply circuitry
  98. \end_layout
  99. \begin_layout Standard
  100. The microcontroller's job is to initialize and communicate to the FPGA and
  101. set up the VCC/GND/VPP supply circuitry.
  102. The microcontroller can receive commands via USB interface to do these
  103. things.
  104. \end_layout
  105. \begin_layout Section
  106. Communicating with the programmer via USB
  107. \end_layout
  108. \begin_layout Standard
  109. In the
  110. \begin_inset Quotes eld
  111. \end_inset
  112. main
  113. \begin_inset Quotes erd
  114. \end_inset
  115. module there is the
  116. \begin_inset Quotes eld
  117. \end_inset
  118. class TOP
  119. \begin_inset Quotes erd
  120. \end_inset
  121. which is used for communication with the programmer device.
  122. The class has various methods for hardware access:
  123. \end_layout
  124. \begin_layout Subsection
  125. cmdRequestVersion()
  126. \end_layout
  127. \begin_layout Standard
  128. Reads the programmer identification and versioning string and returns it.
  129. \end_layout
  130. \begin_layout Subsection
  131. getOscillatorHz()
  132. \end_layout
  133. \begin_layout Standard
  134. Returns the frequency (in Hz) of the oscillator connected to the FPGA clk
  135. pin.
  136. \end_layout
  137. \begin_layout Subsection
  138. getBufferRegSize()
  139. \end_layout
  140. \begin_layout Standard
  141. Returns the size of the
  142. \begin_inset Quotes eld
  143. \end_inset
  144. buffer register
  145. \begin_inset Quotes erd
  146. \end_inset
  147. .
  148. \end_layout
  149. \begin_layout Subsection
  150. cmdReadBufferReg(nrBytes=all)
  151. \end_layout
  152. \begin_layout Standard
  153. Reads the
  154. \begin_inset Quotes eld
  155. \end_inset
  156. buffer register
  157. \begin_inset Quotes erd
  158. \end_inset
  159. from the microcontroller.
  160. That register is used for buffering of data fetched from the FPGA.
  161. If nrBytes is not specified, it reads the whole register.
  162. \end_layout
  163. \begin_layout Subsection
  164. cmdReadBufferReg8()
  165. \end_layout
  166. \begin_layout Standard
  167. Same as cmdReadBufferReg(), but just returns a 8bit int which was formed
  168. by the first 1 byte of the register.
  169. \end_layout
  170. \begin_layout Subsection
  171. cmdReadBufferReg16()
  172. \end_layout
  173. \begin_layout Standard
  174. Same as cmdReadBufferReg(), but just returns a 16bit int which was formed
  175. by the first 2 bytes of the register (little endian).
  176. \end_layout
  177. \begin_layout Subsection
  178. cmdReadBufferReg32()
  179. \end_layout
  180. \begin_layout Standard
  181. Same as cmdReadBufferReg(), but just returns a 32bit int which was formed
  182. by the first 4 bytes of the register (little endian).
  183. \end_layout
  184. \begin_layout Subsection
  185. cmdReadBufferReg48()
  186. \end_layout
  187. \begin_layout Standard
  188. Same as cmdReadBufferReg(), but just returns a 48bit int which was formed
  189. by the first 6 bytes of the register (little endian).
  190. \end_layout
  191. \begin_layout Subsection
  192. cmdSetVPPVoltage(voltage)
  193. \end_layout
  194. \begin_layout Standard
  195. Set VPP (programming voltage) to the specified voltage.
  196. Voltage is a floating point number.
  197. \end_layout
  198. \begin_layout Subsection
  199. cmdSetVCCVoltage(voltage)
  200. \end_layout
  201. \begin_layout Standard
  202. Set VCC (DUT supply voltage) to the specified voltage.
  203. Voltage is a floating point number.
  204. \end_layout
  205. \begin_layout Subsection
  206. cmdLoadGNDLayout(layoutID)
  207. \end_layout
  208. \begin_layout Standard
  209. Load a ZIF-socket GND-layout.
  210. You usually don't want to call this directly.
  211. Use an autogenerated layout instead.
  212. \end_layout
  213. \begin_layout Subsection
  214. cmdLoadVPPLayout(layoutID)
  215. \end_layout
  216. \begin_layout Standard
  217. Load a ZIF-socket VPP-layout.
  218. You usually don't want to call this directly.
  219. Use an autogenerated layout instead.
  220. \end_layout
  221. \begin_layout Subsection
  222. cmdLoadVCCLayout(layoutID)
  223. \end_layout
  224. \begin_layout Standard
  225. Load a ZIF-socket VCC-layout.
  226. You usually don't want to call this directly.
  227. Use an autogenerated layout instead.
  228. \end_layout
  229. \begin_layout Subsection
  230. cmdEnableZifPullups(enable)
  231. \end_layout
  232. \begin_layout Standard
  233. Enable (True) or disable (False) the pullups for all signals on the ZIF
  234. socket.
  235. Default is disabled.
  236. \end_layout
  237. \begin_layout Subsection
  238. cmdFPGAWrite(address, byte)
  239. \end_layout
  240. \begin_layout Standard
  241. Writes a byte to the FPGA using
  242. \begin_inset Quotes eld
  243. \end_inset
  244. address
  245. \begin_inset Quotes erd
  246. \end_inset
  247. for address latching and
  248. \begin_inset Quotes eld
  249. \end_inset
  250. byte
  251. \begin_inset Quotes erd
  252. \end_inset
  253. as payload data.
  254. Note that address 0x10 is fast-tracked and uses one byte less on the USB
  255. bus.
  256. So it is potentially faster.
  257. \end_layout
  258. \begin_layout Subsection
  259. cmdFPGARead(address)
  260. \end_layout
  261. \begin_layout Standard
  262. Reads a byte from the FPGA and puts it into the buffer register.
  263. \begin_inset Quotes eld
  264. \end_inset
  265. address
  266. \begin_inset Quotes erd
  267. \end_inset
  268. is used for address latching on the FPGA.
  269. The microcontroller's buffer register has an automagically incrementing
  270. pointer.
  271. So issueing several cmdFPGARead() in a row will result in all the bytes
  272. being put one after another into the buffer register.
  273. The buffer register does have a limited size.
  274. Overflowing it crashes the programmer, requireing a physical USB disconnect
  275. to recover.
  276. Call getBufferRegSize() to get the size of the buffer register.
  277. Reading the buffer register (cmdReadBufferReg()) will reset the automagic
  278. pointer to zero.
  279. Note that address 0x10 is fast-tracked and uses one byte less on the USB
  280. bus.
  281. So it is potentially faster.
  282. \end_layout
  283. \begin_layout Subsection
  284. cmdDelay(seconds)
  285. \end_layout
  286. \begin_layout Standard
  287. Send a delay command to the programmer.
  288. The Programmer will perform the delay.
  289. A value up to 0.5 seconds is possible.
  290. Note that the actual value will be rounded up to the next possible wait
  291. interval value.
  292. Use this for short (microsecond or low millisecond) delays.
  293. Note that this does _not_ flush the command queue.
  294. \end_layout
  295. \begin_layout Subsection
  296. hostDelay(seconds)
  297. \end_layout
  298. \begin_layout Standard
  299. Sends all queued commands to the device and waits for
  300. \begin_inset Quotes eld
  301. \end_inset
  302. seconds
  303. \begin_inset Quotes erd
  304. \end_inset
  305. .
  306. \begin_inset Quotes eld
  307. \end_inset
  308. seconds
  309. \begin_inset Quotes erd
  310. \end_inset
  311. is a floating point number.
  312. The delay is performed on the host computer by simply not sending commands
  313. to the programmer for the time specified after flushing the command queue.
  314. \end_layout
  315. \begin_layout Section
  316. TX command queueing
  317. \end_layout
  318. \begin_layout Standard
  319. All commands transmitted to the device are not sent immediately, but queued
  320. in software and sent later.
  321. This is done to speed up device access significantly.
  322. The command transmission queue has several flushing conditions:
  323. \end_layout
  324. \begin_layout Itemize
  325. Commands can be flushed explicitely using the
  326. \begin_inset Quotes eld
  327. \end_inset
  328. flushCommands()
  329. \begin_inset Quotes erd
  330. \end_inset
  331. method of
  332. \begin_inset Quotes eld
  333. \end_inset
  334. class TOP
  335. \begin_inset Quotes erd
  336. \end_inset
  337. .
  338. \end_layout
  339. \begin_layout Itemize
  340. Commands are automatically flushed on cmdReadBufferReg() before reading
  341. the data from the device.
  342. This is to ensure sequential consistency of the commands.
  343. \end_layout
  344. \begin_layout Itemize
  345. Commands are flushed on various voltage-layout operations.
  346. \end_layout
  347. \begin_layout Standard
  348. You usually do not need to flush commands explicitely.
  349. \end_layout
  350. \begin_layout Section
  351. Implementing a new chip (DUT) algorithm
  352. \end_layout
  353. \begin_layout Standard
  354. The reading and programming algorithms for the chips (DUTs) are separated
  355. into two parts:
  356. \end_layout
  357. \begin_layout Itemize
  358. Low level FPGA bottom-half
  359. \end_layout
  360. \begin_layout Itemize
  361. High level Python code top-half
  362. \end_layout
  363. \begin_layout Standard
  364. The FPGA bottom-half implements the basic operations (fetching data from
  365. DUT.
  366. Writing data to DUT.
  367. etc...).
  368. It may also implement timingcritical parts of the algorithm.
  369. Everything else is implemented in the high level Python code, that lives
  370. on the other end of the USB line.
  371. \end_layout
  372. \begin_layout Subsection
  373. Python top-half implementation
  374. \end_layout
  375. \begin_layout Standard
  376. The DUT specific top-half lives in the
  377. \begin_inset Quotes eld
  378. \end_inset
  379. libtoprammer/chips
  380. \begin_inset Quotes erd
  381. \end_inset
  382. module.
  383. The files in that module contain the top-half algorithm implementation.
  384. The files are named after the chip ID.
  385. Make sure to update the __init__.py of the module when adding algorithm
  386. implementations.
  387. The top-half files contain a class derived from the
  388. \begin_inset Quotes eld
  389. \end_inset
  390. Chip
  391. \begin_inset Quotes erd
  392. \end_inset
  393. class.
  394. The
  395. \begin_inset Quotes eld
  396. \end_inset
  397. Chip
  398. \begin_inset Quotes erd
  399. \end_inset
  400. class defines the interface that is to be re-implemented in the derived
  401. subclass.
  402. This interface consists of the following methods:
  403. \end_layout
  404. \begin_layout Description
  405. shutdownChip() Called once on chip shutdown.
  406. The default implementation turns off all voltages.
  407. There's usually no need to override that.
  408. \end_layout
  409. \begin_layout Description
  410. readSignature() Read the DUT signature and return it.
  411. Reimplement this, if your DUT supports signature reading.
  412. \end_layout
  413. \begin_layout Description
  414. erase() Erase the DUT.
  415. Reimplement this, if your DUT supports electrical erasing.
  416. \end_layout
  417. \begin_layout Description
  418. test() Run an optional unit-test on the chip.
  419. The generic algorithm GenericAlgorithms.simpleTest may be used to implement
  420. this method.
  421. \end_layout
  422. \begin_layout Description
  423. readProgmem() Read the program memory and return it.
  424. Reimplement this, if your DUT has program memory and supports reading it.
  425. \end_layout
  426. \begin_layout Description
  427. writeProgmem(image) Write the program memory.
  428. Reimplement this, if your DUT has program memory and supports writing it.
  429. \end_layout
  430. \begin_layout Description
  431. readEEPROM() Read the (E)EPROM memory and return it.
  432. Reimplement this, if your DUT has (E)EPROM memory and supports reading
  433. it.
  434. \end_layout
  435. \begin_layout Description
  436. writeEEPROM() Write the (E)EPROM memory.
  437. Reimplement this, if your DUT has (E)EPROM memory and supports writing
  438. it.
  439. \end_layout
  440. \begin_layout Description
  441. readFuse() Read the Fuse memory and return it.
  442. Reimplement this, if your DUT has Fuses and supports reading them.
  443. \end_layout
  444. \begin_layout Description
  445. writeFuse() Write the Fuse memory.
  446. Reimplement this, if your DUT has Fuses and supports writing them.
  447. \end_layout
  448. \begin_layout Description
  449. readLockbits() Read the Lockbit memory and return it.
  450. Reimplement this, if your DUT has Lockbits and supports reading them.
  451. \end_layout
  452. \begin_layout Description
  453. writeLockbits() Write the Lockbit memory.
  454. Reimplement this, if your DUT has Lockbits and supports writing them.
  455. \end_layout
  456. \begin_layout Description
  457. readRAM() Read the Random Access Memory.
  458. Reimplement this, if your DUT has RAM and supports reading it.
  459. \end_layout
  460. \begin_layout Description
  461. writeRAM() Write the Random Access Memory.
  462. Reimplement this, if your DUT has RAM and supports writing to it.
  463. \end_layout
  464. \begin_layout Standard
  465. After defining your
  466. \begin_inset Quotes eld
  467. \end_inset
  468. Chip
  469. \begin_inset Quotes erd
  470. \end_inset
  471. -derived class you need to register it.
  472. This is done by defining a ChipDescription():
  473. \end_layout
  474. \begin_layout LyX-Code
  475. ChipDescription(Chip_MyDevice, bitfile =
  476. \begin_inset Quotes eld
  477. \end_inset
  478. bitfileID
  479. \begin_inset Quotes erd
  480. \end_inset
  481. , chipID =
  482. \begin_inset Quotes eld
  483. \end_inset
  484. myChipID
  485. \begin_inset Quotes erd
  486. \end_inset
  487. )
  488. \end_layout
  489. \begin_layout Standard
  490. The chip class (_not_ an instance of it) is passed as first parameter.
  491. The ID string of the required bitfile is past as second parameter.
  492. A chipID might also be passed.
  493. If the chipID is omitted, the bitfileID is used as chipID.
  494. There are more optional parameters to ChipDescription().
  495. See the inline sourcecode documentation for details.
  496. \end_layout
  497. \begin_layout Subsection
  498. Generic top-half algorithms
  499. \end_layout
  500. \begin_layout Standard
  501. The Python class
  502. \begin_inset Quotes eld
  503. \end_inset
  504. GenericAlgorithms
  505. \begin_inset Quotes erd
  506. \end_inset
  507. in the generic_algorithms.py file provides several generic chip access algorithm
  508. s that can be used in the
  509. \begin_inset Quotes eld
  510. \end_inset
  511. Chip
  512. \begin_inset Quotes erd
  513. \end_inset
  514. methods.
  515. \end_layout
  516. \begin_layout Subsection
  517. FPGA bottom-half implementation
  518. \end_layout
  519. \begin_layout Standard
  520. For the FPGA part you need to get the Xilinx development suite (ISE) version
  521. 10.1 service pack 3.
  522. The "WebPACK", which is sufficient for our purposes, can be downloaded
  523. for free (as in beer) from the Xilinx homepage:
  524. \end_layout
  525. \begin_layout LyX-Code
  526. http://www.xilinx.com/support/download/index.htm
  527. \end_layout
  528. \begin_layout Standard
  529. To create a new sourcecode template fileset for a new chip, go to the libtopramm
  530. er/fpga/src/ subdirectory and execute the "create.sh" script:
  531. \end_layout
  532. \begin_layout LyX-Code
  533. ./create.sh bitfile_name
  534. \end_layout
  535. \begin_layout Standard
  536. Where "bitfile_name" is the name of the new chip's bitfile.
  537. (That often matches the chip-ID).
  538. Now go to libtoprammer/fpga/src/bitfile_name/ and implement the bottom-half
  539. algorithm in the bitfile_name.v Verilog file.
  540. To build the .BIT file from the Verilog sources, go to the libtoprammer/fpga/
  541. directory and execute:
  542. \end_layout
  543. \begin_layout LyX-Code
  544. ./build.sh bitfile_name
  545. \end_layout
  546. \begin_layout Standard
  547. If you omit the
  548. \begin_inset Quotes eld
  549. \end_inset
  550. bitfile_name
  551. \begin_inset Quotes erd
  552. \end_inset
  553. , all bitfiles will be rebuilt.
  554. The resulting .BIT file will be copied to the libtoprammer/fpga/bin/ directory,
  555. after build finished successfully.
  556. \end_layout
  557. \begin_layout Section
  558. Automatic layout generator
  559. \end_layout
  560. \begin_layout Standard
  561. The automatic layout generator (layout_generator.py) can be used to automatically
  562. generate a VCC/VPP/GND layout.
  563. The generator will then tell you how to insert the chip into the ZIF socket.
  564. The advantage of using the autogenerator instead of hardcoding the VCC/VPP/GND
  565. connections in the chip implementation is that the autogenerated layout
  566. is portable between TOPxxxx programmers and it is much easier to implement.
  567. You do not have to search for a chip position in the ZIF socket that fits
  568. the device constraints.
  569. The autogenerator will do it for you.
  570. \end_layout
  571. \begin_layout Standard
  572. The chip interface of the autogenerator is embedded into
  573. \begin_inset Quotes eld
  574. \end_inset
  575. class Chip
  576. \begin_inset Quotes erd
  577. \end_inset
  578. .
  579. So you don't have to work with
  580. \begin_inset Quotes eld
  581. \end_inset
  582. class LayoutGenerator
  583. \begin_inset Quotes erd
  584. \end_inset
  585. directly.
  586. You'll do it through
  587. \begin_inset Quotes eld
  588. \end_inset
  589. class Chip
  590. \begin_inset Quotes erd
  591. \end_inset
  592. instead.
  593. So let's look at
  594. \begin_inset Quotes eld
  595. \end_inset
  596. class Chip
  597. \begin_inset Quotes erd
  598. \end_inset
  599. s autogenerator interface.
  600. \end_layout
  601. \begin_layout Standard
  602. The constructor (__init__()) has some autogenerator related parameters:
  603. \end_layout
  604. \begin_layout Description
  605. chipPackage This parameter is a string identifying the package type of the
  606. DUT chip.
  607. It is something like
  608. \begin_inset Quotes eld
  609. \end_inset
  610. DIP28
  611. \begin_inset Quotes erd
  612. \end_inset
  613. or
  614. \begin_inset Quotes eld
  615. \end_inset
  616. DIP40
  617. \begin_inset Quotes erd
  618. \end_inset
  619. , etc...
  620. .
  621. If this parameter is passed to the constructor, the autogenerator is enabled.
  622. \end_layout
  623. \begin_layout Description
  624. chipPinVCC This parameter is an integer specifying the VCC pin on the chip
  625. package.
  626. Note that it specifies the VCC pin on the chip package and _not_ on the
  627. ZIF socket.
  628. So if your chip datasheet tells you that VCC is on pin 8, you pass an 8
  629. here.
  630. \end_layout
  631. \begin_layout Description
  632. chipPinsVPP This parameter is an integer or a list of integers specifying
  633. the VPP pin(s) on the chip package.
  634. Note that it specifies the VPP pin on the chip package and _not_ on the
  635. ZIF socket.
  636. So if your chip datasheet tells you that VPP is on pin 1, you pass a 1
  637. here.
  638. If your chip needs multiple VPP voltages, just pass a list of pins.
  639. Specify all possible VPP pins here.
  640. Which pin is actually activated is decided later in applyVPP().
  641. \end_layout
  642. \begin_layout Description
  643. chipPinGND This parameter is an integer specifying the GND pin on the chip
  644. package.
  645. Note that it specifies the GND pin on the chip package and _not_ on the
  646. ZIF socket.
  647. So if your chip datasheet tells you that GND is on pin 5, you pass a 5
  648. here.
  649. \end_layout
  650. \begin_layout Standard
  651. After passing all parameters to the
  652. \begin_inset Quotes eld
  653. \end_inset
  654. class Chip
  655. \begin_inset Quotes erd
  656. \end_inset
  657. constructor, the autogenerator is initialized and ready to be used.
  658. The following
  659. \begin_inset Quotes eld
  660. \end_inset
  661. class Chip
  662. \begin_inset Quotes erd
  663. \end_inset
  664. methods can be used to enable or disable a layout:
  665. \end_layout
  666. \begin_layout Description
  667. applyVCC(on) This method enables or disables (depending on the
  668. \begin_inset Quotes eld
  669. \end_inset
  670. on
  671. \begin_inset Quotes erd
  672. \end_inset
  673. parameter) the VCC layout.
  674. Enabling the layout means that the VCC pin will be actively driven by the
  675. configured VCC voltage.
  676. Disabling the layout will tristate the driver.
  677. \end_layout
  678. \begin_layout Description
  679. applyVPP(on,packagePinsToTurnOn) This method enables or disables (depending
  680. on the
  681. \begin_inset Quotes eld
  682. \end_inset
  683. on
  684. \begin_inset Quotes erd
  685. \end_inset
  686. parameter) the VPP layout.
  687. Enabling the layout means that the VPP pins will be actively driven by
  688. the configured VPP voltage.
  689. Disabling the layout will tristate the driver.
  690. The first parameter
  691. \begin_inset Quotes eld
  692. \end_inset
  693. on
  694. \begin_inset Quotes erd
  695. \end_inset
  696. is a boolean to turn ON or OFF the VPP layout.
  697. The second parameter is an optional list of package-pin-numbers specifying
  698. which VPP is turned on.
  699. If the second parameter is not passed, all possible VPPs that were specified
  700. in the constructor are turned on.
  701. The second parameter is unused, if
  702. \begin_inset Quotes eld
  703. \end_inset
  704. on=False
  705. \begin_inset Quotes erd
  706. \end_inset
  707. .
  708. \end_layout
  709. \begin_layout Description
  710. applyGND(on) This method enables or disables (depending on the
  711. \begin_inset Quotes eld
  712. \end_inset
  713. on
  714. \begin_inset Quotes erd
  715. \end_inset
  716. parameter) the GND layout.
  717. Enabling the layout means that the GND pins will be actively driven by
  718. GND.
  719. Disabling the layout will tristate the driver.
  720. \end_layout
  721. \end_body
  722. \end_document