#732 Missing serial controller drivers

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opened 7 months ago by swiftgeek · 0 comments

We don't have actual drivers for serial in:

  • coreboot
  • grub
  • linux

This leads to falling back to legacy 16550A interface, legacy since 1995

Vendor firmware exposes it as PNP0501, but that's not nearly enough to reliably identify it.

Affected devices:

  • PC87392 (x60)
  • WPCN384U (x400)
  • WPCN385L (x200/t)
  • W83667HG-A (KCMA-D8, KGPE-D16)

For National Semiconductors parts (and derivatives) PC87108 datasheet can be used for reference, and it appears to be a probable introduction of said controller (1995), with first SuperIOs incorporating it next year (PC87308/PC87338)

Previous upstreaming attemps by Pavel Machek (1998-2000):

Original attempt on win9x (11-Feb-97):

Recent patch series that adds supports for higher baudrates with broadcom 8250:


Location of prescaler register on modern¹ Winbond (Nuvoton) EC/SIO: "CR F0h" :

  • NCT6683D
  • NCT6685D
  • NCT6686D
  • W83667HG

It appears that there is no lock bit here, just "clock source" selection, without legacy automatic fallback like on NSC. This register also has no name, at best it's shortened to CRF0, and bits to SUACLKB1, SUACLKB0

  • SUACLKBx - Select UART A Clock Source Bit x
  • SUBCLKBx - Select UART B Clock Source Bit x
  • SUCCLKBx - Select UART C Clock Source Bit x

w83627ehf kernel module will probably need to be unloaded before setting up UART, to prevent at least some races (they cannot be avoided outside of kernel code)

¹ actually dates back to at least 1998 (W83977ATF)


  • LPC47N207 (D945GCLF) has two additional baud rates: 230400, 460800

Gigabyte board uses IT8718F which only has legacy 16550A interfaces, so the way to debug that those boards would be to use: ne2k / ehci-debug / serial controller on PCI(e)


Reported RS232 drivers (for boards with SIO that can go beyond 115200):

  • ASUS KGPE-D16 - Avanced Analog Circuits (BCD semi) AZ75232 (232GG marking)
  • Thinkpad X200 - None, Plain UART
  • Thinkpad Advanced (Mini) Dock - Internsil (renesas) ICL3243
  • Thinkpad X6 Ultrabase - Maxim MAX3243
  • Intel D945GCLF2 - TI GD75232 (blurry picture, no confidence)

Coreboot can account for different reference clock set:


National Semi hacky solution, from linux, utilizing lock bit and 16 level FIFO (tested at 1.5Mbaud) [those are not actual commands and assume serial port ttyS0 at 0x3f8]:

stty -F /dev/ttyS0 115200
io_read8 [ 0x3f8 + UART_LCR (0x03) ] → io_read8 0x3FB
io_write8 [ 0x3f8 + UART_LCR (0x03) ] → io_write8 0x3FB 0xE0
io_write8 [ 0x3f8 + UART_EXCR2 (0x04) ] → io_write8 0x3FC 0xB0
io_write8 [ 0x3f8 + UART_LCR (0x03) ] [ /* value from io_read8 */ ]

32 level FIFO would be using 0xB5 instead of 0xB0, but that doesn't seem to be supported or requires special steps to program (reads back 0xB0 after writing 0xB5)

We don't have actual drivers for serial in: * coreboot * grub * linux This leads to falling back to legacy 16550A interface, legacy since 1995 Vendor firmware exposes it as PNP0501, but that's not nearly enough to reliably identify it. Affected devices: * PC87392 (x60) * WPCN384U (x400) * WPCN385L (x200/t) * W83667HG-A (KCMA-D8, KGPE-D16) For National Semiconductors parts (and derivatives) PC87108 datasheet can be used for reference, and it appears to be a probable introduction of said controller (1995), with first SuperIOs incorporating it next year (PC87308/PC87338) * [PC87108 Press release](https://web.archive.org/web/19961019111437/http://www.national.com/news/1995/9511/ps95003.html) * [PC87308/PC87338 Press release](https://web.archive.org/web/19961019114341/http://www.national.com/news/1996/9603/ps96001fir.html) * [Atmel employee confirming that idea](https://www.embeddedrelated.com/showthread/comp.arch.embedded/8794-1.php) Previous upstreaming attemps by Pavel Machek (1998-2000): * [High speed serial ports](http://lkml.iu.edu/hypermail/linux/kernel/9812.1/0007.html) * [Support for hispeed serial ports ](https://www.cs.helsinki.fi/linux/linux-kernel/2001-44/1498.html) Original attempt on win9x (11-Feb-97): * https://web.archive.org/web/19981202091558/http://www1.yk.rim.or.jp:80/~gigo/over115K/index_e.html Recent patch series that adds supports for higher baudrates with broadcom 8250: * [[PATCH v3 0/2] serial: 8250: Add driver for Broadcom UART](https://www.spinics.net/lists/linux-usb/msg208531.html) * [[PATCH v3 1/2] dt-bindings: Add support for the Broadcom UART driver](https://www.spinics.net/lists/linux-usb/msg208532.html) * [[PATCH v3 2/2] serial: 8250: Add new 8250-core based Broadcom STB driver](https://www.spinics.net/lists/linux-usb/msg208533.html) ------------- Location of prescaler register on ~~modern~~¹ Winbond (Nuvoton) EC/SIO: "CR F0h" : * NCT6683D * NCT6685D * NCT6686D * W83667HG It appears that there is no lock bit here, just "clock source" selection, without legacy automatic fallback like on NSC. This register also has no name, at best it's shortened to CRF0, and bits to SUACLKB1, SUACLKB0 * SUACLKBx - Select UART A Clock Source Bit x * SUBCLKBx - Select UART B Clock Source Bit x * SUCCLKBx - Select UART C Clock Source Bit x [w83627ehf kernel module](https://www.kernel.org/doc/html/latest/hwmon/w83627ehf.html) will probably need to be unloaded before setting up UART, to prevent at least some races (they cannot be avoided outside of kernel code) ¹ actually dates back to at least 1998 (W83977ATF) ------------- * LPC47N207 (D945GCLF) has two additional baud rates: 230400, 460800 ------------- Gigabyte board uses IT8718F which only has legacy 16550A interfaces, so the way to debug that those boards would be to use: ne2k / ehci-debug / serial controller on PCI(e) ------------- Reported RS232 drivers (for boards with SIO that can go beyond 115200): * ASUS KGPE-D16 - Avanced Analog Circuits (BCD semi) AZ75232 (232GG marking) * Thinkpad X200 - None, Plain UART * Thinkpad Advanced (Mini) Dock - Internsil (renesas) ICL3243 * Thinkpad X6 Ultrabase - Maxim MAX3243 * Intel D945GCLF2 - TI GD75232 (blurry picture, no confidence) ------------- Coreboot can account for different reference clock set: * see https://review.coreboot.org/c/memtest86plus/+/37060 * lb_serial, input_hertz * uart_fill_lb, uart_platform_refclk() * UART_OVERRIDE_INPUT_CLOCK_DIVIDER * https://review.coreboot.org/c/coreboot/+/14611 * `This works around ROMCC not supporting weak routines.` * TODO: write PRESL setting support via uart_platform_refclk() in `superio/nsc/pc87382/superio.c`, though poking legacy baudrate bank will reset PRESL. So uart8250_init would need to use different bank somehow, or init overriden ------------- National Semi hacky solution, from linux, utilizing lock bit and 16 level FIFO (tested at 1.5Mbaud) [those are not actual commands and assume serial port `ttyS0` at `0x3f8`]: ``` stty -F /dev/ttyS0 115200 io_read8 [ 0x3f8 + UART_LCR (0x03) ] → io_read8 0x3FB io_write8 [ 0x3f8 + UART_LCR (0x03) ] → io_write8 0x3FB 0xE0 io_write8 [ 0x3f8 + UART_EXCR2 (0x04) ] → io_write8 0x3FC 0xB0 io_write8 [ 0x3f8 + UART_LCR (0x03) ] [ /* value from io_read8 */ ] ``` 32 level FIFO would be using `0xB5` instead of `0xB0`, but that doesn't seem to be supported or requires special steps to program (reads back `0xB0` after writing `0xB5`)
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