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- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
- library work;
- use work.common.all;
- use work.wishbone_types.all;
- entity core is
- generic (
- SIM : boolean := false;
- DISABLE_FLATTEN : boolean := false;
- EX1_BYPASS : boolean := true;
- HAS_FPU : boolean := true;
- HAS_BTC : boolean := true;
- RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
- ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
- LOG_LENGTH : natural := 512
- );
- port (
- clk : in std_ulogic;
- rst : in std_ulogic;
- -- Alternate reset (0xffff0000) for use by DRAM init fw
- alt_reset : in std_ulogic;
- -- Wishbone interface
- wishbone_insn_in : in wishbone_slave_out;
- wishbone_insn_out : out wishbone_master_out;
- wishbone_data_in : in wishbone_slave_out;
- wishbone_data_out : out wishbone_master_out;
- dmi_addr : in std_ulogic_vector(3 downto 0);
- dmi_din : in std_ulogic_vector(63 downto 0);
- dmi_dout : out std_ulogic_vector(63 downto 0);
- dmi_req : in std_ulogic;
- dmi_wr : in std_ulogic;
- dmi_ack : out std_ulogic;
- ext_irq : in std_ulogic;
- terminated_out : out std_logic;
- -- for verilator debugging
- nia_req: out std_ulogic;
- nia: out std_ulogic_vector(63 downto 0);
- msr_o: out std_ulogic_vector(63 downto 0);
- insn: out std_ulogic_vector(31 downto 0);
- ldst_req: out std_ulogic;
- ldst_addr: out std_ulogic_vector(63 downto 0)
- );
- end core;
- architecture behave of core is
- begin
- end behave;
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