msm-hsusb.txt 4.0 KB

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  1. MSM SoC HSUSB controllers
  2. EHCI
  3. Required properties:
  4. - compatible: Should contain "qcom,ehci-host"
  5. - regs: offset and length of the register set in the memory map
  6. - usb-phy: phandle for the PHY device
  7. Example EHCI controller device node:
  8. ehci: ehci@f9a55000 {
  9. compatible = "qcom,ehci-host";
  10. reg = <0xf9a55000 0x400>;
  11. usb-phy = <&usb_otg>;
  12. };
  13. USB PHY with optional OTG:
  14. Required properties:
  15. - compatible: Should contain:
  16. "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
  17. "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
  18. - regs: Offset and length of the register set in the memory map
  19. - interrupts: interrupt-specifier for the OTG interrupt.
  20. - clocks: A list of phandle + clock-specifier pairs for the
  21. clocks listed in clock-names
  22. - clock-names: Should contain the following:
  23. "phy" USB PHY reference clock
  24. "core" Protocol engine clock
  25. "iface" Interface bus clock
  26. "alt_core" Protocol engine clock for targets with asynchronous
  27. reset methodology. (optional)
  28. - vdccx-supply: phandle to the regulator for the vdd supply for
  29. digital circuit operation.
  30. - v1p8-supply: phandle to the regulator for the 1.8V supply
  31. - v3p3-supply: phandle to the regulator for the 3.3V supply
  32. - resets: A list of phandle + reset-specifier pairs for the
  33. resets listed in reset-names
  34. - reset-names: Should contain the following:
  35. "phy" USB PHY controller reset
  36. "link" USB LINK controller reset
  37. - qcom,otg-control: OTG control (VBUS and ID notifications) can be one of
  38. 1 - PHY control
  39. 2 - PMIC control
  40. Optional properties:
  41. - dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
  42. - qcom,phy-init-sequence: PHY configuration sequence values. This is related to Device
  43. Mode Eye Diagram test. Start address at which these values will be
  44. written is ULPI_EXT_VENDOR_SPECIFIC. Value of -1 is reserved as
  45. "do not overwrite default value at this address".
  46. For example: qcom,phy-init-sequence = < -1 0x63 >;
  47. Will update only value at address ULPI_EXT_VENDOR_SPECIFIC + 1.
  48. - qcom,phy-num: Select number of pyco-phy to use, can be one of
  49. 0 - PHY one, default
  50. 1 - Second PHY
  51. Some platforms may have configuration to allow USB
  52. controller work with any of the two HSPHYs present.
  53. - qcom,vdd-levels: This property must be a list of three integer values
  54. (no, min, max) where each value represents either a voltage
  55. in microvolts or a value corresponding to voltage corner.
  56. - qcom,manual-pullup: If present, vbus is not routed to USB controller/phy
  57. and controller driver therefore enables pull-up explicitly
  58. before starting controller using usbcmd run/stop bit.
  59. - extcon: phandles to external connector devices. First phandle
  60. should point to external connector, which provide "USB"
  61. cable events, the second should point to external connector
  62. device, which provide "USB-HOST" cable events. If one of
  63. the external connector devices is not required empty <0>
  64. phandle should be specified.
  65. Example HSUSB OTG controller device node:
  66. usb@f9a55000 {
  67. compatible = "qcom,usb-otg-snps";
  68. reg = <0xf9a55000 0x400>;
  69. interrupts = <0 134 0>;
  70. dr_mode = "peripheral";
  71. clocks = <&gcc GCC_XO_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>,
  72. <&gcc GCC_USB_HS_AHB_CLK>;
  73. clock-names = "phy", "core", "iface";
  74. vddcx-supply = <&pm8841_s2_corner>;
  75. v1p8-supply = <&pm8941_l6>;
  76. v3p3-supply = <&pm8941_l24>;
  77. resets = <&gcc GCC_USB2A_PHY_BCR>, <&gcc GCC_USB_HS_BCR>;
  78. reset-names = "phy", "link";
  79. qcom,otg-control = <1>;
  80. qcom,phy-init-sequence = < -1 0x63 >;
  81. qcom,vdd-levels = <1 5 7>;
  82. };