intel8x0.c 90 KB

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  1. /*
  2. * ALSA driver for Intel ICH (i8x0) chipsets
  3. *
  4. * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
  5. *
  6. *
  7. * This code also contains alpha support for SiS 735 chipsets provided
  8. * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
  9. * for SiS735, so the code is not fully functional.
  10. *
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2 of the License, or
  15. * (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  25. *
  26. */
  27. #include <asm/io.h>
  28. #include <linux/delay.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/init.h>
  31. #include <linux/pci.h>
  32. #include <linux/slab.h>
  33. #include <linux/moduleparam.h>
  34. #include <sound/core.h>
  35. #include <sound/pcm.h>
  36. #include <sound/ac97_codec.h>
  37. #include <sound/info.h>
  38. #include <sound/initval.h>
  39. /* for 440MX workaround */
  40. #include <asm/pgtable.h>
  41. #include <asm/cacheflush.h>
  42. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  43. MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
  44. MODULE_LICENSE("GPL");
  45. MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
  46. "{Intel,82901AB-ICH0},"
  47. "{Intel,82801BA-ICH2},"
  48. "{Intel,82801CA-ICH3},"
  49. "{Intel,82801DB-ICH4},"
  50. "{Intel,ICH5},"
  51. "{Intel,ICH6},"
  52. "{Intel,ICH7},"
  53. "{Intel,6300ESB},"
  54. "{Intel,ESB2},"
  55. "{Intel,MX440},"
  56. "{SiS,SI7012},"
  57. "{NVidia,nForce Audio},"
  58. "{NVidia,nForce2 Audio},"
  59. "{NVidia,nForce3 Audio},"
  60. "{NVidia,MCP04},"
  61. "{NVidia,MCP501},"
  62. "{NVidia,CK804},"
  63. "{NVidia,CK8},"
  64. "{NVidia,CK8S},"
  65. "{AMD,AMD768},"
  66. "{AMD,AMD8111},"
  67. "{ALI,M5455}}");
  68. static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
  69. static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
  70. static int ac97_clock;
  71. static char *ac97_quirk;
  72. static int buggy_semaphore;
  73. static int buggy_irq = -1; /* auto-check */
  74. static int xbox;
  75. static int spdif_aclink = -1;
  76. module_param(index, int, 0444);
  77. MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
  78. module_param(id, charp, 0444);
  79. MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
  80. module_param(ac97_clock, int, 0444);
  81. MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
  82. module_param(ac97_quirk, charp, 0444);
  83. MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
  84. module_param(buggy_semaphore, bool, 0444);
  85. MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
  86. module_param(buggy_irq, bool, 0444);
  87. MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
  88. module_param(xbox, bool, 0444);
  89. MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
  90. module_param(spdif_aclink, int, 0444);
  91. MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
  92. /* just for backward compatibility */
  93. static int enable;
  94. module_param(enable, bool, 0444);
  95. static int joystick;
  96. module_param(joystick, int, 0444);
  97. /*
  98. * Direct registers
  99. */
  100. enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
  101. #define ICHREG(x) ICH_REG_##x
  102. #define DEFINE_REGSET(name,base) \
  103. enum { \
  104. ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
  105. ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
  106. ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
  107. ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
  108. ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
  109. ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
  110. ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
  111. };
  112. /* busmaster blocks */
  113. DEFINE_REGSET(OFF, 0); /* offset */
  114. DEFINE_REGSET(PI, 0x00); /* PCM in */
  115. DEFINE_REGSET(PO, 0x10); /* PCM out */
  116. DEFINE_REGSET(MC, 0x20); /* Mic in */
  117. /* ICH4 busmaster blocks */
  118. DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
  119. DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
  120. DEFINE_REGSET(SP, 0x60); /* SPDIF out */
  121. /* values for each busmaster block */
  122. /* LVI */
  123. #define ICH_REG_LVI_MASK 0x1f
  124. /* SR */
  125. #define ICH_FIFOE 0x10 /* FIFO error */
  126. #define ICH_BCIS 0x08 /* buffer completion interrupt status */
  127. #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
  128. #define ICH_CELV 0x02 /* current equals last valid */
  129. #define ICH_DCH 0x01 /* DMA controller halted */
  130. /* PIV */
  131. #define ICH_REG_PIV_MASK 0x1f /* mask */
  132. /* CR */
  133. #define ICH_IOCE 0x10 /* interrupt on completion enable */
  134. #define ICH_FEIE 0x08 /* fifo error interrupt enable */
  135. #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
  136. #define ICH_RESETREGS 0x02 /* reset busmaster registers */
  137. #define ICH_STARTBM 0x01 /* start busmaster operation */
  138. /* global block */
  139. #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
  140. #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
  141. #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
  142. #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
  143. #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
  144. #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
  145. #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
  146. #define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
  147. #define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
  148. #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
  149. #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
  150. #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
  151. #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
  152. #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
  153. #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
  154. #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
  155. #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
  156. #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
  157. #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
  158. #define ICH_ACLINK 0x00000008 /* AClink shut off */
  159. #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
  160. #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
  161. #define ICH_GIE 0x00000001 /* GPI interrupt enable */
  162. #define ICH_REG_GLOB_STA 0x30 /* dword - global status */
  163. #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
  164. #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
  165. #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
  166. #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
  167. #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
  168. #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
  169. #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
  170. #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
  171. #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
  172. #define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
  173. #define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
  174. #define ICH_MD3 0x00020000 /* modem power down semaphore */
  175. #define ICH_AD3 0x00010000 /* audio power down semaphore */
  176. #define ICH_RCS 0x00008000 /* read completion status */
  177. #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
  178. #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
  179. #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
  180. #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
  181. #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
  182. #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
  183. #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
  184. #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
  185. #define ICH_POINT 0x00000040 /* playback interrupt */
  186. #define ICH_PIINT 0x00000020 /* capture interrupt */
  187. #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
  188. #define ICH_MOINT 0x00000004 /* modem playback interrupt */
  189. #define ICH_MIINT 0x00000002 /* modem capture interrupt */
  190. #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
  191. #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
  192. #define ICH_CAS 0x01 /* codec access semaphore */
  193. #define ICH_REG_SDM 0x80
  194. #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
  195. #define ICH_DI2L_SHIFT 6
  196. #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
  197. #define ICH_DI1L_SHIFT 4
  198. #define ICH_SE 0x00000008 /* steer enable */
  199. #define ICH_LDI_MASK 0x00000003 /* last codec read data input */
  200. #define ICH_MAX_FRAGS 32 /* max hw frags */
  201. /*
  202. * registers for Ali5455
  203. */
  204. /* ALi 5455 busmaster blocks */
  205. DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
  206. DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
  207. DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
  208. DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
  209. DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
  210. DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
  211. DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
  212. DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
  213. DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
  214. DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
  215. DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
  216. enum {
  217. ICH_REG_ALI_SCR = 0x00, /* System Control Register */
  218. ICH_REG_ALI_SSR = 0x04, /* System Status Register */
  219. ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
  220. ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
  221. ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
  222. ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
  223. ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
  224. ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
  225. ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
  226. ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
  227. ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
  228. ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
  229. ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
  230. ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
  231. ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
  232. ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
  233. ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
  234. ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
  235. ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
  236. ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
  237. ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
  238. };
  239. #define ALI_CAS_SEM_BUSY 0x80000000
  240. #define ALI_CPR_ADDR_SECONDARY 0x100
  241. #define ALI_CPR_ADDR_READ 0x80
  242. #define ALI_CSPSR_CODEC_READY 0x08
  243. #define ALI_CSPSR_READ_OK 0x02
  244. #define ALI_CSPSR_WRITE_OK 0x01
  245. /* interrupts for the whole chip by interrupt status register finish */
  246. #define ALI_INT_MICIN2 (1<<26)
  247. #define ALI_INT_PCMIN2 (1<<25)
  248. #define ALI_INT_I2SIN (1<<24)
  249. #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
  250. #define ALI_INT_SPDIFIN (1<<22)
  251. #define ALI_INT_LFEOUT (1<<21)
  252. #define ALI_INT_CENTEROUT (1<<20)
  253. #define ALI_INT_CODECSPDIFOUT (1<<19)
  254. #define ALI_INT_MICIN (1<<18)
  255. #define ALI_INT_PCMOUT (1<<17)
  256. #define ALI_INT_PCMIN (1<<16)
  257. #define ALI_INT_CPRAIS (1<<7) /* command port available */
  258. #define ALI_INT_SPRAIS (1<<5) /* status port available */
  259. #define ALI_INT_GPIO (1<<1)
  260. #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
  261. ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
  262. #define ICH_ALI_SC_RESET (1<<31) /* master reset */
  263. #define ICH_ALI_SC_AC97_DBL (1<<30)
  264. #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
  265. #define ICH_ALI_SC_IN_BITS (3<<18)
  266. #define ICH_ALI_SC_OUT_BITS (3<<16)
  267. #define ICH_ALI_SC_6CH_CFG (3<<14)
  268. #define ICH_ALI_SC_PCM_4 (1<<8)
  269. #define ICH_ALI_SC_PCM_6 (2<<8)
  270. #define ICH_ALI_SC_PCM_246_MASK (3<<8)
  271. #define ICH_ALI_SS_SEC_ID (3<<5)
  272. #define ICH_ALI_SS_PRI_ID (3<<3)
  273. #define ICH_ALI_IF_AC97SP (1<<21)
  274. #define ICH_ALI_IF_MC (1<<20)
  275. #define ICH_ALI_IF_PI (1<<19)
  276. #define ICH_ALI_IF_MC2 (1<<18)
  277. #define ICH_ALI_IF_PI2 (1<<17)
  278. #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
  279. #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
  280. #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
  281. #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
  282. #define ICH_ALI_IF_PO_SPDF (1<<3)
  283. #define ICH_ALI_IF_PO (1<<1)
  284. /*
  285. *
  286. */
  287. enum {
  288. ICHD_PCMIN,
  289. ICHD_PCMOUT,
  290. ICHD_MIC,
  291. ICHD_MIC2,
  292. ICHD_PCM2IN,
  293. ICHD_SPBAR,
  294. ICHD_LAST = ICHD_SPBAR
  295. };
  296. enum {
  297. NVD_PCMIN,
  298. NVD_PCMOUT,
  299. NVD_MIC,
  300. NVD_SPBAR,
  301. NVD_LAST = NVD_SPBAR
  302. };
  303. enum {
  304. ALID_PCMIN,
  305. ALID_PCMOUT,
  306. ALID_MIC,
  307. ALID_AC97SPDIFOUT,
  308. ALID_SPDIFIN,
  309. ALID_SPDIFOUT,
  310. ALID_LAST = ALID_SPDIFOUT
  311. };
  312. #define get_ichdev(substream) (substream->runtime->private_data)
  313. struct ichdev {
  314. unsigned int ichd; /* ich device number */
  315. unsigned long reg_offset; /* offset to bmaddr */
  316. u32 *bdbar; /* CPU address (32bit) */
  317. unsigned int bdbar_addr; /* PCI bus address (32bit) */
  318. struct snd_pcm_substream *substream;
  319. unsigned int physbuf; /* physical address (32bit) */
  320. unsigned int size;
  321. unsigned int fragsize;
  322. unsigned int fragsize1;
  323. unsigned int position;
  324. unsigned int pos_shift;
  325. unsigned int last_pos;
  326. int frags;
  327. int lvi;
  328. int lvi_frag;
  329. int civ;
  330. int ack;
  331. int ack_reload;
  332. unsigned int ack_bit;
  333. unsigned int roff_sr;
  334. unsigned int roff_picb;
  335. unsigned int int_sta_mask; /* interrupt status mask */
  336. unsigned int ali_slot; /* ALI DMA slot */
  337. struct ac97_pcm *pcm;
  338. int pcm_open_flag;
  339. unsigned int page_attr_changed: 1;
  340. unsigned int suspended: 1;
  341. };
  342. struct intel8x0 {
  343. unsigned int device_type;
  344. int irq;
  345. void __iomem *addr;
  346. void __iomem *bmaddr;
  347. struct pci_dev *pci;
  348. struct snd_card *card;
  349. int pcm_devs;
  350. struct snd_pcm *pcm[6];
  351. struct ichdev ichd[6];
  352. unsigned multi4: 1,
  353. multi6: 1,
  354. multi8 :1,
  355. dra: 1,
  356. smp20bit: 1;
  357. unsigned in_ac97_init: 1,
  358. in_sdin_init: 1;
  359. unsigned in_measurement: 1; /* during ac97 clock measurement */
  360. unsigned fix_nocache: 1; /* workaround for 440MX */
  361. unsigned buggy_irq: 1; /* workaround for buggy mobos */
  362. unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
  363. unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
  364. int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
  365. unsigned int sdm_saved; /* SDM reg value */
  366. struct snd_ac97_bus *ac97_bus;
  367. struct snd_ac97 *ac97[3];
  368. unsigned int ac97_sdin[3];
  369. unsigned int max_codecs, ncodecs;
  370. unsigned int *codec_bit;
  371. unsigned int codec_isr_bits;
  372. unsigned int codec_ready_bits;
  373. spinlock_t reg_lock;
  374. u32 bdbars_count;
  375. struct snd_dma_buffer bdbars;
  376. u32 int_sta_reg; /* interrupt status register */
  377. u32 int_sta_mask; /* interrupt status mask */
  378. };
  379. static struct pci_device_id snd_intel8x0_ids[] = {
  380. { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */
  381. { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */
  382. { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */
  383. { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */
  384. { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
  385. { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
  386. { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
  387. { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
  388. { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
  389. { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
  390. { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */
  391. { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */
  392. { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
  393. { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
  394. { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
  395. { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
  396. { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
  397. { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
  398. { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
  399. { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
  400. { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */
  401. { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */
  402. { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
  403. { 0, }
  404. };
  405. MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
  406. /*
  407. * Lowlevel I/O - busmaster
  408. */
  409. static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
  410. {
  411. return ioread8(chip->bmaddr + offset);
  412. }
  413. static inline u16 igetword(struct intel8x0 *chip, u32 offset)
  414. {
  415. return ioread16(chip->bmaddr + offset);
  416. }
  417. static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
  418. {
  419. return ioread32(chip->bmaddr + offset);
  420. }
  421. static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
  422. {
  423. iowrite8(val, chip->bmaddr + offset);
  424. }
  425. static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
  426. {
  427. iowrite16(val, chip->bmaddr + offset);
  428. }
  429. static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
  430. {
  431. iowrite32(val, chip->bmaddr + offset);
  432. }
  433. /*
  434. * Lowlevel I/O - AC'97 registers
  435. */
  436. static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
  437. {
  438. return ioread16(chip->addr + offset);
  439. }
  440. static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
  441. {
  442. iowrite16(val, chip->addr + offset);
  443. }
  444. /*
  445. * Basic I/O
  446. */
  447. /*
  448. * access to AC97 codec via normal i/o (for ICH and SIS7012)
  449. */
  450. static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
  451. {
  452. int time;
  453. if (codec > 2)
  454. return -EIO;
  455. if (chip->in_sdin_init) {
  456. /* we don't know the ready bit assignment at the moment */
  457. /* so we check any */
  458. codec = chip->codec_isr_bits;
  459. } else {
  460. codec = chip->codec_bit[chip->ac97_sdin[codec]];
  461. }
  462. /* codec ready ? */
  463. if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
  464. return -EIO;
  465. if (chip->buggy_semaphore)
  466. return 0; /* just ignore ... */
  467. /* Anyone holding a semaphore for 1 msec should be shot... */
  468. time = 100;
  469. do {
  470. if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
  471. return 0;
  472. udelay(10);
  473. } while (time--);
  474. /* access to some forbidden (non existant) ac97 registers will not
  475. * reset the semaphore. So even if you don't get the semaphore, still
  476. * continue the access. We don't need the semaphore anyway. */
  477. snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
  478. igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
  479. iagetword(chip, 0); /* clear semaphore flag */
  480. /* I don't care about the semaphore */
  481. return -EBUSY;
  482. }
  483. static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
  484. unsigned short reg,
  485. unsigned short val)
  486. {
  487. struct intel8x0 *chip = ac97->private_data;
  488. if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
  489. if (! chip->in_ac97_init)
  490. snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
  491. }
  492. iaputword(chip, reg + ac97->num * 0x80, val);
  493. }
  494. static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
  495. unsigned short reg)
  496. {
  497. struct intel8x0 *chip = ac97->private_data;
  498. unsigned short res;
  499. unsigned int tmp;
  500. if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
  501. if (! chip->in_ac97_init)
  502. snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
  503. res = 0xffff;
  504. } else {
  505. res = iagetword(chip, reg + ac97->num * 0x80);
  506. if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
  507. /* reset RCS and preserve other R/WC bits */
  508. iputdword(chip, ICHREG(GLOB_STA), tmp &
  509. ~(chip->codec_ready_bits | ICH_GSCI));
  510. if (! chip->in_ac97_init)
  511. snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
  512. res = 0xffff;
  513. }
  514. }
  515. return res;
  516. }
  517. static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
  518. unsigned int codec)
  519. {
  520. unsigned int tmp;
  521. if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
  522. iagetword(chip, codec * 0x80);
  523. if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
  524. /* reset RCS and preserve other R/WC bits */
  525. iputdword(chip, ICHREG(GLOB_STA), tmp &
  526. ~(chip->codec_ready_bits | ICH_GSCI));
  527. }
  528. }
  529. }
  530. /*
  531. * access to AC97 for Ali5455
  532. */
  533. static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
  534. {
  535. int count = 0;
  536. for (count = 0; count < 0x7f; count++) {
  537. int val = igetbyte(chip, ICHREG(ALI_CSPSR));
  538. if (val & mask)
  539. return 0;
  540. }
  541. if (! chip->in_ac97_init)
  542. snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
  543. return -EBUSY;
  544. }
  545. static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
  546. {
  547. int time = 100;
  548. if (chip->buggy_semaphore)
  549. return 0; /* just ignore ... */
  550. while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
  551. udelay(1);
  552. if (! time && ! chip->in_ac97_init)
  553. snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
  554. return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
  555. }
  556. static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
  557. {
  558. struct intel8x0 *chip = ac97->private_data;
  559. unsigned short data = 0xffff;
  560. if (snd_intel8x0_ali_codec_semaphore(chip))
  561. goto __err;
  562. reg |= ALI_CPR_ADDR_READ;
  563. if (ac97->num)
  564. reg |= ALI_CPR_ADDR_SECONDARY;
  565. iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
  566. if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
  567. goto __err;
  568. data = igetword(chip, ICHREG(ALI_SPR));
  569. __err:
  570. return data;
  571. }
  572. static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
  573. unsigned short val)
  574. {
  575. struct intel8x0 *chip = ac97->private_data;
  576. if (snd_intel8x0_ali_codec_semaphore(chip))
  577. return;
  578. iputword(chip, ICHREG(ALI_CPR), val);
  579. if (ac97->num)
  580. reg |= ALI_CPR_ADDR_SECONDARY;
  581. iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
  582. snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
  583. }
  584. /*
  585. * DMA I/O
  586. */
  587. static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
  588. {
  589. int idx;
  590. u32 *bdbar = ichdev->bdbar;
  591. unsigned long port = ichdev->reg_offset;
  592. iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
  593. if (ichdev->size == ichdev->fragsize) {
  594. ichdev->ack_reload = ichdev->ack = 2;
  595. ichdev->fragsize1 = ichdev->fragsize >> 1;
  596. for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
  597. bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
  598. bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
  599. ichdev->fragsize1 >> ichdev->pos_shift);
  600. bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
  601. bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
  602. ichdev->fragsize1 >> ichdev->pos_shift);
  603. }
  604. ichdev->frags = 2;
  605. } else {
  606. ichdev->ack_reload = ichdev->ack = 1;
  607. ichdev->fragsize1 = ichdev->fragsize;
  608. for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
  609. bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
  610. (((idx >> 1) * ichdev->fragsize) %
  611. ichdev->size));
  612. bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
  613. ichdev->fragsize >> ichdev->pos_shift);
  614. #if 0
  615. printk(KERN_DEBUG "bdbar[%i] = 0x%x [0x%x]\n",
  616. idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
  617. #endif
  618. }
  619. ichdev->frags = ichdev->size / ichdev->fragsize;
  620. }
  621. iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
  622. ichdev->civ = 0;
  623. iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
  624. ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
  625. ichdev->position = 0;
  626. #if 0
  627. printk(KERN_DEBUG "lvi_frag = %i, frags = %i, period_size = 0x%x, "
  628. "period_size1 = 0x%x\n",
  629. ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
  630. ichdev->fragsize1);
  631. #endif
  632. /* clear interrupts */
  633. iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
  634. }
  635. #ifdef __i386__
  636. /*
  637. * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
  638. * which aborts PCI busmaster for audio transfer. A workaround is to set
  639. * the pages as non-cached. For details, see the errata in
  640. * http://www.intel.com/design/chipsets/specupdt/245051.htm
  641. */
  642. static void fill_nocache(void *buf, int size, int nocache)
  643. {
  644. size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
  645. if (nocache)
  646. set_pages_uc(virt_to_page(buf), size);
  647. else
  648. set_pages_wb(virt_to_page(buf), size);
  649. }
  650. #else
  651. #define fill_nocache(buf, size, nocache) do { ; } while (0)
  652. #endif
  653. /*
  654. * Interrupt handler
  655. */
  656. static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
  657. {
  658. unsigned long port = ichdev->reg_offset;
  659. unsigned long flags;
  660. int status, civ, i, step;
  661. int ack = 0;
  662. spin_lock_irqsave(&chip->reg_lock, flags);
  663. status = igetbyte(chip, port + ichdev->roff_sr);
  664. civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
  665. if (!(status & ICH_BCIS)) {
  666. step = 0;
  667. } else if (civ == ichdev->civ) {
  668. // snd_printd("civ same %d\n", civ);
  669. step = 1;
  670. ichdev->civ++;
  671. ichdev->civ &= ICH_REG_LVI_MASK;
  672. } else {
  673. step = civ - ichdev->civ;
  674. if (step < 0)
  675. step += ICH_REG_LVI_MASK + 1;
  676. // if (step != 1)
  677. // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
  678. ichdev->civ = civ;
  679. }
  680. ichdev->position += step * ichdev->fragsize1;
  681. if (! chip->in_measurement)
  682. ichdev->position %= ichdev->size;
  683. ichdev->lvi += step;
  684. ichdev->lvi &= ICH_REG_LVI_MASK;
  685. iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
  686. for (i = 0; i < step; i++) {
  687. ichdev->lvi_frag++;
  688. ichdev->lvi_frag %= ichdev->frags;
  689. ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
  690. #if 0
  691. printk(KERN_DEBUG "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, "
  692. "all = 0x%x, 0x%x\n",
  693. ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
  694. ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
  695. inl(port + 4), inb(port + ICH_REG_OFF_CR));
  696. #endif
  697. if (--ichdev->ack == 0) {
  698. ichdev->ack = ichdev->ack_reload;
  699. ack = 1;
  700. }
  701. }
  702. spin_unlock_irqrestore(&chip->reg_lock, flags);
  703. if (ack && ichdev->substream) {
  704. snd_pcm_period_elapsed(ichdev->substream);
  705. }
  706. iputbyte(chip, port + ichdev->roff_sr,
  707. status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
  708. }
  709. static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
  710. {
  711. struct intel8x0 *chip = dev_id;
  712. struct ichdev *ichdev;
  713. unsigned int status;
  714. unsigned int i;
  715. status = igetdword(chip, chip->int_sta_reg);
  716. if (status == 0xffffffff) /* we are not yet resumed */
  717. return IRQ_NONE;
  718. if ((status & chip->int_sta_mask) == 0) {
  719. if (status) {
  720. /* ack */
  721. iputdword(chip, chip->int_sta_reg, status);
  722. if (! chip->buggy_irq)
  723. status = 0;
  724. }
  725. return IRQ_RETVAL(status);
  726. }
  727. for (i = 0; i < chip->bdbars_count; i++) {
  728. ichdev = &chip->ichd[i];
  729. if (status & ichdev->int_sta_mask)
  730. snd_intel8x0_update(chip, ichdev);
  731. }
  732. /* ack them */
  733. iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
  734. return IRQ_HANDLED;
  735. }
  736. /*
  737. * PCM part
  738. */
  739. static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
  740. {
  741. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  742. struct ichdev *ichdev = get_ichdev(substream);
  743. unsigned char val = 0;
  744. unsigned long port = ichdev->reg_offset;
  745. switch (cmd) {
  746. case SNDRV_PCM_TRIGGER_RESUME:
  747. ichdev->suspended = 0;
  748. /* fallthru */
  749. case SNDRV_PCM_TRIGGER_START:
  750. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  751. val = ICH_IOCE | ICH_STARTBM;
  752. ichdev->last_pos = ichdev->position;
  753. break;
  754. case SNDRV_PCM_TRIGGER_SUSPEND:
  755. ichdev->suspended = 1;
  756. /* fallthru */
  757. case SNDRV_PCM_TRIGGER_STOP:
  758. val = 0;
  759. break;
  760. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  761. val = ICH_IOCE;
  762. break;
  763. default:
  764. return -EINVAL;
  765. }
  766. iputbyte(chip, port + ICH_REG_OFF_CR, val);
  767. if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  768. /* wait until DMA stopped */
  769. while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
  770. /* reset whole DMA things */
  771. iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
  772. }
  773. return 0;
  774. }
  775. static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
  776. {
  777. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  778. struct ichdev *ichdev = get_ichdev(substream);
  779. unsigned long port = ichdev->reg_offset;
  780. static int fiforeg[] = {
  781. ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
  782. };
  783. unsigned int val, fifo;
  784. val = igetdword(chip, ICHREG(ALI_DMACR));
  785. switch (cmd) {
  786. case SNDRV_PCM_TRIGGER_RESUME:
  787. ichdev->suspended = 0;
  788. /* fallthru */
  789. case SNDRV_PCM_TRIGGER_START:
  790. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  791. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  792. /* clear FIFO for synchronization of channels */
  793. fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
  794. fifo &= ~(0xff << (ichdev->ali_slot % 4));
  795. fifo |= 0x83 << (ichdev->ali_slot % 4);
  796. iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
  797. }
  798. iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
  799. val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
  800. /* start DMA */
  801. iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
  802. break;
  803. case SNDRV_PCM_TRIGGER_SUSPEND:
  804. ichdev->suspended = 1;
  805. /* fallthru */
  806. case SNDRV_PCM_TRIGGER_STOP:
  807. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  808. /* pause */
  809. iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
  810. iputbyte(chip, port + ICH_REG_OFF_CR, 0);
  811. while (igetbyte(chip, port + ICH_REG_OFF_CR))
  812. ;
  813. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  814. break;
  815. /* reset whole DMA things */
  816. iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
  817. /* clear interrupts */
  818. iputbyte(chip, port + ICH_REG_OFF_SR,
  819. igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
  820. iputdword(chip, ICHREG(ALI_INTERRUPTSR),
  821. igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
  822. break;
  823. default:
  824. return -EINVAL;
  825. }
  826. return 0;
  827. }
  828. static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
  829. struct snd_pcm_hw_params *hw_params)
  830. {
  831. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  832. struct ichdev *ichdev = get_ichdev(substream);
  833. struct snd_pcm_runtime *runtime = substream->runtime;
  834. int dbl = params_rate(hw_params) > 48000;
  835. int err;
  836. if (chip->fix_nocache && ichdev->page_attr_changed) {
  837. fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
  838. ichdev->page_attr_changed = 0;
  839. }
  840. err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  841. if (err < 0)
  842. return err;
  843. if (chip->fix_nocache) {
  844. if (runtime->dma_area && ! ichdev->page_attr_changed) {
  845. fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
  846. ichdev->page_attr_changed = 1;
  847. }
  848. }
  849. if (ichdev->pcm_open_flag) {
  850. snd_ac97_pcm_close(ichdev->pcm);
  851. ichdev->pcm_open_flag = 0;
  852. }
  853. err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
  854. params_channels(hw_params),
  855. ichdev->pcm->r[dbl].slots);
  856. if (err >= 0) {
  857. ichdev->pcm_open_flag = 1;
  858. /* Force SPDIF setting */
  859. if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
  860. snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
  861. params_rate(hw_params));
  862. }
  863. return err;
  864. }
  865. static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
  866. {
  867. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  868. struct ichdev *ichdev = get_ichdev(substream);
  869. if (ichdev->pcm_open_flag) {
  870. snd_ac97_pcm_close(ichdev->pcm);
  871. ichdev->pcm_open_flag = 0;
  872. }
  873. if (chip->fix_nocache && ichdev->page_attr_changed) {
  874. fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
  875. ichdev->page_attr_changed = 0;
  876. }
  877. return snd_pcm_lib_free_pages(substream);
  878. }
  879. static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
  880. struct snd_pcm_runtime *runtime)
  881. {
  882. unsigned int cnt;
  883. int dbl = runtime->rate > 48000;
  884. spin_lock_irq(&chip->reg_lock);
  885. switch (chip->device_type) {
  886. case DEVICE_ALI:
  887. cnt = igetdword(chip, ICHREG(ALI_SCR));
  888. cnt &= ~ICH_ALI_SC_PCM_246_MASK;
  889. if (runtime->channels == 4 || dbl)
  890. cnt |= ICH_ALI_SC_PCM_4;
  891. else if (runtime->channels == 6)
  892. cnt |= ICH_ALI_SC_PCM_6;
  893. iputdword(chip, ICHREG(ALI_SCR), cnt);
  894. break;
  895. case DEVICE_SIS:
  896. cnt = igetdword(chip, ICHREG(GLOB_CNT));
  897. cnt &= ~ICH_SIS_PCM_246_MASK;
  898. if (runtime->channels == 4 || dbl)
  899. cnt |= ICH_SIS_PCM_4;
  900. else if (runtime->channels == 6)
  901. cnt |= ICH_SIS_PCM_6;
  902. iputdword(chip, ICHREG(GLOB_CNT), cnt);
  903. break;
  904. default:
  905. cnt = igetdword(chip, ICHREG(GLOB_CNT));
  906. cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
  907. if (runtime->channels == 4 || dbl)
  908. cnt |= ICH_PCM_4;
  909. else if (runtime->channels == 6)
  910. cnt |= ICH_PCM_6;
  911. else if (runtime->channels == 8)
  912. cnt |= ICH_PCM_8;
  913. if (chip->device_type == DEVICE_NFORCE) {
  914. /* reset to 2ch once to keep the 6 channel data in alignment,
  915. * to start from Front Left always
  916. */
  917. if (cnt & ICH_PCM_246_MASK) {
  918. iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
  919. spin_unlock_irq(&chip->reg_lock);
  920. msleep(50); /* grrr... */
  921. spin_lock_irq(&chip->reg_lock);
  922. }
  923. } else if (chip->device_type == DEVICE_INTEL_ICH4) {
  924. if (runtime->sample_bits > 16)
  925. cnt |= ICH_PCM_20BIT;
  926. }
  927. iputdword(chip, ICHREG(GLOB_CNT), cnt);
  928. break;
  929. }
  930. spin_unlock_irq(&chip->reg_lock);
  931. }
  932. static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
  933. {
  934. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  935. struct snd_pcm_runtime *runtime = substream->runtime;
  936. struct ichdev *ichdev = get_ichdev(substream);
  937. ichdev->physbuf = runtime->dma_addr;
  938. ichdev->size = snd_pcm_lib_buffer_bytes(substream);
  939. ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
  940. if (ichdev->ichd == ICHD_PCMOUT) {
  941. snd_intel8x0_setup_pcm_out(chip, runtime);
  942. if (chip->device_type == DEVICE_INTEL_ICH4)
  943. ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
  944. }
  945. snd_intel8x0_setup_periods(chip, ichdev);
  946. return 0;
  947. }
  948. static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
  949. {
  950. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  951. struct ichdev *ichdev = get_ichdev(substream);
  952. size_t ptr1, ptr;
  953. int civ, timeout = 10;
  954. unsigned int position;
  955. spin_lock(&chip->reg_lock);
  956. do {
  957. civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
  958. ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
  959. position = ichdev->position;
  960. if (ptr1 == 0) {
  961. udelay(10);
  962. continue;
  963. }
  964. if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
  965. ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
  966. break;
  967. } while (timeout--);
  968. ptr = ichdev->last_pos;
  969. if (ptr1 != 0) {
  970. ptr1 <<= ichdev->pos_shift;
  971. ptr = ichdev->fragsize1 - ptr1;
  972. ptr += position;
  973. if (ptr < ichdev->last_pos) {
  974. unsigned int pos_base, last_base;
  975. pos_base = position / ichdev->fragsize1;
  976. last_base = ichdev->last_pos / ichdev->fragsize1;
  977. /* another sanity check; ptr1 can go back to full
  978. * before the base position is updated
  979. */
  980. if (pos_base == last_base)
  981. ptr = ichdev->last_pos;
  982. }
  983. }
  984. ichdev->last_pos = ptr;
  985. spin_unlock(&chip->reg_lock);
  986. if (ptr >= ichdev->size)
  987. return 0;
  988. return bytes_to_frames(substream->runtime, ptr);
  989. }
  990. static struct snd_pcm_hardware snd_intel8x0_stream =
  991. {
  992. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  993. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  994. SNDRV_PCM_INFO_MMAP_VALID |
  995. SNDRV_PCM_INFO_PAUSE |
  996. SNDRV_PCM_INFO_RESUME),
  997. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  998. .rates = SNDRV_PCM_RATE_48000,
  999. .rate_min = 48000,
  1000. .rate_max = 48000,
  1001. .channels_min = 2,
  1002. .channels_max = 2,
  1003. .buffer_bytes_max = 128 * 1024,
  1004. .period_bytes_min = 32,
  1005. .period_bytes_max = 128 * 1024,
  1006. .periods_min = 1,
  1007. .periods_max = 1024,
  1008. .fifo_size = 0,
  1009. };
  1010. static unsigned int channels4[] = {
  1011. 2, 4,
  1012. };
  1013. static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
  1014. .count = ARRAY_SIZE(channels4),
  1015. .list = channels4,
  1016. .mask = 0,
  1017. };
  1018. static unsigned int channels6[] = {
  1019. 2, 4, 6,
  1020. };
  1021. static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
  1022. .count = ARRAY_SIZE(channels6),
  1023. .list = channels6,
  1024. .mask = 0,
  1025. };
  1026. static unsigned int channels8[] = {
  1027. 2, 4, 6, 8,
  1028. };
  1029. static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
  1030. .count = ARRAY_SIZE(channels8),
  1031. .list = channels8,
  1032. .mask = 0,
  1033. };
  1034. static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
  1035. {
  1036. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1037. struct snd_pcm_runtime *runtime = substream->runtime;
  1038. int err;
  1039. ichdev->substream = substream;
  1040. runtime->hw = snd_intel8x0_stream;
  1041. runtime->hw.rates = ichdev->pcm->rates;
  1042. snd_pcm_limit_hw_rates(runtime);
  1043. if (chip->device_type == DEVICE_SIS) {
  1044. runtime->hw.buffer_bytes_max = 64*1024;
  1045. runtime->hw.period_bytes_max = 64*1024;
  1046. }
  1047. if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
  1048. return err;
  1049. runtime->private_data = ichdev;
  1050. return 0;
  1051. }
  1052. static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
  1053. {
  1054. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1055. struct snd_pcm_runtime *runtime = substream->runtime;
  1056. int err;
  1057. err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
  1058. if (err < 0)
  1059. return err;
  1060. if (chip->multi8) {
  1061. runtime->hw.channels_max = 8;
  1062. snd_pcm_hw_constraint_list(runtime, 0,
  1063. SNDRV_PCM_HW_PARAM_CHANNELS,
  1064. &hw_constraints_channels8);
  1065. } else if (chip->multi6) {
  1066. runtime->hw.channels_max = 6;
  1067. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
  1068. &hw_constraints_channels6);
  1069. } else if (chip->multi4) {
  1070. runtime->hw.channels_max = 4;
  1071. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
  1072. &hw_constraints_channels4);
  1073. }
  1074. if (chip->dra) {
  1075. snd_ac97_pcm_double_rate_rules(runtime);
  1076. }
  1077. if (chip->smp20bit) {
  1078. runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
  1079. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
  1080. }
  1081. return 0;
  1082. }
  1083. static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
  1084. {
  1085. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1086. chip->ichd[ICHD_PCMOUT].substream = NULL;
  1087. return 0;
  1088. }
  1089. static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
  1090. {
  1091. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1092. return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
  1093. }
  1094. static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
  1095. {
  1096. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1097. chip->ichd[ICHD_PCMIN].substream = NULL;
  1098. return 0;
  1099. }
  1100. static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
  1101. {
  1102. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1103. return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
  1104. }
  1105. static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
  1106. {
  1107. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1108. chip->ichd[ICHD_MIC].substream = NULL;
  1109. return 0;
  1110. }
  1111. static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
  1112. {
  1113. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1114. return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
  1115. }
  1116. static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
  1117. {
  1118. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1119. chip->ichd[ICHD_MIC2].substream = NULL;
  1120. return 0;
  1121. }
  1122. static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
  1123. {
  1124. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1125. return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
  1126. }
  1127. static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
  1128. {
  1129. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1130. chip->ichd[ICHD_PCM2IN].substream = NULL;
  1131. return 0;
  1132. }
  1133. static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
  1134. {
  1135. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1136. int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
  1137. return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
  1138. }
  1139. static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
  1140. {
  1141. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1142. int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
  1143. chip->ichd[idx].substream = NULL;
  1144. return 0;
  1145. }
  1146. static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
  1147. {
  1148. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1149. unsigned int val;
  1150. spin_lock_irq(&chip->reg_lock);
  1151. val = igetdword(chip, ICHREG(ALI_INTERFACECR));
  1152. val |= ICH_ALI_IF_AC97SP;
  1153. iputdword(chip, ICHREG(ALI_INTERFACECR), val);
  1154. /* also needs to set ALI_SC_CODEC_SPDF correctly */
  1155. spin_unlock_irq(&chip->reg_lock);
  1156. return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
  1157. }
  1158. static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
  1159. {
  1160. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1161. unsigned int val;
  1162. chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
  1163. spin_lock_irq(&chip->reg_lock);
  1164. val = igetdword(chip, ICHREG(ALI_INTERFACECR));
  1165. val &= ~ICH_ALI_IF_AC97SP;
  1166. iputdword(chip, ICHREG(ALI_INTERFACECR), val);
  1167. spin_unlock_irq(&chip->reg_lock);
  1168. return 0;
  1169. }
  1170. #if 0 // NYI
  1171. static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
  1172. {
  1173. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1174. return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
  1175. }
  1176. static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
  1177. {
  1178. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1179. chip->ichd[ALID_SPDIFIN].substream = NULL;
  1180. return 0;
  1181. }
  1182. static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
  1183. {
  1184. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1185. return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
  1186. }
  1187. static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
  1188. {
  1189. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1190. chip->ichd[ALID_SPDIFOUT].substream = NULL;
  1191. return 0;
  1192. }
  1193. #endif
  1194. static struct snd_pcm_ops snd_intel8x0_playback_ops = {
  1195. .open = snd_intel8x0_playback_open,
  1196. .close = snd_intel8x0_playback_close,
  1197. .ioctl = snd_pcm_lib_ioctl,
  1198. .hw_params = snd_intel8x0_hw_params,
  1199. .hw_free = snd_intel8x0_hw_free,
  1200. .prepare = snd_intel8x0_pcm_prepare,
  1201. .trigger = snd_intel8x0_pcm_trigger,
  1202. .pointer = snd_intel8x0_pcm_pointer,
  1203. };
  1204. static struct snd_pcm_ops snd_intel8x0_capture_ops = {
  1205. .open = snd_intel8x0_capture_open,
  1206. .close = snd_intel8x0_capture_close,
  1207. .ioctl = snd_pcm_lib_ioctl,
  1208. .hw_params = snd_intel8x0_hw_params,
  1209. .hw_free = snd_intel8x0_hw_free,
  1210. .prepare = snd_intel8x0_pcm_prepare,
  1211. .trigger = snd_intel8x0_pcm_trigger,
  1212. .pointer = snd_intel8x0_pcm_pointer,
  1213. };
  1214. static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
  1215. .open = snd_intel8x0_mic_open,
  1216. .close = snd_intel8x0_mic_close,
  1217. .ioctl = snd_pcm_lib_ioctl,
  1218. .hw_params = snd_intel8x0_hw_params,
  1219. .hw_free = snd_intel8x0_hw_free,
  1220. .prepare = snd_intel8x0_pcm_prepare,
  1221. .trigger = snd_intel8x0_pcm_trigger,
  1222. .pointer = snd_intel8x0_pcm_pointer,
  1223. };
  1224. static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
  1225. .open = snd_intel8x0_mic2_open,
  1226. .close = snd_intel8x0_mic2_close,
  1227. .ioctl = snd_pcm_lib_ioctl,
  1228. .hw_params = snd_intel8x0_hw_params,
  1229. .hw_free = snd_intel8x0_hw_free,
  1230. .prepare = snd_intel8x0_pcm_prepare,
  1231. .trigger = snd_intel8x0_pcm_trigger,
  1232. .pointer = snd_intel8x0_pcm_pointer,
  1233. };
  1234. static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
  1235. .open = snd_intel8x0_capture2_open,
  1236. .close = snd_intel8x0_capture2_close,
  1237. .ioctl = snd_pcm_lib_ioctl,
  1238. .hw_params = snd_intel8x0_hw_params,
  1239. .hw_free = snd_intel8x0_hw_free,
  1240. .prepare = snd_intel8x0_pcm_prepare,
  1241. .trigger = snd_intel8x0_pcm_trigger,
  1242. .pointer = snd_intel8x0_pcm_pointer,
  1243. };
  1244. static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
  1245. .open = snd_intel8x0_spdif_open,
  1246. .close = snd_intel8x0_spdif_close,
  1247. .ioctl = snd_pcm_lib_ioctl,
  1248. .hw_params = snd_intel8x0_hw_params,
  1249. .hw_free = snd_intel8x0_hw_free,
  1250. .prepare = snd_intel8x0_pcm_prepare,
  1251. .trigger = snd_intel8x0_pcm_trigger,
  1252. .pointer = snd_intel8x0_pcm_pointer,
  1253. };
  1254. static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
  1255. .open = snd_intel8x0_playback_open,
  1256. .close = snd_intel8x0_playback_close,
  1257. .ioctl = snd_pcm_lib_ioctl,
  1258. .hw_params = snd_intel8x0_hw_params,
  1259. .hw_free = snd_intel8x0_hw_free,
  1260. .prepare = snd_intel8x0_pcm_prepare,
  1261. .trigger = snd_intel8x0_ali_trigger,
  1262. .pointer = snd_intel8x0_pcm_pointer,
  1263. };
  1264. static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
  1265. .open = snd_intel8x0_capture_open,
  1266. .close = snd_intel8x0_capture_close,
  1267. .ioctl = snd_pcm_lib_ioctl,
  1268. .hw_params = snd_intel8x0_hw_params,
  1269. .hw_free = snd_intel8x0_hw_free,
  1270. .prepare = snd_intel8x0_pcm_prepare,
  1271. .trigger = snd_intel8x0_ali_trigger,
  1272. .pointer = snd_intel8x0_pcm_pointer,
  1273. };
  1274. static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
  1275. .open = snd_intel8x0_mic_open,
  1276. .close = snd_intel8x0_mic_close,
  1277. .ioctl = snd_pcm_lib_ioctl,
  1278. .hw_params = snd_intel8x0_hw_params,
  1279. .hw_free = snd_intel8x0_hw_free,
  1280. .prepare = snd_intel8x0_pcm_prepare,
  1281. .trigger = snd_intel8x0_ali_trigger,
  1282. .pointer = snd_intel8x0_pcm_pointer,
  1283. };
  1284. static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
  1285. .open = snd_intel8x0_ali_ac97spdifout_open,
  1286. .close = snd_intel8x0_ali_ac97spdifout_close,
  1287. .ioctl = snd_pcm_lib_ioctl,
  1288. .hw_params = snd_intel8x0_hw_params,
  1289. .hw_free = snd_intel8x0_hw_free,
  1290. .prepare = snd_intel8x0_pcm_prepare,
  1291. .trigger = snd_intel8x0_ali_trigger,
  1292. .pointer = snd_intel8x0_pcm_pointer,
  1293. };
  1294. #if 0 // NYI
  1295. static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
  1296. .open = snd_intel8x0_ali_spdifin_open,
  1297. .close = snd_intel8x0_ali_spdifin_close,
  1298. .ioctl = snd_pcm_lib_ioctl,
  1299. .hw_params = snd_intel8x0_hw_params,
  1300. .hw_free = snd_intel8x0_hw_free,
  1301. .prepare = snd_intel8x0_pcm_prepare,
  1302. .trigger = snd_intel8x0_pcm_trigger,
  1303. .pointer = snd_intel8x0_pcm_pointer,
  1304. };
  1305. static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
  1306. .open = snd_intel8x0_ali_spdifout_open,
  1307. .close = snd_intel8x0_ali_spdifout_close,
  1308. .ioctl = snd_pcm_lib_ioctl,
  1309. .hw_params = snd_intel8x0_hw_params,
  1310. .hw_free = snd_intel8x0_hw_free,
  1311. .prepare = snd_intel8x0_pcm_prepare,
  1312. .trigger = snd_intel8x0_pcm_trigger,
  1313. .pointer = snd_intel8x0_pcm_pointer,
  1314. };
  1315. #endif // NYI
  1316. struct ich_pcm_table {
  1317. char *suffix;
  1318. struct snd_pcm_ops *playback_ops;
  1319. struct snd_pcm_ops *capture_ops;
  1320. size_t prealloc_size;
  1321. size_t prealloc_max_size;
  1322. int ac97_idx;
  1323. };
  1324. static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
  1325. struct ich_pcm_table *rec)
  1326. {
  1327. struct snd_pcm *pcm;
  1328. int err;
  1329. char name[32];
  1330. if (rec->suffix)
  1331. sprintf(name, "Intel ICH - %s", rec->suffix);
  1332. else
  1333. strcpy(name, "Intel ICH");
  1334. err = snd_pcm_new(chip->card, name, device,
  1335. rec->playback_ops ? 1 : 0,
  1336. rec->capture_ops ? 1 : 0, &pcm);
  1337. if (err < 0)
  1338. return err;
  1339. if (rec->playback_ops)
  1340. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
  1341. if (rec->capture_ops)
  1342. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
  1343. pcm->private_data = chip;
  1344. pcm->info_flags = 0;
  1345. if (rec->suffix)
  1346. sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
  1347. else
  1348. strcpy(pcm->name, chip->card->shortname);
  1349. chip->pcm[device] = pcm;
  1350. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1351. snd_dma_pci_data(chip->pci),
  1352. rec->prealloc_size, rec->prealloc_max_size);
  1353. return 0;
  1354. }
  1355. static struct ich_pcm_table intel_pcms[] __devinitdata = {
  1356. {
  1357. .playback_ops = &snd_intel8x0_playback_ops,
  1358. .capture_ops = &snd_intel8x0_capture_ops,
  1359. .prealloc_size = 64 * 1024,
  1360. .prealloc_max_size = 128 * 1024,
  1361. },
  1362. {
  1363. .suffix = "MIC ADC",
  1364. .capture_ops = &snd_intel8x0_capture_mic_ops,
  1365. .prealloc_size = 0,
  1366. .prealloc_max_size = 128 * 1024,
  1367. .ac97_idx = ICHD_MIC,
  1368. },
  1369. {
  1370. .suffix = "MIC2 ADC",
  1371. .capture_ops = &snd_intel8x0_capture_mic2_ops,
  1372. .prealloc_size = 0,
  1373. .prealloc_max_size = 128 * 1024,
  1374. .ac97_idx = ICHD_MIC2,
  1375. },
  1376. {
  1377. .suffix = "ADC2",
  1378. .capture_ops = &snd_intel8x0_capture2_ops,
  1379. .prealloc_size = 0,
  1380. .prealloc_max_size = 128 * 1024,
  1381. .ac97_idx = ICHD_PCM2IN,
  1382. },
  1383. {
  1384. .suffix = "IEC958",
  1385. .playback_ops = &snd_intel8x0_spdif_ops,
  1386. .prealloc_size = 64 * 1024,
  1387. .prealloc_max_size = 128 * 1024,
  1388. .ac97_idx = ICHD_SPBAR,
  1389. },
  1390. };
  1391. static struct ich_pcm_table nforce_pcms[] __devinitdata = {
  1392. {
  1393. .playback_ops = &snd_intel8x0_playback_ops,
  1394. .capture_ops = &snd_intel8x0_capture_ops,
  1395. .prealloc_size = 64 * 1024,
  1396. .prealloc_max_size = 128 * 1024,
  1397. },
  1398. {
  1399. .suffix = "MIC ADC",
  1400. .capture_ops = &snd_intel8x0_capture_mic_ops,
  1401. .prealloc_size = 0,
  1402. .prealloc_max_size = 128 * 1024,
  1403. .ac97_idx = NVD_MIC,
  1404. },
  1405. {
  1406. .suffix = "IEC958",
  1407. .playback_ops = &snd_intel8x0_spdif_ops,
  1408. .prealloc_size = 64 * 1024,
  1409. .prealloc_max_size = 128 * 1024,
  1410. .ac97_idx = NVD_SPBAR,
  1411. },
  1412. };
  1413. static struct ich_pcm_table ali_pcms[] __devinitdata = {
  1414. {
  1415. .playback_ops = &snd_intel8x0_ali_playback_ops,
  1416. .capture_ops = &snd_intel8x0_ali_capture_ops,
  1417. .prealloc_size = 64 * 1024,
  1418. .prealloc_max_size = 128 * 1024,
  1419. },
  1420. {
  1421. .suffix = "MIC ADC",
  1422. .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
  1423. .prealloc_size = 0,
  1424. .prealloc_max_size = 128 * 1024,
  1425. .ac97_idx = ALID_MIC,
  1426. },
  1427. {
  1428. .suffix = "IEC958",
  1429. .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
  1430. /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
  1431. .prealloc_size = 64 * 1024,
  1432. .prealloc_max_size = 128 * 1024,
  1433. .ac97_idx = ALID_AC97SPDIFOUT,
  1434. },
  1435. #if 0 // NYI
  1436. {
  1437. .suffix = "HW IEC958",
  1438. .playback_ops = &snd_intel8x0_ali_spdifout_ops,
  1439. .prealloc_size = 64 * 1024,
  1440. .prealloc_max_size = 128 * 1024,
  1441. },
  1442. #endif
  1443. };
  1444. static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
  1445. {
  1446. int i, tblsize, device, err;
  1447. struct ich_pcm_table *tbl, *rec;
  1448. switch (chip->device_type) {
  1449. case DEVICE_INTEL_ICH4:
  1450. tbl = intel_pcms;
  1451. tblsize = ARRAY_SIZE(intel_pcms);
  1452. if (spdif_aclink)
  1453. tblsize--;
  1454. break;
  1455. case DEVICE_NFORCE:
  1456. tbl = nforce_pcms;
  1457. tblsize = ARRAY_SIZE(nforce_pcms);
  1458. if (spdif_aclink)
  1459. tblsize--;
  1460. break;
  1461. case DEVICE_ALI:
  1462. tbl = ali_pcms;
  1463. tblsize = ARRAY_SIZE(ali_pcms);
  1464. break;
  1465. default:
  1466. tbl = intel_pcms;
  1467. tblsize = 2;
  1468. break;
  1469. }
  1470. device = 0;
  1471. for (i = 0; i < tblsize; i++) {
  1472. rec = tbl + i;
  1473. if (i > 0 && rec->ac97_idx) {
  1474. /* activate PCM only when associated AC'97 codec */
  1475. if (! chip->ichd[rec->ac97_idx].pcm)
  1476. continue;
  1477. }
  1478. err = snd_intel8x0_pcm1(chip, device, rec);
  1479. if (err < 0)
  1480. return err;
  1481. device++;
  1482. }
  1483. chip->pcm_devs = device;
  1484. return 0;
  1485. }
  1486. /*
  1487. * Mixer part
  1488. */
  1489. static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
  1490. {
  1491. struct intel8x0 *chip = bus->private_data;
  1492. chip->ac97_bus = NULL;
  1493. }
  1494. static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
  1495. {
  1496. struct intel8x0 *chip = ac97->private_data;
  1497. chip->ac97[ac97->num] = NULL;
  1498. }
  1499. static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
  1500. /* front PCM */
  1501. {
  1502. .exclusive = 1,
  1503. .r = { {
  1504. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  1505. (1 << AC97_SLOT_PCM_RIGHT) |
  1506. (1 << AC97_SLOT_PCM_CENTER) |
  1507. (1 << AC97_SLOT_PCM_SLEFT) |
  1508. (1 << AC97_SLOT_PCM_SRIGHT) |
  1509. (1 << AC97_SLOT_LFE)
  1510. },
  1511. {
  1512. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  1513. (1 << AC97_SLOT_PCM_RIGHT) |
  1514. (1 << AC97_SLOT_PCM_LEFT_0) |
  1515. (1 << AC97_SLOT_PCM_RIGHT_0)
  1516. }
  1517. }
  1518. },
  1519. /* PCM IN #1 */
  1520. {
  1521. .stream = 1,
  1522. .exclusive = 1,
  1523. .r = { {
  1524. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  1525. (1 << AC97_SLOT_PCM_RIGHT)
  1526. }
  1527. }
  1528. },
  1529. /* MIC IN #1 */
  1530. {
  1531. .stream = 1,
  1532. .exclusive = 1,
  1533. .r = { {
  1534. .slots = (1 << AC97_SLOT_MIC)
  1535. }
  1536. }
  1537. },
  1538. /* S/PDIF PCM */
  1539. {
  1540. .exclusive = 1,
  1541. .spdif = 1,
  1542. .r = { {
  1543. .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
  1544. (1 << AC97_SLOT_SPDIF_RIGHT2)
  1545. }
  1546. }
  1547. },
  1548. /* PCM IN #2 */
  1549. {
  1550. .stream = 1,
  1551. .exclusive = 1,
  1552. .r = { {
  1553. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  1554. (1 << AC97_SLOT_PCM_RIGHT)
  1555. }
  1556. }
  1557. },
  1558. /* MIC IN #2 */
  1559. {
  1560. .stream = 1,
  1561. .exclusive = 1,
  1562. .r = { {
  1563. .slots = (1 << AC97_SLOT_MIC)
  1564. }
  1565. }
  1566. },
  1567. };
  1568. static struct ac97_quirk ac97_quirks[] __devinitdata = {
  1569. {
  1570. .subvendor = 0x0e11,
  1571. .subdevice = 0x000e,
  1572. .name = "Compaq Deskpro EN", /* AD1885 */
  1573. .type = AC97_TUNE_HP_ONLY
  1574. },
  1575. {
  1576. .subvendor = 0x0e11,
  1577. .subdevice = 0x008a,
  1578. .name = "Compaq Evo W4000", /* AD1885 */
  1579. .type = AC97_TUNE_HP_ONLY
  1580. },
  1581. {
  1582. .subvendor = 0x0e11,
  1583. .subdevice = 0x00b8,
  1584. .name = "Compaq Evo D510C",
  1585. .type = AC97_TUNE_HP_ONLY
  1586. },
  1587. {
  1588. .subvendor = 0x0e11,
  1589. .subdevice = 0x0860,
  1590. .name = "HP/Compaq nx7010",
  1591. .type = AC97_TUNE_MUTE_LED
  1592. },
  1593. {
  1594. .subvendor = 0x1014,
  1595. .subdevice = 0x1f00,
  1596. .name = "MS-9128",
  1597. .type = AC97_TUNE_ALC_JACK
  1598. },
  1599. {
  1600. .subvendor = 0x1014,
  1601. .subdevice = 0x0267,
  1602. .name = "IBM NetVista A30p", /* AD1981B */
  1603. .type = AC97_TUNE_HP_ONLY
  1604. },
  1605. {
  1606. .subvendor = 0x1025,
  1607. .subdevice = 0x0082,
  1608. .name = "Acer Travelmate 2310",
  1609. .type = AC97_TUNE_HP_ONLY
  1610. },
  1611. {
  1612. .subvendor = 0x1025,
  1613. .subdevice = 0x0083,
  1614. .name = "Acer Aspire 3003LCi",
  1615. .type = AC97_TUNE_HP_ONLY
  1616. },
  1617. {
  1618. .subvendor = 0x1028,
  1619. .subdevice = 0x00d8,
  1620. .name = "Dell Precision 530", /* AD1885 */
  1621. .type = AC97_TUNE_HP_ONLY
  1622. },
  1623. {
  1624. .subvendor = 0x1028,
  1625. .subdevice = 0x010d,
  1626. .name = "Dell", /* which model? AD1885 */
  1627. .type = AC97_TUNE_HP_ONLY
  1628. },
  1629. {
  1630. .subvendor = 0x1028,
  1631. .subdevice = 0x0126,
  1632. .name = "Dell Optiplex GX260", /* AD1981A */
  1633. .type = AC97_TUNE_HP_ONLY
  1634. },
  1635. {
  1636. .subvendor = 0x1028,
  1637. .subdevice = 0x012c,
  1638. .name = "Dell Precision 650", /* AD1981A */
  1639. .type = AC97_TUNE_HP_ONLY
  1640. },
  1641. {
  1642. .subvendor = 0x1028,
  1643. .subdevice = 0x012d,
  1644. .name = "Dell Precision 450", /* AD1981B*/
  1645. .type = AC97_TUNE_HP_ONLY
  1646. },
  1647. {
  1648. .subvendor = 0x1028,
  1649. .subdevice = 0x0147,
  1650. .name = "Dell", /* which model? AD1981B*/
  1651. .type = AC97_TUNE_HP_ONLY
  1652. },
  1653. {
  1654. .subvendor = 0x1028,
  1655. .subdevice = 0x0151,
  1656. .name = "Dell Optiplex GX270", /* AD1981B */
  1657. .type = AC97_TUNE_HP_ONLY
  1658. },
  1659. {
  1660. .subvendor = 0x1028,
  1661. .subdevice = 0x014e,
  1662. .name = "Dell D800", /* STAC9750/51 */
  1663. .type = AC97_TUNE_HP_ONLY
  1664. },
  1665. {
  1666. .subvendor = 0x1028,
  1667. .subdevice = 0x0163,
  1668. .name = "Dell Unknown", /* STAC9750/51 */
  1669. .type = AC97_TUNE_HP_ONLY
  1670. },
  1671. {
  1672. .subvendor = 0x1028,
  1673. .subdevice = 0x016a,
  1674. .name = "Dell Inspiron 8600", /* STAC9750/51 */
  1675. .type = AC97_TUNE_HP_ONLY
  1676. },
  1677. {
  1678. .subvendor = 0x1028,
  1679. .subdevice = 0x0186,
  1680. .name = "Dell Latitude D810", /* cf. Malone #41015 */
  1681. .type = AC97_TUNE_HP_MUTE_LED
  1682. },
  1683. {
  1684. .subvendor = 0x1028,
  1685. .subdevice = 0x0188,
  1686. .name = "Dell Inspiron 6000",
  1687. .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
  1688. },
  1689. {
  1690. .subvendor = 0x1028,
  1691. .subdevice = 0x0191,
  1692. .name = "Dell Inspiron 8600",
  1693. .type = AC97_TUNE_HP_ONLY
  1694. },
  1695. {
  1696. .subvendor = 0x103c,
  1697. .subdevice = 0x006d,
  1698. .name = "HP zv5000",
  1699. .type = AC97_TUNE_MUTE_LED /*AD1981B*/
  1700. },
  1701. { /* FIXME: which codec? */
  1702. .subvendor = 0x103c,
  1703. .subdevice = 0x00c3,
  1704. .name = "HP xw6000",
  1705. .type = AC97_TUNE_HP_ONLY
  1706. },
  1707. {
  1708. .subvendor = 0x103c,
  1709. .subdevice = 0x088c,
  1710. .name = "HP nc8000",
  1711. .type = AC97_TUNE_HP_MUTE_LED
  1712. },
  1713. {
  1714. .subvendor = 0x103c,
  1715. .subdevice = 0x0890,
  1716. .name = "HP nc6000",
  1717. .type = AC97_TUNE_MUTE_LED
  1718. },
  1719. {
  1720. .subvendor = 0x103c,
  1721. .subdevice = 0x129d,
  1722. .name = "HP xw8000",
  1723. .type = AC97_TUNE_HP_ONLY
  1724. },
  1725. {
  1726. .subvendor = 0x103c,
  1727. .subdevice = 0x0938,
  1728. .name = "HP nc4200",
  1729. .type = AC97_TUNE_HP_MUTE_LED
  1730. },
  1731. {
  1732. .subvendor = 0x103c,
  1733. .subdevice = 0x099c,
  1734. .name = "HP nx6110/nc6120",
  1735. .type = AC97_TUNE_HP_MUTE_LED
  1736. },
  1737. {
  1738. .subvendor = 0x103c,
  1739. .subdevice = 0x0944,
  1740. .name = "HP nc6220",
  1741. .type = AC97_TUNE_HP_MUTE_LED
  1742. },
  1743. {
  1744. .subvendor = 0x103c,
  1745. .subdevice = 0x0934,
  1746. .name = "HP nc8220",
  1747. .type = AC97_TUNE_HP_MUTE_LED
  1748. },
  1749. {
  1750. .subvendor = 0x103c,
  1751. .subdevice = 0x12f1,
  1752. .name = "HP xw8200", /* AD1981B*/
  1753. .type = AC97_TUNE_HP_ONLY
  1754. },
  1755. {
  1756. .subvendor = 0x103c,
  1757. .subdevice = 0x12f2,
  1758. .name = "HP xw6200",
  1759. .type = AC97_TUNE_HP_ONLY
  1760. },
  1761. {
  1762. .subvendor = 0x103c,
  1763. .subdevice = 0x3008,
  1764. .name = "HP xw4200", /* AD1981B*/
  1765. .type = AC97_TUNE_HP_ONLY
  1766. },
  1767. {
  1768. .subvendor = 0x104d,
  1769. .subdevice = 0x8197,
  1770. .name = "Sony S1XP",
  1771. .type = AC97_TUNE_INV_EAPD
  1772. },
  1773. {
  1774. .subvendor = 0x1043,
  1775. .subdevice = 0x80f3,
  1776. .name = "ASUS ICH5/AD1985",
  1777. .type = AC97_TUNE_AD_SHARING
  1778. },
  1779. {
  1780. .subvendor = 0x10cf,
  1781. .subdevice = 0x11c3,
  1782. .name = "Fujitsu-Siemens E4010",
  1783. .type = AC97_TUNE_HP_ONLY
  1784. },
  1785. {
  1786. .subvendor = 0x10cf,
  1787. .subdevice = 0x1225,
  1788. .name = "Fujitsu-Siemens T3010",
  1789. .type = AC97_TUNE_HP_ONLY
  1790. },
  1791. {
  1792. .subvendor = 0x10cf,
  1793. .subdevice = 0x1253,
  1794. .name = "Fujitsu S6210", /* STAC9750/51 */
  1795. .type = AC97_TUNE_HP_ONLY
  1796. },
  1797. {
  1798. .subvendor = 0x10cf,
  1799. .subdevice = 0x127d,
  1800. .name = "Fujitsu Lifebook P7010",
  1801. .type = AC97_TUNE_HP_ONLY
  1802. },
  1803. {
  1804. .subvendor = 0x10cf,
  1805. .subdevice = 0x127e,
  1806. .name = "Fujitsu Lifebook C1211D",
  1807. .type = AC97_TUNE_HP_ONLY
  1808. },
  1809. {
  1810. .subvendor = 0x10cf,
  1811. .subdevice = 0x12ec,
  1812. .name = "Fujitsu-Siemens 4010",
  1813. .type = AC97_TUNE_HP_ONLY
  1814. },
  1815. {
  1816. .subvendor = 0x10cf,
  1817. .subdevice = 0x12f2,
  1818. .name = "Fujitsu-Siemens Celsius H320",
  1819. .type = AC97_TUNE_SWAP_HP
  1820. },
  1821. {
  1822. .subvendor = 0x10f1,
  1823. .subdevice = 0x2665,
  1824. .name = "Fujitsu-Siemens Celsius", /* AD1981? */
  1825. .type = AC97_TUNE_HP_ONLY
  1826. },
  1827. {
  1828. .subvendor = 0x10f1,
  1829. .subdevice = 0x2885,
  1830. .name = "AMD64 Mobo", /* ALC650 */
  1831. .type = AC97_TUNE_HP_ONLY
  1832. },
  1833. {
  1834. .subvendor = 0x10f1,
  1835. .subdevice = 0x2895,
  1836. .name = "Tyan Thunder K8WE",
  1837. .type = AC97_TUNE_HP_ONLY
  1838. },
  1839. {
  1840. .subvendor = 0x10f7,
  1841. .subdevice = 0x834c,
  1842. .name = "Panasonic CF-R4",
  1843. .type = AC97_TUNE_HP_ONLY,
  1844. },
  1845. {
  1846. .subvendor = 0x110a,
  1847. .subdevice = 0x0056,
  1848. .name = "Fujitsu-Siemens Scenic", /* AD1981? */
  1849. .type = AC97_TUNE_HP_ONLY
  1850. },
  1851. {
  1852. .subvendor = 0x11d4,
  1853. .subdevice = 0x5375,
  1854. .name = "ADI AD1985 (discrete)",
  1855. .type = AC97_TUNE_HP_ONLY
  1856. },
  1857. {
  1858. .subvendor = 0x1462,
  1859. .subdevice = 0x5470,
  1860. .name = "MSI P4 ATX 645 Ultra",
  1861. .type = AC97_TUNE_HP_ONLY
  1862. },
  1863. {
  1864. .subvendor = 0x1734,
  1865. .subdevice = 0x0088,
  1866. .name = "Fujitsu-Siemens D1522", /* AD1981 */
  1867. .type = AC97_TUNE_HP_ONLY
  1868. },
  1869. {
  1870. .subvendor = 0x8086,
  1871. .subdevice = 0x2000,
  1872. .mask = 0xfff0,
  1873. .name = "Intel ICH5/AD1985",
  1874. .type = AC97_TUNE_AD_SHARING
  1875. },
  1876. {
  1877. .subvendor = 0x8086,
  1878. .subdevice = 0x4000,
  1879. .mask = 0xfff0,
  1880. .name = "Intel ICH5/AD1985",
  1881. .type = AC97_TUNE_AD_SHARING
  1882. },
  1883. {
  1884. .subvendor = 0x8086,
  1885. .subdevice = 0x4856,
  1886. .name = "Intel D845WN (82801BA)",
  1887. .type = AC97_TUNE_SWAP_HP
  1888. },
  1889. {
  1890. .subvendor = 0x8086,
  1891. .subdevice = 0x4d44,
  1892. .name = "Intel D850EMV2", /* AD1885 */
  1893. .type = AC97_TUNE_HP_ONLY
  1894. },
  1895. {
  1896. .subvendor = 0x8086,
  1897. .subdevice = 0x4d56,
  1898. .name = "Intel ICH/AD1885",
  1899. .type = AC97_TUNE_HP_ONLY
  1900. },
  1901. {
  1902. .subvendor = 0x8086,
  1903. .subdevice = 0x6000,
  1904. .mask = 0xfff0,
  1905. .name = "Intel ICH5/AD1985",
  1906. .type = AC97_TUNE_AD_SHARING
  1907. },
  1908. {
  1909. .subvendor = 0x8086,
  1910. .subdevice = 0xe000,
  1911. .mask = 0xfff0,
  1912. .name = "Intel ICH5/AD1985",
  1913. .type = AC97_TUNE_AD_SHARING
  1914. },
  1915. #if 0 /* FIXME: this seems wrong on most boards */
  1916. {
  1917. .subvendor = 0x8086,
  1918. .subdevice = 0xa000,
  1919. .mask = 0xfff0,
  1920. .name = "Intel ICH5/AD1985",
  1921. .type = AC97_TUNE_HP_ONLY
  1922. },
  1923. #endif
  1924. { } /* terminator */
  1925. };
  1926. static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
  1927. const char *quirk_override)
  1928. {
  1929. struct snd_ac97_bus *pbus;
  1930. struct snd_ac97_template ac97;
  1931. int err;
  1932. unsigned int i, codecs;
  1933. unsigned int glob_sta = 0;
  1934. struct snd_ac97_bus_ops *ops;
  1935. static struct snd_ac97_bus_ops standard_bus_ops = {
  1936. .write = snd_intel8x0_codec_write,
  1937. .read = snd_intel8x0_codec_read,
  1938. };
  1939. static struct snd_ac97_bus_ops ali_bus_ops = {
  1940. .write = snd_intel8x0_ali_codec_write,
  1941. .read = snd_intel8x0_ali_codec_read,
  1942. };
  1943. chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
  1944. if (!spdif_aclink) {
  1945. switch (chip->device_type) {
  1946. case DEVICE_NFORCE:
  1947. chip->spdif_idx = NVD_SPBAR;
  1948. break;
  1949. case DEVICE_ALI:
  1950. chip->spdif_idx = ALID_AC97SPDIFOUT;
  1951. break;
  1952. case DEVICE_INTEL_ICH4:
  1953. chip->spdif_idx = ICHD_SPBAR;
  1954. break;
  1955. };
  1956. }
  1957. chip->in_ac97_init = 1;
  1958. memset(&ac97, 0, sizeof(ac97));
  1959. ac97.private_data = chip;
  1960. ac97.private_free = snd_intel8x0_mixer_free_ac97;
  1961. ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
  1962. if (chip->xbox)
  1963. ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
  1964. if (chip->device_type != DEVICE_ALI) {
  1965. glob_sta = igetdword(chip, ICHREG(GLOB_STA));
  1966. ops = &standard_bus_ops;
  1967. chip->in_sdin_init = 1;
  1968. codecs = 0;
  1969. for (i = 0; i < chip->max_codecs; i++) {
  1970. if (! (glob_sta & chip->codec_bit[i]))
  1971. continue;
  1972. if (chip->device_type == DEVICE_INTEL_ICH4) {
  1973. snd_intel8x0_codec_read_test(chip, codecs);
  1974. chip->ac97_sdin[codecs] =
  1975. igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
  1976. if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
  1977. chip->ac97_sdin[codecs] = 0;
  1978. } else
  1979. chip->ac97_sdin[codecs] = i;
  1980. codecs++;
  1981. }
  1982. chip->in_sdin_init = 0;
  1983. if (! codecs)
  1984. codecs = 1;
  1985. } else {
  1986. ops = &ali_bus_ops;
  1987. codecs = 1;
  1988. /* detect the secondary codec */
  1989. for (i = 0; i < 100; i++) {
  1990. unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
  1991. if (reg & 0x40) {
  1992. codecs = 2;
  1993. break;
  1994. }
  1995. iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
  1996. udelay(1);
  1997. }
  1998. }
  1999. if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
  2000. goto __err;
  2001. pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
  2002. if (ac97_clock >= 8000 && ac97_clock <= 48000)
  2003. pbus->clock = ac97_clock;
  2004. /* FIXME: my test board doesn't work well with VRA... */
  2005. if (chip->device_type == DEVICE_ALI)
  2006. pbus->no_vra = 1;
  2007. else
  2008. pbus->dra = 1;
  2009. chip->ac97_bus = pbus;
  2010. chip->ncodecs = codecs;
  2011. ac97.pci = chip->pci;
  2012. for (i = 0; i < codecs; i++) {
  2013. ac97.num = i;
  2014. if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
  2015. if (err != -EACCES)
  2016. snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
  2017. if (i == 0)
  2018. goto __err;
  2019. }
  2020. }
  2021. /* tune up the primary codec */
  2022. snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
  2023. /* enable separate SDINs for ICH4 */
  2024. if (chip->device_type == DEVICE_INTEL_ICH4)
  2025. pbus->isdin = 1;
  2026. /* find the available PCM streams */
  2027. i = ARRAY_SIZE(ac97_pcm_defs);
  2028. if (chip->device_type != DEVICE_INTEL_ICH4)
  2029. i -= 2; /* do not allocate PCM2IN and MIC2 */
  2030. if (chip->spdif_idx < 0)
  2031. i--; /* do not allocate S/PDIF */
  2032. err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
  2033. if (err < 0)
  2034. goto __err;
  2035. chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
  2036. chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
  2037. chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
  2038. if (chip->spdif_idx >= 0)
  2039. chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
  2040. if (chip->device_type == DEVICE_INTEL_ICH4) {
  2041. chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
  2042. chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
  2043. }
  2044. /* enable separate SDINs for ICH4 */
  2045. if (chip->device_type == DEVICE_INTEL_ICH4) {
  2046. struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
  2047. u8 tmp = igetbyte(chip, ICHREG(SDM));
  2048. tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
  2049. if (pcm) {
  2050. tmp |= ICH_SE; /* steer enable for multiple SDINs */
  2051. tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
  2052. for (i = 1; i < 4; i++) {
  2053. if (pcm->r[0].codec[i]) {
  2054. tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
  2055. break;
  2056. }
  2057. }
  2058. } else {
  2059. tmp &= ~ICH_SE; /* steer disable */
  2060. }
  2061. iputbyte(chip, ICHREG(SDM), tmp);
  2062. }
  2063. if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
  2064. chip->multi4 = 1;
  2065. if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
  2066. chip->multi6 = 1;
  2067. if (chip->ac97[0]->flags & AC97_HAS_8CH)
  2068. chip->multi8 = 1;
  2069. }
  2070. }
  2071. if (pbus->pcms[0].r[1].rslots[0]) {
  2072. chip->dra = 1;
  2073. }
  2074. if (chip->device_type == DEVICE_INTEL_ICH4) {
  2075. if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
  2076. chip->smp20bit = 1;
  2077. }
  2078. if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
  2079. /* 48kHz only */
  2080. chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
  2081. }
  2082. if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
  2083. /* use slot 10/11 for SPDIF */
  2084. u32 val;
  2085. val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
  2086. val |= ICH_PCM_SPDIF_1011;
  2087. iputdword(chip, ICHREG(GLOB_CNT), val);
  2088. snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
  2089. }
  2090. chip->in_ac97_init = 0;
  2091. return 0;
  2092. __err:
  2093. /* clear the cold-reset bit for the next chance */
  2094. if (chip->device_type != DEVICE_ALI)
  2095. iputdword(chip, ICHREG(GLOB_CNT),
  2096. igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
  2097. return err;
  2098. }
  2099. /*
  2100. *
  2101. */
  2102. static void do_ali_reset(struct intel8x0 *chip)
  2103. {
  2104. iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
  2105. iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
  2106. iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
  2107. iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
  2108. iputdword(chip, ICHREG(ALI_INTERFACECR),
  2109. ICH_ALI_IF_PI|ICH_ALI_IF_PO);
  2110. iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
  2111. iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
  2112. }
  2113. #ifdef CONFIG_SND_AC97_POWER_SAVE
  2114. static struct snd_pci_quirk ich_chip_reset_mode[] = {
  2115. SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
  2116. { } /* end */
  2117. };
  2118. static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
  2119. {
  2120. unsigned int cnt;
  2121. /* ACLink on, 2 channels */
  2122. if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
  2123. return -EIO;
  2124. cnt = igetdword(chip, ICHREG(GLOB_CNT));
  2125. cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
  2126. /* do cold reset - the full ac97 powerdown may leave the controller
  2127. * in a warm state but actually it cannot communicate with the codec.
  2128. */
  2129. iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
  2130. cnt = igetdword(chip, ICHREG(GLOB_CNT));
  2131. udelay(10);
  2132. iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
  2133. msleep(1);
  2134. return 0;
  2135. }
  2136. #define snd_intel8x0_ich_chip_can_cold_reset(chip) \
  2137. (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
  2138. #else
  2139. #define snd_intel8x0_ich_chip_cold_reset(chip) 0
  2140. #define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
  2141. #endif
  2142. static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
  2143. {
  2144. unsigned long end_time;
  2145. unsigned int cnt;
  2146. /* ACLink on, 2 channels */
  2147. cnt = igetdword(chip, ICHREG(GLOB_CNT));
  2148. cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
  2149. /* finish cold or do warm reset */
  2150. cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
  2151. iputdword(chip, ICHREG(GLOB_CNT), cnt);
  2152. end_time = (jiffies + (HZ / 4)) + 1;
  2153. do {
  2154. if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
  2155. return 0;
  2156. schedule_timeout_uninterruptible(1);
  2157. } while (time_after_eq(end_time, jiffies));
  2158. snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
  2159. igetdword(chip, ICHREG(GLOB_CNT)));
  2160. return -EIO;
  2161. }
  2162. static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
  2163. {
  2164. unsigned long end_time;
  2165. unsigned int status, nstatus;
  2166. unsigned int cnt;
  2167. int err;
  2168. /* put logic to right state */
  2169. /* first clear status bits */
  2170. status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
  2171. if (chip->device_type == DEVICE_NFORCE)
  2172. status |= ICH_NVSPINT;
  2173. cnt = igetdword(chip, ICHREG(GLOB_STA));
  2174. iputdword(chip, ICHREG(GLOB_STA), cnt & status);
  2175. if (snd_intel8x0_ich_chip_can_cold_reset(chip))
  2176. err = snd_intel8x0_ich_chip_cold_reset(chip);
  2177. else
  2178. err = snd_intel8x0_ich_chip_reset(chip);
  2179. if (err < 0)
  2180. return err;
  2181. if (probing) {
  2182. /* wait for any codec ready status.
  2183. * Once it becomes ready it should remain ready
  2184. * as long as we do not disable the ac97 link.
  2185. */
  2186. end_time = jiffies + HZ;
  2187. do {
  2188. status = igetdword(chip, ICHREG(GLOB_STA)) &
  2189. chip->codec_isr_bits;
  2190. if (status)
  2191. break;
  2192. schedule_timeout_uninterruptible(1);
  2193. } while (time_after_eq(end_time, jiffies));
  2194. if (! status) {
  2195. /* no codec is found */
  2196. snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
  2197. igetdword(chip, ICHREG(GLOB_STA)));
  2198. return -EIO;
  2199. }
  2200. /* wait for other codecs ready status. */
  2201. end_time = jiffies + HZ / 4;
  2202. while (status != chip->codec_isr_bits &&
  2203. time_after_eq(end_time, jiffies)) {
  2204. schedule_timeout_uninterruptible(1);
  2205. status |= igetdword(chip, ICHREG(GLOB_STA)) &
  2206. chip->codec_isr_bits;
  2207. }
  2208. } else {
  2209. /* resume phase */
  2210. int i;
  2211. status = 0;
  2212. for (i = 0; i < chip->ncodecs; i++)
  2213. if (chip->ac97[i])
  2214. status |= chip->codec_bit[chip->ac97_sdin[i]];
  2215. /* wait until all the probed codecs are ready */
  2216. end_time = jiffies + HZ;
  2217. do {
  2218. nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
  2219. chip->codec_isr_bits;
  2220. if (status == nstatus)
  2221. break;
  2222. schedule_timeout_uninterruptible(1);
  2223. } while (time_after_eq(end_time, jiffies));
  2224. }
  2225. if (chip->device_type == DEVICE_SIS) {
  2226. /* unmute the output on SIS7012 */
  2227. iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
  2228. }
  2229. if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
  2230. /* enable SPDIF interrupt */
  2231. unsigned int val;
  2232. pci_read_config_dword(chip->pci, 0x4c, &val);
  2233. val |= 0x1000000;
  2234. pci_write_config_dword(chip->pci, 0x4c, val);
  2235. }
  2236. return 0;
  2237. }
  2238. static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
  2239. {
  2240. u32 reg;
  2241. int i = 0;
  2242. reg = igetdword(chip, ICHREG(ALI_SCR));
  2243. if ((reg & 2) == 0) /* Cold required */
  2244. reg |= 2;
  2245. else
  2246. reg |= 1; /* Warm */
  2247. reg &= ~0x80000000; /* ACLink on */
  2248. iputdword(chip, ICHREG(ALI_SCR), reg);
  2249. for (i = 0; i < HZ / 2; i++) {
  2250. if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
  2251. goto __ok;
  2252. schedule_timeout_uninterruptible(1);
  2253. }
  2254. snd_printk(KERN_ERR "AC'97 reset failed.\n");
  2255. if (probing)
  2256. return -EIO;
  2257. __ok:
  2258. for (i = 0; i < HZ / 2; i++) {
  2259. reg = igetdword(chip, ICHREG(ALI_RTSR));
  2260. if (reg & 0x80) /* primary codec */
  2261. break;
  2262. iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
  2263. schedule_timeout_uninterruptible(1);
  2264. }
  2265. do_ali_reset(chip);
  2266. return 0;
  2267. }
  2268. static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
  2269. {
  2270. unsigned int i, timeout;
  2271. int err;
  2272. if (chip->device_type != DEVICE_ALI) {
  2273. if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
  2274. return err;
  2275. iagetword(chip, 0); /* clear semaphore flag */
  2276. } else {
  2277. if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
  2278. return err;
  2279. }
  2280. /* disable interrupts */
  2281. for (i = 0; i < chip->bdbars_count; i++)
  2282. iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
  2283. /* reset channels */
  2284. for (i = 0; i < chip->bdbars_count; i++)
  2285. iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
  2286. for (i = 0; i < chip->bdbars_count; i++) {
  2287. timeout = 100000;
  2288. while (--timeout != 0) {
  2289. if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
  2290. break;
  2291. }
  2292. if (timeout == 0)
  2293. printk(KERN_ERR "intel8x0: reset of registers failed?\n");
  2294. }
  2295. /* initialize Buffer Descriptor Lists */
  2296. for (i = 0; i < chip->bdbars_count; i++)
  2297. iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
  2298. chip->ichd[i].bdbar_addr);
  2299. return 0;
  2300. }
  2301. static int snd_intel8x0_free(struct intel8x0 *chip)
  2302. {
  2303. unsigned int i;
  2304. if (chip->irq < 0)
  2305. goto __hw_end;
  2306. /* disable interrupts */
  2307. for (i = 0; i < chip->bdbars_count; i++)
  2308. iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
  2309. /* reset channels */
  2310. for (i = 0; i < chip->bdbars_count; i++)
  2311. iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
  2312. if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
  2313. /* stop the spdif interrupt */
  2314. unsigned int val;
  2315. pci_read_config_dword(chip->pci, 0x4c, &val);
  2316. val &= ~0x1000000;
  2317. pci_write_config_dword(chip->pci, 0x4c, val);
  2318. }
  2319. /* --- */
  2320. __hw_end:
  2321. if (chip->irq >= 0)
  2322. free_irq(chip->irq, chip);
  2323. if (chip->bdbars.area) {
  2324. if (chip->fix_nocache)
  2325. fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
  2326. snd_dma_free_pages(&chip->bdbars);
  2327. }
  2328. if (chip->addr)
  2329. pci_iounmap(chip->pci, chip->addr);
  2330. if (chip->bmaddr)
  2331. pci_iounmap(chip->pci, chip->bmaddr);
  2332. pci_release_regions(chip->pci);
  2333. pci_disable_device(chip->pci);
  2334. kfree(chip);
  2335. return 0;
  2336. }
  2337. #ifdef CONFIG_PM
  2338. /*
  2339. * power management
  2340. */
  2341. static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
  2342. {
  2343. struct snd_card *card = pci_get_drvdata(pci);
  2344. struct intel8x0 *chip = card->private_data;
  2345. int i;
  2346. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  2347. for (i = 0; i < chip->pcm_devs; i++)
  2348. snd_pcm_suspend_all(chip->pcm[i]);
  2349. /* clear nocache */
  2350. if (chip->fix_nocache) {
  2351. for (i = 0; i < chip->bdbars_count; i++) {
  2352. struct ichdev *ichdev = &chip->ichd[i];
  2353. if (ichdev->substream && ichdev->page_attr_changed) {
  2354. struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
  2355. if (runtime->dma_area)
  2356. fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
  2357. }
  2358. }
  2359. }
  2360. for (i = 0; i < chip->ncodecs; i++)
  2361. snd_ac97_suspend(chip->ac97[i]);
  2362. if (chip->device_type == DEVICE_INTEL_ICH4)
  2363. chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
  2364. if (chip->irq >= 0) {
  2365. free_irq(chip->irq, chip);
  2366. chip->irq = -1;
  2367. }
  2368. pci_disable_device(pci);
  2369. pci_save_state(pci);
  2370. /* The call below may disable built-in speaker on some laptops
  2371. * after S2RAM. So, don't touch it.
  2372. */
  2373. /* pci_set_power_state(pci, pci_choose_state(pci, state)); */
  2374. return 0;
  2375. }
  2376. static int intel8x0_resume(struct pci_dev *pci)
  2377. {
  2378. struct snd_card *card = pci_get_drvdata(pci);
  2379. struct intel8x0 *chip = card->private_data;
  2380. int i;
  2381. pci_set_power_state(pci, PCI_D0);
  2382. pci_restore_state(pci);
  2383. if (pci_enable_device(pci) < 0) {
  2384. printk(KERN_ERR "intel8x0: pci_enable_device failed, "
  2385. "disabling device\n");
  2386. snd_card_disconnect(card);
  2387. return -EIO;
  2388. }
  2389. pci_set_master(pci);
  2390. snd_intel8x0_chip_init(chip, 0);
  2391. if (request_irq(pci->irq, snd_intel8x0_interrupt,
  2392. IRQF_SHARED, card->shortname, chip)) {
  2393. printk(KERN_ERR "intel8x0: unable to grab IRQ %d, "
  2394. "disabling device\n", pci->irq);
  2395. snd_card_disconnect(card);
  2396. return -EIO;
  2397. }
  2398. chip->irq = pci->irq;
  2399. synchronize_irq(chip->irq);
  2400. /* re-initialize mixer stuff */
  2401. if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
  2402. /* enable separate SDINs for ICH4 */
  2403. iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
  2404. /* use slot 10/11 for SPDIF */
  2405. iputdword(chip, ICHREG(GLOB_CNT),
  2406. (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
  2407. ICH_PCM_SPDIF_1011);
  2408. }
  2409. /* refill nocache */
  2410. if (chip->fix_nocache)
  2411. fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
  2412. for (i = 0; i < chip->ncodecs; i++)
  2413. snd_ac97_resume(chip->ac97[i]);
  2414. /* refill nocache */
  2415. if (chip->fix_nocache) {
  2416. for (i = 0; i < chip->bdbars_count; i++) {
  2417. struct ichdev *ichdev = &chip->ichd[i];
  2418. if (ichdev->substream && ichdev->page_attr_changed) {
  2419. struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
  2420. if (runtime->dma_area)
  2421. fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
  2422. }
  2423. }
  2424. }
  2425. /* resume status */
  2426. for (i = 0; i < chip->bdbars_count; i++) {
  2427. struct ichdev *ichdev = &chip->ichd[i];
  2428. unsigned long port = ichdev->reg_offset;
  2429. if (! ichdev->substream || ! ichdev->suspended)
  2430. continue;
  2431. if (ichdev->ichd == ICHD_PCMOUT)
  2432. snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
  2433. iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
  2434. iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
  2435. iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
  2436. iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
  2437. }
  2438. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  2439. return 0;
  2440. }
  2441. #endif /* CONFIG_PM */
  2442. #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
  2443. static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
  2444. {
  2445. struct snd_pcm_substream *subs;
  2446. struct ichdev *ichdev;
  2447. unsigned long port;
  2448. unsigned long pos, pos1, t;
  2449. int civ, timeout = 1000, attempt = 1;
  2450. struct timespec start_time, stop_time;
  2451. if (chip->ac97_bus->clock != 48000)
  2452. return; /* specified in module option */
  2453. __again:
  2454. subs = chip->pcm[0]->streams[0].substream;
  2455. if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
  2456. snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
  2457. return;
  2458. }
  2459. ichdev = &chip->ichd[ICHD_PCMOUT];
  2460. ichdev->physbuf = subs->dma_buffer.addr;
  2461. ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
  2462. ichdev->substream = NULL; /* don't process interrupts */
  2463. /* set rate */
  2464. if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
  2465. snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
  2466. return;
  2467. }
  2468. snd_intel8x0_setup_periods(chip, ichdev);
  2469. port = ichdev->reg_offset;
  2470. spin_lock_irq(&chip->reg_lock);
  2471. chip->in_measurement = 1;
  2472. /* trigger */
  2473. if (chip->device_type != DEVICE_ALI)
  2474. iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
  2475. else {
  2476. iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
  2477. iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
  2478. }
  2479. do_posix_clock_monotonic_gettime(&start_time);
  2480. spin_unlock_irq(&chip->reg_lock);
  2481. msleep(50);
  2482. spin_lock_irq(&chip->reg_lock);
  2483. /* check the position */
  2484. do {
  2485. civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
  2486. pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
  2487. if (pos1 == 0) {
  2488. udelay(10);
  2489. continue;
  2490. }
  2491. if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
  2492. pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
  2493. break;
  2494. } while (timeout--);
  2495. if (pos1 == 0) { /* oops, this value is not reliable */
  2496. pos = 0;
  2497. } else {
  2498. pos = ichdev->fragsize1;
  2499. pos -= pos1 << ichdev->pos_shift;
  2500. pos += ichdev->position;
  2501. }
  2502. chip->in_measurement = 0;
  2503. do_posix_clock_monotonic_gettime(&stop_time);
  2504. /* stop */
  2505. if (chip->device_type == DEVICE_ALI) {
  2506. iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
  2507. iputbyte(chip, port + ICH_REG_OFF_CR, 0);
  2508. while (igetbyte(chip, port + ICH_REG_OFF_CR))
  2509. ;
  2510. } else {
  2511. iputbyte(chip, port + ICH_REG_OFF_CR, 0);
  2512. while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
  2513. ;
  2514. }
  2515. iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
  2516. spin_unlock_irq(&chip->reg_lock);
  2517. if (pos == 0) {
  2518. snd_printk(KERN_ERR "intel8x0: measure - unreliable DMA position..\n");
  2519. __retry:
  2520. if (attempt < 3) {
  2521. msleep(300);
  2522. attempt++;
  2523. goto __again;
  2524. }
  2525. goto __end;
  2526. }
  2527. pos /= 4;
  2528. t = stop_time.tv_sec - start_time.tv_sec;
  2529. t *= 1000000;
  2530. t += (stop_time.tv_nsec - start_time.tv_nsec) / 1000;
  2531. printk(KERN_INFO "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
  2532. if (t == 0) {
  2533. snd_printk(KERN_ERR "intel8x0: ?? calculation error..\n");
  2534. goto __retry;
  2535. }
  2536. pos *= 1000;
  2537. pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
  2538. if (pos < 40000 || pos >= 60000) {
  2539. /* abnormal value. hw problem? */
  2540. printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
  2541. goto __retry;
  2542. } else if (pos > 40500 && pos < 41500)
  2543. /* first exception - 41000Hz reference clock */
  2544. chip->ac97_bus->clock = 41000;
  2545. else if (pos > 43600 && pos < 44600)
  2546. /* second exception - 44100HZ reference clock */
  2547. chip->ac97_bus->clock = 44100;
  2548. else if (pos < 47500 || pos > 48500)
  2549. /* not 48000Hz, tuning the clock.. */
  2550. chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
  2551. __end:
  2552. printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
  2553. snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
  2554. }
  2555. static struct snd_pci_quirk intel8x0_clock_list[] __devinitdata = {
  2556. SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
  2557. SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
  2558. SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
  2559. SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
  2560. SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
  2561. { } /* terminator */
  2562. };
  2563. static int __devinit intel8x0_in_clock_list(struct intel8x0 *chip)
  2564. {
  2565. struct pci_dev *pci = chip->pci;
  2566. const struct snd_pci_quirk *wl;
  2567. wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
  2568. if (!wl)
  2569. return 0;
  2570. printk(KERN_INFO "intel8x0: white list rate for %04x:%04x is %i\n",
  2571. pci->subsystem_vendor, pci->subsystem_device, wl->value);
  2572. chip->ac97_bus->clock = wl->value;
  2573. return 1;
  2574. }
  2575. #ifdef CONFIG_PROC_FS
  2576. static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
  2577. struct snd_info_buffer *buffer)
  2578. {
  2579. struct intel8x0 *chip = entry->private_data;
  2580. unsigned int tmp;
  2581. snd_iprintf(buffer, "Intel8x0\n\n");
  2582. if (chip->device_type == DEVICE_ALI)
  2583. return;
  2584. tmp = igetdword(chip, ICHREG(GLOB_STA));
  2585. snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
  2586. snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
  2587. if (chip->device_type == DEVICE_INTEL_ICH4)
  2588. snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
  2589. snd_iprintf(buffer, "AC'97 codecs ready :");
  2590. if (tmp & chip->codec_isr_bits) {
  2591. int i;
  2592. static const char *codecs[3] = {
  2593. "primary", "secondary", "tertiary"
  2594. };
  2595. for (i = 0; i < chip->max_codecs; i++)
  2596. if (tmp & chip->codec_bit[i])
  2597. snd_iprintf(buffer, " %s", codecs[i]);
  2598. } else
  2599. snd_iprintf(buffer, " none");
  2600. snd_iprintf(buffer, "\n");
  2601. if (chip->device_type == DEVICE_INTEL_ICH4 ||
  2602. chip->device_type == DEVICE_SIS)
  2603. snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
  2604. chip->ac97_sdin[0],
  2605. chip->ac97_sdin[1],
  2606. chip->ac97_sdin[2]);
  2607. }
  2608. static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
  2609. {
  2610. struct snd_info_entry *entry;
  2611. if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
  2612. snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
  2613. }
  2614. #else
  2615. #define snd_intel8x0_proc_init(x)
  2616. #endif
  2617. static int snd_intel8x0_dev_free(struct snd_device *device)
  2618. {
  2619. struct intel8x0 *chip = device->device_data;
  2620. return snd_intel8x0_free(chip);
  2621. }
  2622. struct ich_reg_info {
  2623. unsigned int int_sta_mask;
  2624. unsigned int offset;
  2625. };
  2626. static unsigned int ich_codec_bits[3] = {
  2627. ICH_PCR, ICH_SCR, ICH_TCR
  2628. };
  2629. static unsigned int sis_codec_bits[3] = {
  2630. ICH_PCR, ICH_SCR, ICH_SIS_TCR
  2631. };
  2632. static int __devinit snd_intel8x0_create(struct snd_card *card,
  2633. struct pci_dev *pci,
  2634. unsigned long device_type,
  2635. struct intel8x0 ** r_intel8x0)
  2636. {
  2637. struct intel8x0 *chip;
  2638. int err;
  2639. unsigned int i;
  2640. unsigned int int_sta_masks;
  2641. struct ichdev *ichdev;
  2642. static struct snd_device_ops ops = {
  2643. .dev_free = snd_intel8x0_dev_free,
  2644. };
  2645. static unsigned int bdbars[] = {
  2646. 3, /* DEVICE_INTEL */
  2647. 6, /* DEVICE_INTEL_ICH4 */
  2648. 3, /* DEVICE_SIS */
  2649. 6, /* DEVICE_ALI */
  2650. 4, /* DEVICE_NFORCE */
  2651. };
  2652. static struct ich_reg_info intel_regs[6] = {
  2653. { ICH_PIINT, 0 },
  2654. { ICH_POINT, 0x10 },
  2655. { ICH_MCINT, 0x20 },
  2656. { ICH_M2INT, 0x40 },
  2657. { ICH_P2INT, 0x50 },
  2658. { ICH_SPINT, 0x60 },
  2659. };
  2660. static struct ich_reg_info nforce_regs[4] = {
  2661. { ICH_PIINT, 0 },
  2662. { ICH_POINT, 0x10 },
  2663. { ICH_MCINT, 0x20 },
  2664. { ICH_NVSPINT, 0x70 },
  2665. };
  2666. static struct ich_reg_info ali_regs[6] = {
  2667. { ALI_INT_PCMIN, 0x40 },
  2668. { ALI_INT_PCMOUT, 0x50 },
  2669. { ALI_INT_MICIN, 0x60 },
  2670. { ALI_INT_CODECSPDIFOUT, 0x70 },
  2671. { ALI_INT_SPDIFIN, 0xa0 },
  2672. { ALI_INT_SPDIFOUT, 0xb0 },
  2673. };
  2674. struct ich_reg_info *tbl;
  2675. *r_intel8x0 = NULL;
  2676. if ((err = pci_enable_device(pci)) < 0)
  2677. return err;
  2678. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  2679. if (chip == NULL) {
  2680. pci_disable_device(pci);
  2681. return -ENOMEM;
  2682. }
  2683. spin_lock_init(&chip->reg_lock);
  2684. chip->device_type = device_type;
  2685. chip->card = card;
  2686. chip->pci = pci;
  2687. chip->irq = -1;
  2688. /* module parameters */
  2689. chip->buggy_irq = buggy_irq;
  2690. chip->buggy_semaphore = buggy_semaphore;
  2691. if (xbox)
  2692. chip->xbox = 1;
  2693. if (pci->vendor == PCI_VENDOR_ID_INTEL &&
  2694. pci->device == PCI_DEVICE_ID_INTEL_440MX)
  2695. chip->fix_nocache = 1; /* enable workaround */
  2696. if ((err = pci_request_regions(pci, card->shortname)) < 0) {
  2697. kfree(chip);
  2698. pci_disable_device(pci);
  2699. return err;
  2700. }
  2701. if (device_type == DEVICE_ALI) {
  2702. /* ALI5455 has no ac97 region */
  2703. chip->bmaddr = pci_iomap(pci, 0, 0);
  2704. goto port_inited;
  2705. }
  2706. if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
  2707. chip->addr = pci_iomap(pci, 2, 0);
  2708. else
  2709. chip->addr = pci_iomap(pci, 0, 0);
  2710. if (!chip->addr) {
  2711. snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
  2712. snd_intel8x0_free(chip);
  2713. return -EIO;
  2714. }
  2715. if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
  2716. chip->bmaddr = pci_iomap(pci, 3, 0);
  2717. else
  2718. chip->bmaddr = pci_iomap(pci, 1, 0);
  2719. if (!chip->bmaddr) {
  2720. snd_printk(KERN_ERR "Controller space ioremap problem\n");
  2721. snd_intel8x0_free(chip);
  2722. return -EIO;
  2723. }
  2724. port_inited:
  2725. chip->bdbars_count = bdbars[device_type];
  2726. /* initialize offsets */
  2727. switch (device_type) {
  2728. case DEVICE_NFORCE:
  2729. tbl = nforce_regs;
  2730. break;
  2731. case DEVICE_ALI:
  2732. tbl = ali_regs;
  2733. break;
  2734. default:
  2735. tbl = intel_regs;
  2736. break;
  2737. }
  2738. for (i = 0; i < chip->bdbars_count; i++) {
  2739. ichdev = &chip->ichd[i];
  2740. ichdev->ichd = i;
  2741. ichdev->reg_offset = tbl[i].offset;
  2742. ichdev->int_sta_mask = tbl[i].int_sta_mask;
  2743. if (device_type == DEVICE_SIS) {
  2744. /* SiS 7012 swaps the registers */
  2745. ichdev->roff_sr = ICH_REG_OFF_PICB;
  2746. ichdev->roff_picb = ICH_REG_OFF_SR;
  2747. } else {
  2748. ichdev->roff_sr = ICH_REG_OFF_SR;
  2749. ichdev->roff_picb = ICH_REG_OFF_PICB;
  2750. }
  2751. if (device_type == DEVICE_ALI)
  2752. ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
  2753. /* SIS7012 handles the pcm data in bytes, others are in samples */
  2754. ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
  2755. }
  2756. /* allocate buffer descriptor lists */
  2757. /* the start of each lists must be aligned to 8 bytes */
  2758. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
  2759. chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
  2760. &chip->bdbars) < 0) {
  2761. snd_intel8x0_free(chip);
  2762. snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
  2763. return -ENOMEM;
  2764. }
  2765. /* tables must be aligned to 8 bytes here, but the kernel pages
  2766. are much bigger, so we don't care (on i386) */
  2767. /* workaround for 440MX */
  2768. if (chip->fix_nocache)
  2769. fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
  2770. int_sta_masks = 0;
  2771. for (i = 0; i < chip->bdbars_count; i++) {
  2772. ichdev = &chip->ichd[i];
  2773. ichdev->bdbar = ((u32 *)chip->bdbars.area) +
  2774. (i * ICH_MAX_FRAGS * 2);
  2775. ichdev->bdbar_addr = chip->bdbars.addr +
  2776. (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
  2777. int_sta_masks |= ichdev->int_sta_mask;
  2778. }
  2779. chip->int_sta_reg = device_type == DEVICE_ALI ?
  2780. ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
  2781. chip->int_sta_mask = int_sta_masks;
  2782. pci_set_master(pci);
  2783. switch(chip->device_type) {
  2784. case DEVICE_INTEL_ICH4:
  2785. /* ICH4 can have three codecs */
  2786. chip->max_codecs = 3;
  2787. chip->codec_bit = ich_codec_bits;
  2788. chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
  2789. break;
  2790. case DEVICE_SIS:
  2791. /* recent SIS7012 can have three codecs */
  2792. chip->max_codecs = 3;
  2793. chip->codec_bit = sis_codec_bits;
  2794. chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
  2795. break;
  2796. default:
  2797. /* others up to two codecs */
  2798. chip->max_codecs = 2;
  2799. chip->codec_bit = ich_codec_bits;
  2800. chip->codec_ready_bits = ICH_PRI | ICH_SRI;
  2801. break;
  2802. }
  2803. for (i = 0; i < chip->max_codecs; i++)
  2804. chip->codec_isr_bits |= chip->codec_bit[i];
  2805. if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
  2806. snd_intel8x0_free(chip);
  2807. return err;
  2808. }
  2809. /* request irq after initializaing int_sta_mask, etc */
  2810. if (request_irq(pci->irq, snd_intel8x0_interrupt,
  2811. IRQF_SHARED, card->shortname, chip)) {
  2812. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  2813. snd_intel8x0_free(chip);
  2814. return -EBUSY;
  2815. }
  2816. chip->irq = pci->irq;
  2817. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  2818. snd_intel8x0_free(chip);
  2819. return err;
  2820. }
  2821. snd_card_set_dev(card, &pci->dev);
  2822. *r_intel8x0 = chip;
  2823. return 0;
  2824. }
  2825. static struct shortname_table {
  2826. unsigned int id;
  2827. const char *s;
  2828. } shortnames[] __devinitdata = {
  2829. { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
  2830. { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
  2831. { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
  2832. { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
  2833. { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
  2834. { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
  2835. { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
  2836. { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
  2837. { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
  2838. { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
  2839. { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
  2840. { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
  2841. { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
  2842. { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
  2843. { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
  2844. { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
  2845. { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
  2846. { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
  2847. { 0x003a, "NVidia MCP04" },
  2848. { 0x746d, "AMD AMD8111" },
  2849. { 0x7445, "AMD AMD768" },
  2850. { 0x5455, "ALi M5455" },
  2851. { 0, NULL },
  2852. };
  2853. static struct snd_pci_quirk spdif_aclink_defaults[] __devinitdata = {
  2854. SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
  2855. { } /* end */
  2856. };
  2857. /* look up white/black list for SPDIF over ac-link */
  2858. static int __devinit check_default_spdif_aclink(struct pci_dev *pci)
  2859. {
  2860. const struct snd_pci_quirk *w;
  2861. w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
  2862. if (w) {
  2863. if (w->value)
  2864. snd_printdd(KERN_INFO "intel8x0: Using SPDIF over "
  2865. "AC-Link for %s\n", w->name);
  2866. else
  2867. snd_printdd(KERN_INFO "intel8x0: Using integrated "
  2868. "SPDIF DMA for %s\n", w->name);
  2869. return w->value;
  2870. }
  2871. return 0;
  2872. }
  2873. static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
  2874. const struct pci_device_id *pci_id)
  2875. {
  2876. struct snd_card *card;
  2877. struct intel8x0 *chip;
  2878. int err;
  2879. struct shortname_table *name;
  2880. err = snd_card_create(index, id, THIS_MODULE, 0, &card);
  2881. if (err < 0)
  2882. return err;
  2883. if (spdif_aclink < 0)
  2884. spdif_aclink = check_default_spdif_aclink(pci);
  2885. strcpy(card->driver, "ICH");
  2886. if (!spdif_aclink) {
  2887. switch (pci_id->driver_data) {
  2888. case DEVICE_NFORCE:
  2889. strcpy(card->driver, "NFORCE");
  2890. break;
  2891. case DEVICE_INTEL_ICH4:
  2892. strcpy(card->driver, "ICH4");
  2893. }
  2894. }
  2895. strcpy(card->shortname, "Intel ICH");
  2896. for (name = shortnames; name->id; name++) {
  2897. if (pci->device == name->id) {
  2898. strcpy(card->shortname, name->s);
  2899. break;
  2900. }
  2901. }
  2902. if (buggy_irq < 0) {
  2903. /* some Nforce[2] and ICH boards have problems with IRQ handling.
  2904. * Needs to return IRQ_HANDLED for unknown irqs.
  2905. */
  2906. if (pci_id->driver_data == DEVICE_NFORCE)
  2907. buggy_irq = 1;
  2908. else
  2909. buggy_irq = 0;
  2910. }
  2911. if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
  2912. &chip)) < 0) {
  2913. snd_card_free(card);
  2914. return err;
  2915. }
  2916. card->private_data = chip;
  2917. if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
  2918. snd_card_free(card);
  2919. return err;
  2920. }
  2921. if ((err = snd_intel8x0_pcm(chip)) < 0) {
  2922. snd_card_free(card);
  2923. return err;
  2924. }
  2925. snd_intel8x0_proc_init(chip);
  2926. snprintf(card->longname, sizeof(card->longname),
  2927. "%s with %s at irq %i", card->shortname,
  2928. snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
  2929. if (ac97_clock == 0 || ac97_clock == 1) {
  2930. if (ac97_clock == 0) {
  2931. if (intel8x0_in_clock_list(chip) == 0)
  2932. intel8x0_measure_ac97_clock(chip);
  2933. } else {
  2934. intel8x0_measure_ac97_clock(chip);
  2935. }
  2936. }
  2937. if ((err = snd_card_register(card)) < 0) {
  2938. snd_card_free(card);
  2939. return err;
  2940. }
  2941. pci_set_drvdata(pci, card);
  2942. return 0;
  2943. }
  2944. static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
  2945. {
  2946. snd_card_free(pci_get_drvdata(pci));
  2947. pci_set_drvdata(pci, NULL);
  2948. }
  2949. static struct pci_driver driver = {
  2950. .name = "Intel ICH",
  2951. .id_table = snd_intel8x0_ids,
  2952. .probe = snd_intel8x0_probe,
  2953. .remove = __devexit_p(snd_intel8x0_remove),
  2954. #ifdef CONFIG_PM
  2955. .suspend = intel8x0_suspend,
  2956. .resume = intel8x0_resume,
  2957. #endif
  2958. };
  2959. static int __init alsa_card_intel8x0_init(void)
  2960. {
  2961. return pci_register_driver(&driver);
  2962. }
  2963. static void __exit alsa_card_intel8x0_exit(void)
  2964. {
  2965. pci_unregister_driver(&driver);
  2966. }
  2967. module_init(alsa_card_intel8x0_init)
  2968. module_exit(alsa_card_intel8x0_exit)