fm801.c 46 KB

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  1. /*
  2. * The driver for the ForteMedia FM801 based soundcards
  3. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  4. *
  5. * Support FM only card by Andy Shevchenko <andy@smile.org.ua>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. *
  21. */
  22. #include <linux/delay.h>
  23. #include <linux/init.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/pci.h>
  26. #include <linux/slab.h>
  27. #include <linux/moduleparam.h>
  28. #include <sound/core.h>
  29. #include <sound/pcm.h>
  30. #include <sound/tlv.h>
  31. #include <sound/ac97_codec.h>
  32. #include <sound/mpu401.h>
  33. #include <sound/opl3.h>
  34. #include <sound/initval.h>
  35. #include <asm/io.h>
  36. #ifdef CONFIG_SND_FM801_TEA575X_BOOL
  37. #include <sound/tea575x-tuner.h>
  38. #define TEA575X_RADIO 1
  39. #endif
  40. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  41. MODULE_DESCRIPTION("ForteMedia FM801");
  42. MODULE_LICENSE("GPL");
  43. MODULE_SUPPORTED_DEVICE("{{ForteMedia,FM801},"
  44. "{Genius,SoundMaker Live 5.1}}");
  45. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  46. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  47. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  48. /*
  49. * Enable TEA575x tuner
  50. * 1 = MediaForte 256-PCS
  51. * 2 = MediaForte 256-PCPR
  52. * 3 = MediaForte 64-PCR
  53. * 16 = setup tuner only (this is additional bit), i.e. SF-64-PCR FM card
  54. * High 16-bits are video (radio) device number + 1
  55. */
  56. static int tea575x_tuner[SNDRV_CARDS];
  57. module_param_array(index, int, NULL, 0444);
  58. MODULE_PARM_DESC(index, "Index value for the FM801 soundcard.");
  59. module_param_array(id, charp, NULL, 0444);
  60. MODULE_PARM_DESC(id, "ID string for the FM801 soundcard.");
  61. module_param_array(enable, bool, NULL, 0444);
  62. MODULE_PARM_DESC(enable, "Enable FM801 soundcard.");
  63. module_param_array(tea575x_tuner, int, NULL, 0444);
  64. MODULE_PARM_DESC(tea575x_tuner, "Enable TEA575x tuner.");
  65. /*
  66. * Direct registers
  67. */
  68. #define FM801_REG(chip, reg) (chip->port + FM801_##reg)
  69. #define FM801_PCM_VOL 0x00 /* PCM Output Volume */
  70. #define FM801_FM_VOL 0x02 /* FM Output Volume */
  71. #define FM801_I2S_VOL 0x04 /* I2S Volume */
  72. #define FM801_REC_SRC 0x06 /* Record Source */
  73. #define FM801_PLY_CTRL 0x08 /* Playback Control */
  74. #define FM801_PLY_COUNT 0x0a /* Playback Count */
  75. #define FM801_PLY_BUF1 0x0c /* Playback Bufer I */
  76. #define FM801_PLY_BUF2 0x10 /* Playback Buffer II */
  77. #define FM801_CAP_CTRL 0x14 /* Capture Control */
  78. #define FM801_CAP_COUNT 0x16 /* Capture Count */
  79. #define FM801_CAP_BUF1 0x18 /* Capture Buffer I */
  80. #define FM801_CAP_BUF2 0x1c /* Capture Buffer II */
  81. #define FM801_CODEC_CTRL 0x22 /* Codec Control */
  82. #define FM801_I2S_MODE 0x24 /* I2S Mode Control */
  83. #define FM801_VOLUME 0x26 /* Volume Up/Down/Mute Status */
  84. #define FM801_I2C_CTRL 0x29 /* I2C Control */
  85. #define FM801_AC97_CMD 0x2a /* AC'97 Command */
  86. #define FM801_AC97_DATA 0x2c /* AC'97 Data */
  87. #define FM801_MPU401_DATA 0x30 /* MPU401 Data */
  88. #define FM801_MPU401_CMD 0x31 /* MPU401 Command */
  89. #define FM801_GPIO_CTRL 0x52 /* General Purpose I/O Control */
  90. #define FM801_GEN_CTRL 0x54 /* General Control */
  91. #define FM801_IRQ_MASK 0x56 /* Interrupt Mask */
  92. #define FM801_IRQ_STATUS 0x5a /* Interrupt Status */
  93. #define FM801_OPL3_BANK0 0x68 /* OPL3 Status Read / Bank 0 Write */
  94. #define FM801_OPL3_DATA0 0x69 /* OPL3 Data 0 Write */
  95. #define FM801_OPL3_BANK1 0x6a /* OPL3 Bank 1 Write */
  96. #define FM801_OPL3_DATA1 0x6b /* OPL3 Bank 1 Write */
  97. #define FM801_POWERDOWN 0x70 /* Blocks Power Down Control */
  98. /* codec access */
  99. #define FM801_AC97_READ (1<<7) /* read=1, write=0 */
  100. #define FM801_AC97_VALID (1<<8) /* port valid=1 */
  101. #define FM801_AC97_BUSY (1<<9) /* busy=1 */
  102. #define FM801_AC97_ADDR_SHIFT 10 /* codec id (2bit) */
  103. /* playback and record control register bits */
  104. #define FM801_BUF1_LAST (1<<1)
  105. #define FM801_BUF2_LAST (1<<2)
  106. #define FM801_START (1<<5)
  107. #define FM801_PAUSE (1<<6)
  108. #define FM801_IMMED_STOP (1<<7)
  109. #define FM801_RATE_SHIFT 8
  110. #define FM801_RATE_MASK (15 << FM801_RATE_SHIFT)
  111. #define FM801_CHANNELS_4 (1<<12) /* playback only */
  112. #define FM801_CHANNELS_6 (2<<12) /* playback only */
  113. #define FM801_CHANNELS_6MS (3<<12) /* playback only */
  114. #define FM801_CHANNELS_MASK (3<<12)
  115. #define FM801_16BIT (1<<14)
  116. #define FM801_STEREO (1<<15)
  117. /* IRQ status bits */
  118. #define FM801_IRQ_PLAYBACK (1<<8)
  119. #define FM801_IRQ_CAPTURE (1<<9)
  120. #define FM801_IRQ_VOLUME (1<<14)
  121. #define FM801_IRQ_MPU (1<<15)
  122. /* GPIO control register */
  123. #define FM801_GPIO_GP0 (1<<0) /* read/write */
  124. #define FM801_GPIO_GP1 (1<<1)
  125. #define FM801_GPIO_GP2 (1<<2)
  126. #define FM801_GPIO_GP3 (1<<3)
  127. #define FM801_GPIO_GP(x) (1<<(0+(x)))
  128. #define FM801_GPIO_GD0 (1<<8) /* directions: 1 = input, 0 = output*/
  129. #define FM801_GPIO_GD1 (1<<9)
  130. #define FM801_GPIO_GD2 (1<<10)
  131. #define FM801_GPIO_GD3 (1<<11)
  132. #define FM801_GPIO_GD(x) (1<<(8+(x)))
  133. #define FM801_GPIO_GS0 (1<<12) /* function select: */
  134. #define FM801_GPIO_GS1 (1<<13) /* 1 = GPIO */
  135. #define FM801_GPIO_GS2 (1<<14) /* 0 = other (S/PDIF, VOL) */
  136. #define FM801_GPIO_GS3 (1<<15)
  137. #define FM801_GPIO_GS(x) (1<<(12+(x)))
  138. /*
  139. */
  140. struct fm801 {
  141. int irq;
  142. unsigned long port; /* I/O port number */
  143. unsigned int multichannel: 1, /* multichannel support */
  144. secondary: 1; /* secondary codec */
  145. unsigned char secondary_addr; /* address of the secondary codec */
  146. unsigned int tea575x_tuner; /* tuner flags */
  147. unsigned short ply_ctrl; /* playback control */
  148. unsigned short cap_ctrl; /* capture control */
  149. unsigned long ply_buffer;
  150. unsigned int ply_buf;
  151. unsigned int ply_count;
  152. unsigned int ply_size;
  153. unsigned int ply_pos;
  154. unsigned long cap_buffer;
  155. unsigned int cap_buf;
  156. unsigned int cap_count;
  157. unsigned int cap_size;
  158. unsigned int cap_pos;
  159. struct snd_ac97_bus *ac97_bus;
  160. struct snd_ac97 *ac97;
  161. struct snd_ac97 *ac97_sec;
  162. struct pci_dev *pci;
  163. struct snd_card *card;
  164. struct snd_pcm *pcm;
  165. struct snd_rawmidi *rmidi;
  166. struct snd_pcm_substream *playback_substream;
  167. struct snd_pcm_substream *capture_substream;
  168. unsigned int p_dma_size;
  169. unsigned int c_dma_size;
  170. spinlock_t reg_lock;
  171. struct snd_info_entry *proc_entry;
  172. #ifdef TEA575X_RADIO
  173. struct snd_tea575x tea;
  174. #endif
  175. #ifdef CONFIG_PM
  176. u16 saved_regs[0x20];
  177. #endif
  178. };
  179. static struct pci_device_id snd_fm801_ids[] = {
  180. { 0x1319, 0x0801, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0, }, /* FM801 */
  181. { 0x5213, 0x0510, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0, }, /* Gallant Odyssey Sound 4 */
  182. { 0, }
  183. };
  184. MODULE_DEVICE_TABLE(pci, snd_fm801_ids);
  185. /*
  186. * common I/O routines
  187. */
  188. static int snd_fm801_update_bits(struct fm801 *chip, unsigned short reg,
  189. unsigned short mask, unsigned short value)
  190. {
  191. int change;
  192. unsigned long flags;
  193. unsigned short old, new;
  194. spin_lock_irqsave(&chip->reg_lock, flags);
  195. old = inw(chip->port + reg);
  196. new = (old & ~mask) | value;
  197. change = old != new;
  198. if (change)
  199. outw(new, chip->port + reg);
  200. spin_unlock_irqrestore(&chip->reg_lock, flags);
  201. return change;
  202. }
  203. static void snd_fm801_codec_write(struct snd_ac97 *ac97,
  204. unsigned short reg,
  205. unsigned short val)
  206. {
  207. struct fm801 *chip = ac97->private_data;
  208. int idx;
  209. /*
  210. * Wait until the codec interface is not ready..
  211. */
  212. for (idx = 0; idx < 100; idx++) {
  213. if (!(inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_BUSY))
  214. goto ok1;
  215. udelay(10);
  216. }
  217. snd_printk(KERN_ERR "AC'97 interface is busy (1)\n");
  218. return;
  219. ok1:
  220. /* write data and address */
  221. outw(val, FM801_REG(chip, AC97_DATA));
  222. outw(reg | (ac97->addr << FM801_AC97_ADDR_SHIFT), FM801_REG(chip, AC97_CMD));
  223. /*
  224. * Wait until the write command is not completed..
  225. */
  226. for (idx = 0; idx < 1000; idx++) {
  227. if (!(inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_BUSY))
  228. return;
  229. udelay(10);
  230. }
  231. snd_printk(KERN_ERR "AC'97 interface #%d is busy (2)\n", ac97->num);
  232. }
  233. static unsigned short snd_fm801_codec_read(struct snd_ac97 *ac97, unsigned short reg)
  234. {
  235. struct fm801 *chip = ac97->private_data;
  236. int idx;
  237. /*
  238. * Wait until the codec interface is not ready..
  239. */
  240. for (idx = 0; idx < 100; idx++) {
  241. if (!(inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_BUSY))
  242. goto ok1;
  243. udelay(10);
  244. }
  245. snd_printk(KERN_ERR "AC'97 interface is busy (1)\n");
  246. return 0;
  247. ok1:
  248. /* read command */
  249. outw(reg | (ac97->addr << FM801_AC97_ADDR_SHIFT) | FM801_AC97_READ,
  250. FM801_REG(chip, AC97_CMD));
  251. for (idx = 0; idx < 100; idx++) {
  252. if (!(inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_BUSY))
  253. goto ok2;
  254. udelay(10);
  255. }
  256. snd_printk(KERN_ERR "AC'97 interface #%d is busy (2)\n", ac97->num);
  257. return 0;
  258. ok2:
  259. for (idx = 0; idx < 1000; idx++) {
  260. if (inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_VALID)
  261. goto ok3;
  262. udelay(10);
  263. }
  264. snd_printk(KERN_ERR "AC'97 interface #%d is not valid (2)\n", ac97->num);
  265. return 0;
  266. ok3:
  267. return inw(FM801_REG(chip, AC97_DATA));
  268. }
  269. static unsigned int rates[] = {
  270. 5500, 8000, 9600, 11025,
  271. 16000, 19200, 22050, 32000,
  272. 38400, 44100, 48000
  273. };
  274. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  275. .count = ARRAY_SIZE(rates),
  276. .list = rates,
  277. .mask = 0,
  278. };
  279. static unsigned int channels[] = {
  280. 2, 4, 6
  281. };
  282. static struct snd_pcm_hw_constraint_list hw_constraints_channels = {
  283. .count = ARRAY_SIZE(channels),
  284. .list = channels,
  285. .mask = 0,
  286. };
  287. /*
  288. * Sample rate routines
  289. */
  290. static unsigned short snd_fm801_rate_bits(unsigned int rate)
  291. {
  292. unsigned int idx;
  293. for (idx = 0; idx < ARRAY_SIZE(rates); idx++)
  294. if (rates[idx] == rate)
  295. return idx;
  296. snd_BUG();
  297. return ARRAY_SIZE(rates) - 1;
  298. }
  299. /*
  300. * PCM part
  301. */
  302. static int snd_fm801_playback_trigger(struct snd_pcm_substream *substream,
  303. int cmd)
  304. {
  305. struct fm801 *chip = snd_pcm_substream_chip(substream);
  306. spin_lock(&chip->reg_lock);
  307. switch (cmd) {
  308. case SNDRV_PCM_TRIGGER_START:
  309. chip->ply_ctrl &= ~(FM801_BUF1_LAST |
  310. FM801_BUF2_LAST |
  311. FM801_PAUSE);
  312. chip->ply_ctrl |= FM801_START |
  313. FM801_IMMED_STOP;
  314. break;
  315. case SNDRV_PCM_TRIGGER_STOP:
  316. chip->ply_ctrl &= ~(FM801_START | FM801_PAUSE);
  317. break;
  318. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  319. case SNDRV_PCM_TRIGGER_SUSPEND:
  320. chip->ply_ctrl |= FM801_PAUSE;
  321. break;
  322. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  323. case SNDRV_PCM_TRIGGER_RESUME:
  324. chip->ply_ctrl &= ~FM801_PAUSE;
  325. break;
  326. default:
  327. spin_unlock(&chip->reg_lock);
  328. snd_BUG();
  329. return -EINVAL;
  330. }
  331. outw(chip->ply_ctrl, FM801_REG(chip, PLY_CTRL));
  332. spin_unlock(&chip->reg_lock);
  333. return 0;
  334. }
  335. static int snd_fm801_capture_trigger(struct snd_pcm_substream *substream,
  336. int cmd)
  337. {
  338. struct fm801 *chip = snd_pcm_substream_chip(substream);
  339. spin_lock(&chip->reg_lock);
  340. switch (cmd) {
  341. case SNDRV_PCM_TRIGGER_START:
  342. chip->cap_ctrl &= ~(FM801_BUF1_LAST |
  343. FM801_BUF2_LAST |
  344. FM801_PAUSE);
  345. chip->cap_ctrl |= FM801_START |
  346. FM801_IMMED_STOP;
  347. break;
  348. case SNDRV_PCM_TRIGGER_STOP:
  349. chip->cap_ctrl &= ~(FM801_START | FM801_PAUSE);
  350. break;
  351. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  352. case SNDRV_PCM_TRIGGER_SUSPEND:
  353. chip->cap_ctrl |= FM801_PAUSE;
  354. break;
  355. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  356. case SNDRV_PCM_TRIGGER_RESUME:
  357. chip->cap_ctrl &= ~FM801_PAUSE;
  358. break;
  359. default:
  360. spin_unlock(&chip->reg_lock);
  361. snd_BUG();
  362. return -EINVAL;
  363. }
  364. outw(chip->cap_ctrl, FM801_REG(chip, CAP_CTRL));
  365. spin_unlock(&chip->reg_lock);
  366. return 0;
  367. }
  368. static int snd_fm801_hw_params(struct snd_pcm_substream *substream,
  369. struct snd_pcm_hw_params *hw_params)
  370. {
  371. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  372. }
  373. static int snd_fm801_hw_free(struct snd_pcm_substream *substream)
  374. {
  375. return snd_pcm_lib_free_pages(substream);
  376. }
  377. static int snd_fm801_playback_prepare(struct snd_pcm_substream *substream)
  378. {
  379. struct fm801 *chip = snd_pcm_substream_chip(substream);
  380. struct snd_pcm_runtime *runtime = substream->runtime;
  381. chip->ply_size = snd_pcm_lib_buffer_bytes(substream);
  382. chip->ply_count = snd_pcm_lib_period_bytes(substream);
  383. spin_lock_irq(&chip->reg_lock);
  384. chip->ply_ctrl &= ~(FM801_START | FM801_16BIT |
  385. FM801_STEREO | FM801_RATE_MASK |
  386. FM801_CHANNELS_MASK);
  387. if (snd_pcm_format_width(runtime->format) == 16)
  388. chip->ply_ctrl |= FM801_16BIT;
  389. if (runtime->channels > 1) {
  390. chip->ply_ctrl |= FM801_STEREO;
  391. if (runtime->channels == 4)
  392. chip->ply_ctrl |= FM801_CHANNELS_4;
  393. else if (runtime->channels == 6)
  394. chip->ply_ctrl |= FM801_CHANNELS_6;
  395. }
  396. chip->ply_ctrl |= snd_fm801_rate_bits(runtime->rate) << FM801_RATE_SHIFT;
  397. chip->ply_buf = 0;
  398. outw(chip->ply_ctrl, FM801_REG(chip, PLY_CTRL));
  399. outw(chip->ply_count - 1, FM801_REG(chip, PLY_COUNT));
  400. chip->ply_buffer = runtime->dma_addr;
  401. chip->ply_pos = 0;
  402. outl(chip->ply_buffer, FM801_REG(chip, PLY_BUF1));
  403. outl(chip->ply_buffer + (chip->ply_count % chip->ply_size), FM801_REG(chip, PLY_BUF2));
  404. spin_unlock_irq(&chip->reg_lock);
  405. return 0;
  406. }
  407. static int snd_fm801_capture_prepare(struct snd_pcm_substream *substream)
  408. {
  409. struct fm801 *chip = snd_pcm_substream_chip(substream);
  410. struct snd_pcm_runtime *runtime = substream->runtime;
  411. chip->cap_size = snd_pcm_lib_buffer_bytes(substream);
  412. chip->cap_count = snd_pcm_lib_period_bytes(substream);
  413. spin_lock_irq(&chip->reg_lock);
  414. chip->cap_ctrl &= ~(FM801_START | FM801_16BIT |
  415. FM801_STEREO | FM801_RATE_MASK);
  416. if (snd_pcm_format_width(runtime->format) == 16)
  417. chip->cap_ctrl |= FM801_16BIT;
  418. if (runtime->channels > 1)
  419. chip->cap_ctrl |= FM801_STEREO;
  420. chip->cap_ctrl |= snd_fm801_rate_bits(runtime->rate) << FM801_RATE_SHIFT;
  421. chip->cap_buf = 0;
  422. outw(chip->cap_ctrl, FM801_REG(chip, CAP_CTRL));
  423. outw(chip->cap_count - 1, FM801_REG(chip, CAP_COUNT));
  424. chip->cap_buffer = runtime->dma_addr;
  425. chip->cap_pos = 0;
  426. outl(chip->cap_buffer, FM801_REG(chip, CAP_BUF1));
  427. outl(chip->cap_buffer + (chip->cap_count % chip->cap_size), FM801_REG(chip, CAP_BUF2));
  428. spin_unlock_irq(&chip->reg_lock);
  429. return 0;
  430. }
  431. static snd_pcm_uframes_t snd_fm801_playback_pointer(struct snd_pcm_substream *substream)
  432. {
  433. struct fm801 *chip = snd_pcm_substream_chip(substream);
  434. size_t ptr;
  435. if (!(chip->ply_ctrl & FM801_START))
  436. return 0;
  437. spin_lock(&chip->reg_lock);
  438. ptr = chip->ply_pos + (chip->ply_count - 1) - inw(FM801_REG(chip, PLY_COUNT));
  439. if (inw(FM801_REG(chip, IRQ_STATUS)) & FM801_IRQ_PLAYBACK) {
  440. ptr += chip->ply_count;
  441. ptr %= chip->ply_size;
  442. }
  443. spin_unlock(&chip->reg_lock);
  444. return bytes_to_frames(substream->runtime, ptr);
  445. }
  446. static snd_pcm_uframes_t snd_fm801_capture_pointer(struct snd_pcm_substream *substream)
  447. {
  448. struct fm801 *chip = snd_pcm_substream_chip(substream);
  449. size_t ptr;
  450. if (!(chip->cap_ctrl & FM801_START))
  451. return 0;
  452. spin_lock(&chip->reg_lock);
  453. ptr = chip->cap_pos + (chip->cap_count - 1) - inw(FM801_REG(chip, CAP_COUNT));
  454. if (inw(FM801_REG(chip, IRQ_STATUS)) & FM801_IRQ_CAPTURE) {
  455. ptr += chip->cap_count;
  456. ptr %= chip->cap_size;
  457. }
  458. spin_unlock(&chip->reg_lock);
  459. return bytes_to_frames(substream->runtime, ptr);
  460. }
  461. static irqreturn_t snd_fm801_interrupt(int irq, void *dev_id)
  462. {
  463. struct fm801 *chip = dev_id;
  464. unsigned short status;
  465. unsigned int tmp;
  466. status = inw(FM801_REG(chip, IRQ_STATUS));
  467. status &= FM801_IRQ_PLAYBACK|FM801_IRQ_CAPTURE|FM801_IRQ_MPU|FM801_IRQ_VOLUME;
  468. if (! status)
  469. return IRQ_NONE;
  470. /* ack first */
  471. outw(status, FM801_REG(chip, IRQ_STATUS));
  472. if (chip->pcm && (status & FM801_IRQ_PLAYBACK) && chip->playback_substream) {
  473. spin_lock(&chip->reg_lock);
  474. chip->ply_buf++;
  475. chip->ply_pos += chip->ply_count;
  476. chip->ply_pos %= chip->ply_size;
  477. tmp = chip->ply_pos + chip->ply_count;
  478. tmp %= chip->ply_size;
  479. outl(chip->ply_buffer + tmp,
  480. (chip->ply_buf & 1) ?
  481. FM801_REG(chip, PLY_BUF1) :
  482. FM801_REG(chip, PLY_BUF2));
  483. spin_unlock(&chip->reg_lock);
  484. snd_pcm_period_elapsed(chip->playback_substream);
  485. }
  486. if (chip->pcm && (status & FM801_IRQ_CAPTURE) && chip->capture_substream) {
  487. spin_lock(&chip->reg_lock);
  488. chip->cap_buf++;
  489. chip->cap_pos += chip->cap_count;
  490. chip->cap_pos %= chip->cap_size;
  491. tmp = chip->cap_pos + chip->cap_count;
  492. tmp %= chip->cap_size;
  493. outl(chip->cap_buffer + tmp,
  494. (chip->cap_buf & 1) ?
  495. FM801_REG(chip, CAP_BUF1) :
  496. FM801_REG(chip, CAP_BUF2));
  497. spin_unlock(&chip->reg_lock);
  498. snd_pcm_period_elapsed(chip->capture_substream);
  499. }
  500. if (chip->rmidi && (status & FM801_IRQ_MPU))
  501. snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
  502. if (status & FM801_IRQ_VOLUME)
  503. ;/* TODO */
  504. return IRQ_HANDLED;
  505. }
  506. static struct snd_pcm_hardware snd_fm801_playback =
  507. {
  508. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  509. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  510. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME |
  511. SNDRV_PCM_INFO_MMAP_VALID),
  512. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  513. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  514. .rate_min = 5500,
  515. .rate_max = 48000,
  516. .channels_min = 1,
  517. .channels_max = 2,
  518. .buffer_bytes_max = (128*1024),
  519. .period_bytes_min = 64,
  520. .period_bytes_max = (128*1024),
  521. .periods_min = 1,
  522. .periods_max = 1024,
  523. .fifo_size = 0,
  524. };
  525. static struct snd_pcm_hardware snd_fm801_capture =
  526. {
  527. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  528. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  529. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME |
  530. SNDRV_PCM_INFO_MMAP_VALID),
  531. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  532. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  533. .rate_min = 5500,
  534. .rate_max = 48000,
  535. .channels_min = 1,
  536. .channels_max = 2,
  537. .buffer_bytes_max = (128*1024),
  538. .period_bytes_min = 64,
  539. .period_bytes_max = (128*1024),
  540. .periods_min = 1,
  541. .periods_max = 1024,
  542. .fifo_size = 0,
  543. };
  544. static int snd_fm801_playback_open(struct snd_pcm_substream *substream)
  545. {
  546. struct fm801 *chip = snd_pcm_substream_chip(substream);
  547. struct snd_pcm_runtime *runtime = substream->runtime;
  548. int err;
  549. chip->playback_substream = substream;
  550. runtime->hw = snd_fm801_playback;
  551. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  552. &hw_constraints_rates);
  553. if (chip->multichannel) {
  554. runtime->hw.channels_max = 6;
  555. snd_pcm_hw_constraint_list(runtime, 0,
  556. SNDRV_PCM_HW_PARAM_CHANNELS,
  557. &hw_constraints_channels);
  558. }
  559. if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
  560. return err;
  561. return 0;
  562. }
  563. static int snd_fm801_capture_open(struct snd_pcm_substream *substream)
  564. {
  565. struct fm801 *chip = snd_pcm_substream_chip(substream);
  566. struct snd_pcm_runtime *runtime = substream->runtime;
  567. int err;
  568. chip->capture_substream = substream;
  569. runtime->hw = snd_fm801_capture;
  570. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  571. &hw_constraints_rates);
  572. if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
  573. return err;
  574. return 0;
  575. }
  576. static int snd_fm801_playback_close(struct snd_pcm_substream *substream)
  577. {
  578. struct fm801 *chip = snd_pcm_substream_chip(substream);
  579. chip->playback_substream = NULL;
  580. return 0;
  581. }
  582. static int snd_fm801_capture_close(struct snd_pcm_substream *substream)
  583. {
  584. struct fm801 *chip = snd_pcm_substream_chip(substream);
  585. chip->capture_substream = NULL;
  586. return 0;
  587. }
  588. static struct snd_pcm_ops snd_fm801_playback_ops = {
  589. .open = snd_fm801_playback_open,
  590. .close = snd_fm801_playback_close,
  591. .ioctl = snd_pcm_lib_ioctl,
  592. .hw_params = snd_fm801_hw_params,
  593. .hw_free = snd_fm801_hw_free,
  594. .prepare = snd_fm801_playback_prepare,
  595. .trigger = snd_fm801_playback_trigger,
  596. .pointer = snd_fm801_playback_pointer,
  597. };
  598. static struct snd_pcm_ops snd_fm801_capture_ops = {
  599. .open = snd_fm801_capture_open,
  600. .close = snd_fm801_capture_close,
  601. .ioctl = snd_pcm_lib_ioctl,
  602. .hw_params = snd_fm801_hw_params,
  603. .hw_free = snd_fm801_hw_free,
  604. .prepare = snd_fm801_capture_prepare,
  605. .trigger = snd_fm801_capture_trigger,
  606. .pointer = snd_fm801_capture_pointer,
  607. };
  608. static int __devinit snd_fm801_pcm(struct fm801 *chip, int device, struct snd_pcm ** rpcm)
  609. {
  610. struct snd_pcm *pcm;
  611. int err;
  612. if (rpcm)
  613. *rpcm = NULL;
  614. if ((err = snd_pcm_new(chip->card, "FM801", device, 1, 1, &pcm)) < 0)
  615. return err;
  616. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_fm801_playback_ops);
  617. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_fm801_capture_ops);
  618. pcm->private_data = chip;
  619. pcm->info_flags = 0;
  620. strcpy(pcm->name, "FM801");
  621. chip->pcm = pcm;
  622. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  623. snd_dma_pci_data(chip->pci),
  624. chip->multichannel ? 128*1024 : 64*1024, 128*1024);
  625. if (rpcm)
  626. *rpcm = pcm;
  627. return 0;
  628. }
  629. /*
  630. * TEA5757 radio
  631. */
  632. #ifdef TEA575X_RADIO
  633. /* 256PCS GPIO numbers */
  634. #define TEA_256PCS_DATA 1
  635. #define TEA_256PCS_WRITE_ENABLE 2 /* inverted */
  636. #define TEA_256PCS_BUS_CLOCK 3
  637. static void snd_fm801_tea575x_256pcs_write(struct snd_tea575x *tea, unsigned int val)
  638. {
  639. struct fm801 *chip = tea->private_data;
  640. unsigned short reg;
  641. int i = 25;
  642. spin_lock_irq(&chip->reg_lock);
  643. reg = inw(FM801_REG(chip, GPIO_CTRL));
  644. /* use GPIO lines and set write enable bit */
  645. reg |= FM801_GPIO_GS(TEA_256PCS_DATA) |
  646. FM801_GPIO_GS(TEA_256PCS_WRITE_ENABLE) |
  647. FM801_GPIO_GS(TEA_256PCS_BUS_CLOCK);
  648. /* all of lines are in the write direction */
  649. /* clear data and clock lines */
  650. reg &= ~(FM801_GPIO_GD(TEA_256PCS_DATA) |
  651. FM801_GPIO_GD(TEA_256PCS_WRITE_ENABLE) |
  652. FM801_GPIO_GD(TEA_256PCS_BUS_CLOCK) |
  653. FM801_GPIO_GP(TEA_256PCS_DATA) |
  654. FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK) |
  655. FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE));
  656. outw(reg, FM801_REG(chip, GPIO_CTRL));
  657. udelay(1);
  658. while (i--) {
  659. if (val & (1 << i))
  660. reg |= FM801_GPIO_GP(TEA_256PCS_DATA);
  661. else
  662. reg &= ~FM801_GPIO_GP(TEA_256PCS_DATA);
  663. outw(reg, FM801_REG(chip, GPIO_CTRL));
  664. udelay(1);
  665. reg |= FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
  666. outw(reg, FM801_REG(chip, GPIO_CTRL));
  667. reg &= ~FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
  668. outw(reg, FM801_REG(chip, GPIO_CTRL));
  669. udelay(1);
  670. }
  671. /* and reset the write enable bit */
  672. reg |= FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE) |
  673. FM801_GPIO_GP(TEA_256PCS_DATA);
  674. outw(reg, FM801_REG(chip, GPIO_CTRL));
  675. spin_unlock_irq(&chip->reg_lock);
  676. }
  677. static unsigned int snd_fm801_tea575x_256pcs_read(struct snd_tea575x *tea)
  678. {
  679. struct fm801 *chip = tea->private_data;
  680. unsigned short reg;
  681. unsigned int val = 0;
  682. int i;
  683. spin_lock_irq(&chip->reg_lock);
  684. reg = inw(FM801_REG(chip, GPIO_CTRL));
  685. /* use GPIO lines, set data direction to input */
  686. reg |= FM801_GPIO_GS(TEA_256PCS_DATA) |
  687. FM801_GPIO_GS(TEA_256PCS_WRITE_ENABLE) |
  688. FM801_GPIO_GS(TEA_256PCS_BUS_CLOCK) |
  689. FM801_GPIO_GD(TEA_256PCS_DATA) |
  690. FM801_GPIO_GP(TEA_256PCS_DATA) |
  691. FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE);
  692. /* all of lines are in the write direction, except data */
  693. /* clear data, write enable and clock lines */
  694. reg &= ~(FM801_GPIO_GD(TEA_256PCS_WRITE_ENABLE) |
  695. FM801_GPIO_GD(TEA_256PCS_BUS_CLOCK) |
  696. FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK));
  697. for (i = 0; i < 24; i++) {
  698. reg &= ~FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
  699. outw(reg, FM801_REG(chip, GPIO_CTRL));
  700. udelay(1);
  701. reg |= FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
  702. outw(reg, FM801_REG(chip, GPIO_CTRL));
  703. udelay(1);
  704. val <<= 1;
  705. if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_256PCS_DATA))
  706. val |= 1;
  707. }
  708. spin_unlock_irq(&chip->reg_lock);
  709. return val;
  710. }
  711. /* 256PCPR GPIO numbers */
  712. #define TEA_256PCPR_BUS_CLOCK 0
  713. #define TEA_256PCPR_DATA 1
  714. #define TEA_256PCPR_WRITE_ENABLE 2 /* inverted */
  715. static void snd_fm801_tea575x_256pcpr_write(struct snd_tea575x *tea, unsigned int val)
  716. {
  717. struct fm801 *chip = tea->private_data;
  718. unsigned short reg;
  719. int i = 25;
  720. spin_lock_irq(&chip->reg_lock);
  721. reg = inw(FM801_REG(chip, GPIO_CTRL));
  722. /* use GPIO lines and set write enable bit */
  723. reg |= FM801_GPIO_GS(TEA_256PCPR_DATA) |
  724. FM801_GPIO_GS(TEA_256PCPR_WRITE_ENABLE) |
  725. FM801_GPIO_GS(TEA_256PCPR_BUS_CLOCK);
  726. /* all of lines are in the write direction */
  727. /* clear data and clock lines */
  728. reg &= ~(FM801_GPIO_GD(TEA_256PCPR_DATA) |
  729. FM801_GPIO_GD(TEA_256PCPR_WRITE_ENABLE) |
  730. FM801_GPIO_GD(TEA_256PCPR_BUS_CLOCK) |
  731. FM801_GPIO_GP(TEA_256PCPR_DATA) |
  732. FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK) |
  733. FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE));
  734. outw(reg, FM801_REG(chip, GPIO_CTRL));
  735. udelay(1);
  736. while (i--) {
  737. if (val & (1 << i))
  738. reg |= FM801_GPIO_GP(TEA_256PCPR_DATA);
  739. else
  740. reg &= ~FM801_GPIO_GP(TEA_256PCPR_DATA);
  741. outw(reg, FM801_REG(chip, GPIO_CTRL));
  742. udelay(1);
  743. reg |= FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
  744. outw(reg, FM801_REG(chip, GPIO_CTRL));
  745. reg &= ~FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
  746. outw(reg, FM801_REG(chip, GPIO_CTRL));
  747. udelay(1);
  748. }
  749. /* and reset the write enable bit */
  750. reg |= FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE) |
  751. FM801_GPIO_GP(TEA_256PCPR_DATA);
  752. outw(reg, FM801_REG(chip, GPIO_CTRL));
  753. spin_unlock_irq(&chip->reg_lock);
  754. }
  755. static unsigned int snd_fm801_tea575x_256pcpr_read(struct snd_tea575x *tea)
  756. {
  757. struct fm801 *chip = tea->private_data;
  758. unsigned short reg;
  759. unsigned int val = 0;
  760. int i;
  761. spin_lock_irq(&chip->reg_lock);
  762. reg = inw(FM801_REG(chip, GPIO_CTRL));
  763. /* use GPIO lines, set data direction to input */
  764. reg |= FM801_GPIO_GS(TEA_256PCPR_DATA) |
  765. FM801_GPIO_GS(TEA_256PCPR_WRITE_ENABLE) |
  766. FM801_GPIO_GS(TEA_256PCPR_BUS_CLOCK) |
  767. FM801_GPIO_GD(TEA_256PCPR_DATA) |
  768. FM801_GPIO_GP(TEA_256PCPR_DATA) |
  769. FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE);
  770. /* all of lines are in the write direction, except data */
  771. /* clear data, write enable and clock lines */
  772. reg &= ~(FM801_GPIO_GD(TEA_256PCPR_WRITE_ENABLE) |
  773. FM801_GPIO_GD(TEA_256PCPR_BUS_CLOCK) |
  774. FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK));
  775. for (i = 0; i < 24; i++) {
  776. reg &= ~FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
  777. outw(reg, FM801_REG(chip, GPIO_CTRL));
  778. udelay(1);
  779. reg |= FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
  780. outw(reg, FM801_REG(chip, GPIO_CTRL));
  781. udelay(1);
  782. val <<= 1;
  783. if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_256PCPR_DATA))
  784. val |= 1;
  785. }
  786. spin_unlock_irq(&chip->reg_lock);
  787. return val;
  788. }
  789. /* 64PCR GPIO numbers */
  790. #define TEA_64PCR_BUS_CLOCK 0
  791. #define TEA_64PCR_WRITE_ENABLE 1 /* inverted */
  792. #define TEA_64PCR_DATA 2
  793. static void snd_fm801_tea575x_64pcr_write(struct snd_tea575x *tea, unsigned int val)
  794. {
  795. struct fm801 *chip = tea->private_data;
  796. unsigned short reg;
  797. int i = 25;
  798. spin_lock_irq(&chip->reg_lock);
  799. reg = inw(FM801_REG(chip, GPIO_CTRL));
  800. /* use GPIO lines and set write enable bit */
  801. reg |= FM801_GPIO_GS(TEA_64PCR_DATA) |
  802. FM801_GPIO_GS(TEA_64PCR_WRITE_ENABLE) |
  803. FM801_GPIO_GS(TEA_64PCR_BUS_CLOCK);
  804. /* all of lines are in the write direction */
  805. /* clear data and clock lines */
  806. reg &= ~(FM801_GPIO_GD(TEA_64PCR_DATA) |
  807. FM801_GPIO_GD(TEA_64PCR_WRITE_ENABLE) |
  808. FM801_GPIO_GD(TEA_64PCR_BUS_CLOCK) |
  809. FM801_GPIO_GP(TEA_64PCR_DATA) |
  810. FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK) |
  811. FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE));
  812. outw(reg, FM801_REG(chip, GPIO_CTRL));
  813. udelay(1);
  814. while (i--) {
  815. if (val & (1 << i))
  816. reg |= FM801_GPIO_GP(TEA_64PCR_DATA);
  817. else
  818. reg &= ~FM801_GPIO_GP(TEA_64PCR_DATA);
  819. outw(reg, FM801_REG(chip, GPIO_CTRL));
  820. udelay(1);
  821. reg |= FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
  822. outw(reg, FM801_REG(chip, GPIO_CTRL));
  823. reg &= ~FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
  824. outw(reg, FM801_REG(chip, GPIO_CTRL));
  825. udelay(1);
  826. }
  827. /* and reset the write enable bit */
  828. reg |= FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE) |
  829. FM801_GPIO_GP(TEA_64PCR_DATA);
  830. outw(reg, FM801_REG(chip, GPIO_CTRL));
  831. spin_unlock_irq(&chip->reg_lock);
  832. }
  833. static unsigned int snd_fm801_tea575x_64pcr_read(struct snd_tea575x *tea)
  834. {
  835. struct fm801 *chip = tea->private_data;
  836. unsigned short reg;
  837. unsigned int val = 0;
  838. int i;
  839. spin_lock_irq(&chip->reg_lock);
  840. reg = inw(FM801_REG(chip, GPIO_CTRL));
  841. /* use GPIO lines, set data direction to input */
  842. reg |= FM801_GPIO_GS(TEA_64PCR_DATA) |
  843. FM801_GPIO_GS(TEA_64PCR_WRITE_ENABLE) |
  844. FM801_GPIO_GS(TEA_64PCR_BUS_CLOCK) |
  845. FM801_GPIO_GD(TEA_64PCR_DATA) |
  846. FM801_GPIO_GP(TEA_64PCR_DATA) |
  847. FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE);
  848. /* all of lines are in the write direction, except data */
  849. /* clear data, write enable and clock lines */
  850. reg &= ~(FM801_GPIO_GD(TEA_64PCR_WRITE_ENABLE) |
  851. FM801_GPIO_GD(TEA_64PCR_BUS_CLOCK) |
  852. FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK));
  853. for (i = 0; i < 24; i++) {
  854. reg &= ~FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
  855. outw(reg, FM801_REG(chip, GPIO_CTRL));
  856. udelay(1);
  857. reg |= FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
  858. outw(reg, FM801_REG(chip, GPIO_CTRL));
  859. udelay(1);
  860. val <<= 1;
  861. if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_64PCR_DATA))
  862. val |= 1;
  863. }
  864. spin_unlock_irq(&chip->reg_lock);
  865. return val;
  866. }
  867. static void snd_fm801_tea575x_64pcr_mute(struct snd_tea575x *tea,
  868. unsigned int mute)
  869. {
  870. struct fm801 *chip = tea->private_data;
  871. unsigned short reg;
  872. spin_lock_irq(&chip->reg_lock);
  873. reg = inw(FM801_REG(chip, GPIO_CTRL));
  874. if (mute)
  875. /* 0xf800 (mute) */
  876. reg &= ~FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE);
  877. else
  878. /* 0xf802 (unmute) */
  879. reg |= FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE);
  880. outw(reg, FM801_REG(chip, GPIO_CTRL));
  881. udelay(1);
  882. spin_unlock_irq(&chip->reg_lock);
  883. }
  884. static struct snd_tea575x_ops snd_fm801_tea_ops[3] = {
  885. {
  886. /* 1 = MediaForte 256-PCS */
  887. .write = snd_fm801_tea575x_256pcs_write,
  888. .read = snd_fm801_tea575x_256pcs_read,
  889. },
  890. {
  891. /* 2 = MediaForte 256-PCPR */
  892. .write = snd_fm801_tea575x_256pcpr_write,
  893. .read = snd_fm801_tea575x_256pcpr_read,
  894. },
  895. {
  896. /* 3 = MediaForte 64-PCR */
  897. .write = snd_fm801_tea575x_64pcr_write,
  898. .read = snd_fm801_tea575x_64pcr_read,
  899. .mute = snd_fm801_tea575x_64pcr_mute,
  900. }
  901. };
  902. #endif
  903. /*
  904. * Mixer routines
  905. */
  906. #define FM801_SINGLE(xname, reg, shift, mask, invert) \
  907. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_fm801_info_single, \
  908. .get = snd_fm801_get_single, .put = snd_fm801_put_single, \
  909. .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
  910. static int snd_fm801_info_single(struct snd_kcontrol *kcontrol,
  911. struct snd_ctl_elem_info *uinfo)
  912. {
  913. int mask = (kcontrol->private_value >> 16) & 0xff;
  914. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  915. uinfo->count = 1;
  916. uinfo->value.integer.min = 0;
  917. uinfo->value.integer.max = mask;
  918. return 0;
  919. }
  920. static int snd_fm801_get_single(struct snd_kcontrol *kcontrol,
  921. struct snd_ctl_elem_value *ucontrol)
  922. {
  923. struct fm801 *chip = snd_kcontrol_chip(kcontrol);
  924. int reg = kcontrol->private_value & 0xff;
  925. int shift = (kcontrol->private_value >> 8) & 0xff;
  926. int mask = (kcontrol->private_value >> 16) & 0xff;
  927. int invert = (kcontrol->private_value >> 24) & 0xff;
  928. ucontrol->value.integer.value[0] = (inw(chip->port + reg) >> shift) & mask;
  929. if (invert)
  930. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  931. return 0;
  932. }
  933. static int snd_fm801_put_single(struct snd_kcontrol *kcontrol,
  934. struct snd_ctl_elem_value *ucontrol)
  935. {
  936. struct fm801 *chip = snd_kcontrol_chip(kcontrol);
  937. int reg = kcontrol->private_value & 0xff;
  938. int shift = (kcontrol->private_value >> 8) & 0xff;
  939. int mask = (kcontrol->private_value >> 16) & 0xff;
  940. int invert = (kcontrol->private_value >> 24) & 0xff;
  941. unsigned short val;
  942. val = (ucontrol->value.integer.value[0] & mask);
  943. if (invert)
  944. val = mask - val;
  945. return snd_fm801_update_bits(chip, reg, mask << shift, val << shift);
  946. }
  947. #define FM801_DOUBLE(xname, reg, shift_left, shift_right, mask, invert) \
  948. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_fm801_info_double, \
  949. .get = snd_fm801_get_double, .put = snd_fm801_put_double, \
  950. .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24) }
  951. #define FM801_DOUBLE_TLV(xname, reg, shift_left, shift_right, mask, invert, xtlv) \
  952. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
  953. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
  954. .name = xname, .info = snd_fm801_info_double, \
  955. .get = snd_fm801_get_double, .put = snd_fm801_put_double, \
  956. .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24), \
  957. .tlv = { .p = (xtlv) } }
  958. static int snd_fm801_info_double(struct snd_kcontrol *kcontrol,
  959. struct snd_ctl_elem_info *uinfo)
  960. {
  961. int mask = (kcontrol->private_value >> 16) & 0xff;
  962. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  963. uinfo->count = 2;
  964. uinfo->value.integer.min = 0;
  965. uinfo->value.integer.max = mask;
  966. return 0;
  967. }
  968. static int snd_fm801_get_double(struct snd_kcontrol *kcontrol,
  969. struct snd_ctl_elem_value *ucontrol)
  970. {
  971. struct fm801 *chip = snd_kcontrol_chip(kcontrol);
  972. int reg = kcontrol->private_value & 0xff;
  973. int shift_left = (kcontrol->private_value >> 8) & 0x0f;
  974. int shift_right = (kcontrol->private_value >> 12) & 0x0f;
  975. int mask = (kcontrol->private_value >> 16) & 0xff;
  976. int invert = (kcontrol->private_value >> 24) & 0xff;
  977. spin_lock_irq(&chip->reg_lock);
  978. ucontrol->value.integer.value[0] = (inw(chip->port + reg) >> shift_left) & mask;
  979. ucontrol->value.integer.value[1] = (inw(chip->port + reg) >> shift_right) & mask;
  980. spin_unlock_irq(&chip->reg_lock);
  981. if (invert) {
  982. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  983. ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
  984. }
  985. return 0;
  986. }
  987. static int snd_fm801_put_double(struct snd_kcontrol *kcontrol,
  988. struct snd_ctl_elem_value *ucontrol)
  989. {
  990. struct fm801 *chip = snd_kcontrol_chip(kcontrol);
  991. int reg = kcontrol->private_value & 0xff;
  992. int shift_left = (kcontrol->private_value >> 8) & 0x0f;
  993. int shift_right = (kcontrol->private_value >> 12) & 0x0f;
  994. int mask = (kcontrol->private_value >> 16) & 0xff;
  995. int invert = (kcontrol->private_value >> 24) & 0xff;
  996. unsigned short val1, val2;
  997. val1 = ucontrol->value.integer.value[0] & mask;
  998. val2 = ucontrol->value.integer.value[1] & mask;
  999. if (invert) {
  1000. val1 = mask - val1;
  1001. val2 = mask - val2;
  1002. }
  1003. return snd_fm801_update_bits(chip, reg,
  1004. (mask << shift_left) | (mask << shift_right),
  1005. (val1 << shift_left ) | (val2 << shift_right));
  1006. }
  1007. static int snd_fm801_info_mux(struct snd_kcontrol *kcontrol,
  1008. struct snd_ctl_elem_info *uinfo)
  1009. {
  1010. static char *texts[5] = {
  1011. "AC97 Primary", "FM", "I2S", "PCM", "AC97 Secondary"
  1012. };
  1013. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1014. uinfo->count = 1;
  1015. uinfo->value.enumerated.items = 5;
  1016. if (uinfo->value.enumerated.item > 4)
  1017. uinfo->value.enumerated.item = 4;
  1018. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1019. return 0;
  1020. }
  1021. static int snd_fm801_get_mux(struct snd_kcontrol *kcontrol,
  1022. struct snd_ctl_elem_value *ucontrol)
  1023. {
  1024. struct fm801 *chip = snd_kcontrol_chip(kcontrol);
  1025. unsigned short val;
  1026. val = inw(FM801_REG(chip, REC_SRC)) & 7;
  1027. if (val > 4)
  1028. val = 4;
  1029. ucontrol->value.enumerated.item[0] = val;
  1030. return 0;
  1031. }
  1032. static int snd_fm801_put_mux(struct snd_kcontrol *kcontrol,
  1033. struct snd_ctl_elem_value *ucontrol)
  1034. {
  1035. struct fm801 *chip = snd_kcontrol_chip(kcontrol);
  1036. unsigned short val;
  1037. if ((val = ucontrol->value.enumerated.item[0]) > 4)
  1038. return -EINVAL;
  1039. return snd_fm801_update_bits(chip, FM801_REC_SRC, 7, val);
  1040. }
  1041. static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -3450, 150, 0);
  1042. #define FM801_CONTROLS ARRAY_SIZE(snd_fm801_controls)
  1043. static struct snd_kcontrol_new snd_fm801_controls[] __devinitdata = {
  1044. FM801_DOUBLE_TLV("Wave Playback Volume", FM801_PCM_VOL, 0, 8, 31, 1,
  1045. db_scale_dsp),
  1046. FM801_SINGLE("Wave Playback Switch", FM801_PCM_VOL, 15, 1, 1),
  1047. FM801_DOUBLE_TLV("I2S Playback Volume", FM801_I2S_VOL, 0, 8, 31, 1,
  1048. db_scale_dsp),
  1049. FM801_SINGLE("I2S Playback Switch", FM801_I2S_VOL, 15, 1, 1),
  1050. FM801_DOUBLE_TLV("FM Playback Volume", FM801_FM_VOL, 0, 8, 31, 1,
  1051. db_scale_dsp),
  1052. FM801_SINGLE("FM Playback Switch", FM801_FM_VOL, 15, 1, 1),
  1053. {
  1054. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1055. .name = "Digital Capture Source",
  1056. .info = snd_fm801_info_mux,
  1057. .get = snd_fm801_get_mux,
  1058. .put = snd_fm801_put_mux,
  1059. }
  1060. };
  1061. #define FM801_CONTROLS_MULTI ARRAY_SIZE(snd_fm801_controls_multi)
  1062. static struct snd_kcontrol_new snd_fm801_controls_multi[] __devinitdata = {
  1063. FM801_SINGLE("AC97 2ch->4ch Copy Switch", FM801_CODEC_CTRL, 7, 1, 0),
  1064. FM801_SINGLE("AC97 18-bit Switch", FM801_CODEC_CTRL, 10, 1, 0),
  1065. FM801_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), FM801_I2S_MODE, 8, 1, 0),
  1066. FM801_SINGLE(SNDRV_CTL_NAME_IEC958("Raw Data ",PLAYBACK,SWITCH), FM801_I2S_MODE, 9, 1, 0),
  1067. FM801_SINGLE(SNDRV_CTL_NAME_IEC958("Raw Data ",CAPTURE,SWITCH), FM801_I2S_MODE, 10, 1, 0),
  1068. FM801_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), FM801_GEN_CTRL, 2, 1, 0),
  1069. };
  1070. static void snd_fm801_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
  1071. {
  1072. struct fm801 *chip = bus->private_data;
  1073. chip->ac97_bus = NULL;
  1074. }
  1075. static void snd_fm801_mixer_free_ac97(struct snd_ac97 *ac97)
  1076. {
  1077. struct fm801 *chip = ac97->private_data;
  1078. if (ac97->num == 0) {
  1079. chip->ac97 = NULL;
  1080. } else {
  1081. chip->ac97_sec = NULL;
  1082. }
  1083. }
  1084. static int __devinit snd_fm801_mixer(struct fm801 *chip)
  1085. {
  1086. struct snd_ac97_template ac97;
  1087. unsigned int i;
  1088. int err;
  1089. static struct snd_ac97_bus_ops ops = {
  1090. .write = snd_fm801_codec_write,
  1091. .read = snd_fm801_codec_read,
  1092. };
  1093. if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
  1094. return err;
  1095. chip->ac97_bus->private_free = snd_fm801_mixer_free_ac97_bus;
  1096. memset(&ac97, 0, sizeof(ac97));
  1097. ac97.private_data = chip;
  1098. ac97.private_free = snd_fm801_mixer_free_ac97;
  1099. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
  1100. return err;
  1101. if (chip->secondary) {
  1102. ac97.num = 1;
  1103. ac97.addr = chip->secondary_addr;
  1104. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_sec)) < 0)
  1105. return err;
  1106. }
  1107. for (i = 0; i < FM801_CONTROLS; i++)
  1108. snd_ctl_add(chip->card, snd_ctl_new1(&snd_fm801_controls[i], chip));
  1109. if (chip->multichannel) {
  1110. for (i = 0; i < FM801_CONTROLS_MULTI; i++)
  1111. snd_ctl_add(chip->card, snd_ctl_new1(&snd_fm801_controls_multi[i], chip));
  1112. }
  1113. return 0;
  1114. }
  1115. /*
  1116. * initialization routines
  1117. */
  1118. static int wait_for_codec(struct fm801 *chip, unsigned int codec_id,
  1119. unsigned short reg, unsigned long waits)
  1120. {
  1121. unsigned long timeout = jiffies + waits;
  1122. outw(FM801_AC97_READ | (codec_id << FM801_AC97_ADDR_SHIFT) | reg,
  1123. FM801_REG(chip, AC97_CMD));
  1124. udelay(5);
  1125. do {
  1126. if ((inw(FM801_REG(chip, AC97_CMD)) & (FM801_AC97_VALID|FM801_AC97_BUSY))
  1127. == FM801_AC97_VALID)
  1128. return 0;
  1129. schedule_timeout_uninterruptible(1);
  1130. } while (time_after(timeout, jiffies));
  1131. return -EIO;
  1132. }
  1133. static int snd_fm801_chip_init(struct fm801 *chip, int resume)
  1134. {
  1135. unsigned short cmdw;
  1136. if (chip->tea575x_tuner & 0x0010)
  1137. goto __ac97_ok;
  1138. /* codec cold reset + AC'97 warm reset */
  1139. outw((1<<5) | (1<<6), FM801_REG(chip, CODEC_CTRL));
  1140. inw(FM801_REG(chip, CODEC_CTRL)); /* flush posting data */
  1141. udelay(100);
  1142. outw(0, FM801_REG(chip, CODEC_CTRL));
  1143. if (wait_for_codec(chip, 0, AC97_RESET, msecs_to_jiffies(750)) < 0) {
  1144. snd_printk(KERN_ERR "Primary AC'97 codec not found\n");
  1145. if (! resume)
  1146. return -EIO;
  1147. }
  1148. if (chip->multichannel) {
  1149. if (chip->secondary_addr) {
  1150. wait_for_codec(chip, chip->secondary_addr,
  1151. AC97_VENDOR_ID1, msecs_to_jiffies(50));
  1152. } else {
  1153. /* my card has the secondary codec */
  1154. /* at address #3, so the loop is inverted */
  1155. int i;
  1156. for (i = 3; i > 0; i--) {
  1157. if (!wait_for_codec(chip, i, AC97_VENDOR_ID1,
  1158. msecs_to_jiffies(50))) {
  1159. cmdw = inw(FM801_REG(chip, AC97_DATA));
  1160. if (cmdw != 0xffff && cmdw != 0) {
  1161. chip->secondary = 1;
  1162. chip->secondary_addr = i;
  1163. break;
  1164. }
  1165. }
  1166. }
  1167. }
  1168. /* the recovery phase, it seems that probing for non-existing codec might */
  1169. /* cause timeout problems */
  1170. wait_for_codec(chip, 0, AC97_VENDOR_ID1, msecs_to_jiffies(750));
  1171. }
  1172. __ac97_ok:
  1173. /* init volume */
  1174. outw(0x0808, FM801_REG(chip, PCM_VOL));
  1175. outw(0x9f1f, FM801_REG(chip, FM_VOL));
  1176. outw(0x8808, FM801_REG(chip, I2S_VOL));
  1177. /* I2S control - I2S mode */
  1178. outw(0x0003, FM801_REG(chip, I2S_MODE));
  1179. /* interrupt setup */
  1180. cmdw = inw(FM801_REG(chip, IRQ_MASK));
  1181. if (chip->irq < 0)
  1182. cmdw |= 0x00c3; /* mask everything, no PCM nor MPU */
  1183. else
  1184. cmdw &= ~0x0083; /* unmask MPU, PLAYBACK & CAPTURE */
  1185. outw(cmdw, FM801_REG(chip, IRQ_MASK));
  1186. /* interrupt clear */
  1187. outw(FM801_IRQ_PLAYBACK|FM801_IRQ_CAPTURE|FM801_IRQ_MPU, FM801_REG(chip, IRQ_STATUS));
  1188. return 0;
  1189. }
  1190. static int snd_fm801_free(struct fm801 *chip)
  1191. {
  1192. unsigned short cmdw;
  1193. if (chip->irq < 0)
  1194. goto __end_hw;
  1195. /* interrupt setup - mask everything */
  1196. cmdw = inw(FM801_REG(chip, IRQ_MASK));
  1197. cmdw |= 0x00c3;
  1198. outw(cmdw, FM801_REG(chip, IRQ_MASK));
  1199. __end_hw:
  1200. #ifdef TEA575X_RADIO
  1201. snd_tea575x_exit(&chip->tea);
  1202. #endif
  1203. if (chip->irq >= 0)
  1204. free_irq(chip->irq, chip);
  1205. pci_release_regions(chip->pci);
  1206. pci_disable_device(chip->pci);
  1207. kfree(chip);
  1208. return 0;
  1209. }
  1210. static int snd_fm801_dev_free(struct snd_device *device)
  1211. {
  1212. struct fm801 *chip = device->device_data;
  1213. return snd_fm801_free(chip);
  1214. }
  1215. static int __devinit snd_fm801_create(struct snd_card *card,
  1216. struct pci_dev * pci,
  1217. int tea575x_tuner,
  1218. struct fm801 ** rchip)
  1219. {
  1220. struct fm801 *chip;
  1221. int err;
  1222. static struct snd_device_ops ops = {
  1223. .dev_free = snd_fm801_dev_free,
  1224. };
  1225. *rchip = NULL;
  1226. if ((err = pci_enable_device(pci)) < 0)
  1227. return err;
  1228. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1229. if (chip == NULL) {
  1230. pci_disable_device(pci);
  1231. return -ENOMEM;
  1232. }
  1233. spin_lock_init(&chip->reg_lock);
  1234. chip->card = card;
  1235. chip->pci = pci;
  1236. chip->irq = -1;
  1237. chip->tea575x_tuner = tea575x_tuner;
  1238. if ((err = pci_request_regions(pci, "FM801")) < 0) {
  1239. kfree(chip);
  1240. pci_disable_device(pci);
  1241. return err;
  1242. }
  1243. chip->port = pci_resource_start(pci, 0);
  1244. if ((tea575x_tuner & 0x0010) == 0) {
  1245. if (request_irq(pci->irq, snd_fm801_interrupt, IRQF_SHARED,
  1246. "FM801", chip)) {
  1247. snd_printk(KERN_ERR "unable to grab IRQ %d\n", chip->irq);
  1248. snd_fm801_free(chip);
  1249. return -EBUSY;
  1250. }
  1251. chip->irq = pci->irq;
  1252. pci_set_master(pci);
  1253. }
  1254. if (pci->revision >= 0xb1) /* FM801-AU */
  1255. chip->multichannel = 1;
  1256. snd_fm801_chip_init(chip, 0);
  1257. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1258. snd_fm801_free(chip);
  1259. return err;
  1260. }
  1261. snd_card_set_dev(card, &pci->dev);
  1262. #ifdef TEA575X_RADIO
  1263. if (tea575x_tuner > 0 && (tea575x_tuner & 0x000f) < 4) {
  1264. chip->tea.dev_nr = tea575x_tuner >> 16;
  1265. chip->tea.card = card;
  1266. chip->tea.freq_fixup = 10700;
  1267. chip->tea.private_data = chip;
  1268. chip->tea.ops = &snd_fm801_tea_ops[(tea575x_tuner & 0x000f) - 1];
  1269. snd_tea575x_init(&chip->tea);
  1270. }
  1271. #endif
  1272. *rchip = chip;
  1273. return 0;
  1274. }
  1275. static int __devinit snd_card_fm801_probe(struct pci_dev *pci,
  1276. const struct pci_device_id *pci_id)
  1277. {
  1278. static int dev;
  1279. struct snd_card *card;
  1280. struct fm801 *chip;
  1281. struct snd_opl3 *opl3;
  1282. int err;
  1283. if (dev >= SNDRV_CARDS)
  1284. return -ENODEV;
  1285. if (!enable[dev]) {
  1286. dev++;
  1287. return -ENOENT;
  1288. }
  1289. err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
  1290. if (err < 0)
  1291. return err;
  1292. if ((err = snd_fm801_create(card, pci, tea575x_tuner[dev], &chip)) < 0) {
  1293. snd_card_free(card);
  1294. return err;
  1295. }
  1296. card->private_data = chip;
  1297. strcpy(card->driver, "FM801");
  1298. strcpy(card->shortname, "ForteMedia FM801-");
  1299. strcat(card->shortname, chip->multichannel ? "AU" : "AS");
  1300. sprintf(card->longname, "%s at 0x%lx, irq %i",
  1301. card->shortname, chip->port, chip->irq);
  1302. if (tea575x_tuner[dev] & 0x0010)
  1303. goto __fm801_tuner_only;
  1304. if ((err = snd_fm801_pcm(chip, 0, NULL)) < 0) {
  1305. snd_card_free(card);
  1306. return err;
  1307. }
  1308. if ((err = snd_fm801_mixer(chip)) < 0) {
  1309. snd_card_free(card);
  1310. return err;
  1311. }
  1312. if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_FM801,
  1313. FM801_REG(chip, MPU401_DATA),
  1314. MPU401_INFO_INTEGRATED,
  1315. chip->irq, 0, &chip->rmidi)) < 0) {
  1316. snd_card_free(card);
  1317. return err;
  1318. }
  1319. if ((err = snd_opl3_create(card, FM801_REG(chip, OPL3_BANK0),
  1320. FM801_REG(chip, OPL3_BANK1),
  1321. OPL3_HW_OPL3_FM801, 1, &opl3)) < 0) {
  1322. snd_card_free(card);
  1323. return err;
  1324. }
  1325. if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
  1326. snd_card_free(card);
  1327. return err;
  1328. }
  1329. __fm801_tuner_only:
  1330. if ((err = snd_card_register(card)) < 0) {
  1331. snd_card_free(card);
  1332. return err;
  1333. }
  1334. pci_set_drvdata(pci, card);
  1335. dev++;
  1336. return 0;
  1337. }
  1338. static void __devexit snd_card_fm801_remove(struct pci_dev *pci)
  1339. {
  1340. snd_card_free(pci_get_drvdata(pci));
  1341. pci_set_drvdata(pci, NULL);
  1342. }
  1343. #ifdef CONFIG_PM
  1344. static unsigned char saved_regs[] = {
  1345. FM801_PCM_VOL, FM801_I2S_VOL, FM801_FM_VOL, FM801_REC_SRC,
  1346. FM801_PLY_CTRL, FM801_PLY_COUNT, FM801_PLY_BUF1, FM801_PLY_BUF2,
  1347. FM801_CAP_CTRL, FM801_CAP_COUNT, FM801_CAP_BUF1, FM801_CAP_BUF2,
  1348. FM801_CODEC_CTRL, FM801_I2S_MODE, FM801_VOLUME, FM801_GEN_CTRL,
  1349. };
  1350. static int snd_fm801_suspend(struct pci_dev *pci, pm_message_t state)
  1351. {
  1352. struct snd_card *card = pci_get_drvdata(pci);
  1353. struct fm801 *chip = card->private_data;
  1354. int i;
  1355. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  1356. snd_pcm_suspend_all(chip->pcm);
  1357. snd_ac97_suspend(chip->ac97);
  1358. snd_ac97_suspend(chip->ac97_sec);
  1359. for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
  1360. chip->saved_regs[i] = inw(chip->port + saved_regs[i]);
  1361. /* FIXME: tea575x suspend */
  1362. pci_disable_device(pci);
  1363. pci_save_state(pci);
  1364. pci_set_power_state(pci, pci_choose_state(pci, state));
  1365. return 0;
  1366. }
  1367. static int snd_fm801_resume(struct pci_dev *pci)
  1368. {
  1369. struct snd_card *card = pci_get_drvdata(pci);
  1370. struct fm801 *chip = card->private_data;
  1371. int i;
  1372. pci_set_power_state(pci, PCI_D0);
  1373. pci_restore_state(pci);
  1374. if (pci_enable_device(pci) < 0) {
  1375. printk(KERN_ERR "fm801: pci_enable_device failed, "
  1376. "disabling device\n");
  1377. snd_card_disconnect(card);
  1378. return -EIO;
  1379. }
  1380. pci_set_master(pci);
  1381. snd_fm801_chip_init(chip, 1);
  1382. snd_ac97_resume(chip->ac97);
  1383. snd_ac97_resume(chip->ac97_sec);
  1384. for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
  1385. outw(chip->saved_regs[i], chip->port + saved_regs[i]);
  1386. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  1387. return 0;
  1388. }
  1389. #endif
  1390. static struct pci_driver driver = {
  1391. .name = "FM801",
  1392. .id_table = snd_fm801_ids,
  1393. .probe = snd_card_fm801_probe,
  1394. .remove = __devexit_p(snd_card_fm801_remove),
  1395. #ifdef CONFIG_PM
  1396. .suspend = snd_fm801_suspend,
  1397. .resume = snd_fm801_resume,
  1398. #endif
  1399. };
  1400. static int __init alsa_card_fm801_init(void)
  1401. {
  1402. return pci_register_driver(&driver);
  1403. }
  1404. static void __exit alsa_card_fm801_exit(void)
  1405. {
  1406. pci_unregister_driver(&driver);
  1407. }
  1408. module_init(alsa_card_fm801_init)
  1409. module_exit(alsa_card_fm801_exit)