dsp_spos_scb_lib.c 48 KB

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  1. /*
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License as published by
  5. * the Free Software Foundation; either version 2 of the License, or
  6. * (at your option) any later version.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  16. *
  17. */
  18. /*
  19. * 2002-07 Benny Sjostrand benny@hostmobility.com
  20. */
  21. #include <asm/io.h>
  22. #include <linux/delay.h>
  23. #include <linux/pm.h>
  24. #include <linux/init.h>
  25. #include <linux/slab.h>
  26. #include <linux/mutex.h>
  27. #include <sound/core.h>
  28. #include <sound/control.h>
  29. #include <sound/info.h>
  30. #include <sound/cs46xx.h>
  31. #include "cs46xx_lib.h"
  32. #include "dsp_spos.h"
  33. struct proc_scb_info {
  34. struct dsp_scb_descriptor * scb_desc;
  35. struct snd_cs46xx *chip;
  36. };
  37. static void remove_symbol (struct snd_cs46xx * chip, struct dsp_symbol_entry * symbol)
  38. {
  39. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  40. int symbol_index = (int)(symbol - ins->symbol_table.symbols);
  41. if (snd_BUG_ON(ins->symbol_table.nsymbols <= 0))
  42. return;
  43. if (snd_BUG_ON(symbol_index < 0 ||
  44. symbol_index >= ins->symbol_table.nsymbols))
  45. return;
  46. ins->symbol_table.symbols[symbol_index].deleted = 1;
  47. if (symbol_index < ins->symbol_table.highest_frag_index) {
  48. ins->symbol_table.highest_frag_index = symbol_index;
  49. }
  50. if (symbol_index == ins->symbol_table.nsymbols - 1)
  51. ins->symbol_table.nsymbols --;
  52. if (ins->symbol_table.highest_frag_index > ins->symbol_table.nsymbols) {
  53. ins->symbol_table.highest_frag_index = ins->symbol_table.nsymbols;
  54. }
  55. }
  56. #ifdef CONFIG_PROC_FS
  57. static void cs46xx_dsp_proc_scb_info_read (struct snd_info_entry *entry,
  58. struct snd_info_buffer *buffer)
  59. {
  60. struct proc_scb_info * scb_info = entry->private_data;
  61. struct dsp_scb_descriptor * scb = scb_info->scb_desc;
  62. struct dsp_spos_instance * ins;
  63. struct snd_cs46xx *chip = scb_info->chip;
  64. int j,col;
  65. void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
  66. ins = chip->dsp_spos_instance;
  67. mutex_lock(&chip->spos_mutex);
  68. snd_iprintf(buffer,"%04x %s:\n",scb->address,scb->scb_name);
  69. for (col = 0,j = 0;j < 0x10; j++,col++) {
  70. if (col == 4) {
  71. snd_iprintf(buffer,"\n");
  72. col = 0;
  73. }
  74. snd_iprintf(buffer,"%08x ",readl(dst + (scb->address + j) * sizeof(u32)));
  75. }
  76. snd_iprintf(buffer,"\n");
  77. if (scb->parent_scb_ptr != NULL) {
  78. snd_iprintf(buffer,"parent [%s:%04x] ",
  79. scb->parent_scb_ptr->scb_name,
  80. scb->parent_scb_ptr->address);
  81. } else snd_iprintf(buffer,"parent [none] ");
  82. snd_iprintf(buffer,"sub_list_ptr [%s:%04x]\nnext_scb_ptr [%s:%04x] task_entry [%s:%04x]\n",
  83. scb->sub_list_ptr->scb_name,
  84. scb->sub_list_ptr->address,
  85. scb->next_scb_ptr->scb_name,
  86. scb->next_scb_ptr->address,
  87. scb->task_entry->symbol_name,
  88. scb->task_entry->address);
  89. snd_iprintf(buffer,"index [%d] ref_count [%d]\n",scb->index,scb->ref_count);
  90. mutex_unlock(&chip->spos_mutex);
  91. }
  92. #endif
  93. static void _dsp_unlink_scb (struct snd_cs46xx *chip, struct dsp_scb_descriptor * scb)
  94. {
  95. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  96. unsigned long flags;
  97. if ( scb->parent_scb_ptr ) {
  98. /* unlink parent SCB */
  99. if (snd_BUG_ON(scb->parent_scb_ptr->sub_list_ptr != scb &&
  100. scb->parent_scb_ptr->next_scb_ptr != scb))
  101. return;
  102. if (scb->parent_scb_ptr->sub_list_ptr == scb) {
  103. if (scb->next_scb_ptr == ins->the_null_scb) {
  104. /* last and only node in parent sublist */
  105. scb->parent_scb_ptr->sub_list_ptr = scb->sub_list_ptr;
  106. if (scb->sub_list_ptr != ins->the_null_scb) {
  107. scb->sub_list_ptr->parent_scb_ptr = scb->parent_scb_ptr;
  108. }
  109. scb->sub_list_ptr = ins->the_null_scb;
  110. } else {
  111. /* first node in parent sublist */
  112. scb->parent_scb_ptr->sub_list_ptr = scb->next_scb_ptr;
  113. if (scb->next_scb_ptr != ins->the_null_scb) {
  114. /* update next node parent ptr. */
  115. scb->next_scb_ptr->parent_scb_ptr = scb->parent_scb_ptr;
  116. }
  117. scb->next_scb_ptr = ins->the_null_scb;
  118. }
  119. } else {
  120. scb->parent_scb_ptr->next_scb_ptr = scb->next_scb_ptr;
  121. if (scb->next_scb_ptr != ins->the_null_scb) {
  122. /* update next node parent ptr. */
  123. scb->next_scb_ptr->parent_scb_ptr = scb->parent_scb_ptr;
  124. }
  125. scb->next_scb_ptr = ins->the_null_scb;
  126. }
  127. spin_lock_irqsave(&chip->reg_lock, flags);
  128. /* update parent first entry in DSP RAM */
  129. cs46xx_dsp_spos_update_scb(chip,scb->parent_scb_ptr);
  130. /* then update entry in DSP RAM */
  131. cs46xx_dsp_spos_update_scb(chip,scb);
  132. scb->parent_scb_ptr = NULL;
  133. spin_unlock_irqrestore(&chip->reg_lock, flags);
  134. }
  135. }
  136. static void _dsp_clear_sample_buffer (struct snd_cs46xx *chip, u32 sample_buffer_addr,
  137. int dword_count)
  138. {
  139. void __iomem *dst = chip->region.idx[2].remap_addr + sample_buffer_addr;
  140. int i;
  141. for (i = 0; i < dword_count ; ++i ) {
  142. writel(0, dst);
  143. dst += 4;
  144. }
  145. }
  146. void cs46xx_dsp_remove_scb (struct snd_cs46xx *chip, struct dsp_scb_descriptor * scb)
  147. {
  148. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  149. unsigned long flags;
  150. /* check integrety */
  151. if (snd_BUG_ON(scb->index < 0 ||
  152. scb->index >= ins->nscb ||
  153. (ins->scbs + scb->index) != scb))
  154. return;
  155. #if 0
  156. /* can't remove a SCB with childs before
  157. removing childs first */
  158. if (snd_BUG_ON(scb->sub_list_ptr != ins->the_null_scb ||
  159. scb->next_scb_ptr != ins->the_null_scb))
  160. goto _end;
  161. #endif
  162. spin_lock_irqsave(&scb->lock, flags);
  163. _dsp_unlink_scb (chip,scb);
  164. spin_unlock_irqrestore(&scb->lock, flags);
  165. cs46xx_dsp_proc_free_scb_desc(scb);
  166. if (snd_BUG_ON(!scb->scb_symbol))
  167. return;
  168. remove_symbol (chip,scb->scb_symbol);
  169. ins->scbs[scb->index].deleted = 1;
  170. if (scb->index < ins->scb_highest_frag_index)
  171. ins->scb_highest_frag_index = scb->index;
  172. if (scb->index == ins->nscb - 1) {
  173. ins->nscb --;
  174. }
  175. if (ins->scb_highest_frag_index > ins->nscb) {
  176. ins->scb_highest_frag_index = ins->nscb;
  177. }
  178. #if 0
  179. /* !!!! THIS IS A PIECE OF SHIT MADE BY ME !!! */
  180. for(i = scb->index + 1;i < ins->nscb; ++i) {
  181. ins->scbs[i - 1].index = i - 1;
  182. }
  183. #endif
  184. }
  185. #ifdef CONFIG_PROC_FS
  186. void cs46xx_dsp_proc_free_scb_desc (struct dsp_scb_descriptor * scb)
  187. {
  188. if (scb->proc_info) {
  189. struct proc_scb_info * scb_info = scb->proc_info->private_data;
  190. snd_printdd("cs46xx_dsp_proc_free_scb_desc: freeing %s\n",scb->scb_name);
  191. snd_info_free_entry(scb->proc_info);
  192. scb->proc_info = NULL;
  193. kfree (scb_info);
  194. }
  195. }
  196. void cs46xx_dsp_proc_register_scb_desc (struct snd_cs46xx *chip,
  197. struct dsp_scb_descriptor * scb)
  198. {
  199. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  200. struct snd_info_entry * entry;
  201. struct proc_scb_info * scb_info;
  202. /* register to proc */
  203. if (ins->snd_card != NULL && ins->proc_dsp_dir != NULL &&
  204. scb->proc_info == NULL) {
  205. if ((entry = snd_info_create_card_entry(ins->snd_card, scb->scb_name,
  206. ins->proc_dsp_dir)) != NULL) {
  207. scb_info = kmalloc(sizeof(struct proc_scb_info), GFP_KERNEL);
  208. if (!scb_info) {
  209. snd_info_free_entry(entry);
  210. entry = NULL;
  211. goto out;
  212. }
  213. scb_info->chip = chip;
  214. scb_info->scb_desc = scb;
  215. entry->content = SNDRV_INFO_CONTENT_TEXT;
  216. entry->private_data = scb_info;
  217. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  218. entry->c.text.read = cs46xx_dsp_proc_scb_info_read;
  219. if (snd_info_register(entry) < 0) {
  220. snd_info_free_entry(entry);
  221. kfree (scb_info);
  222. entry = NULL;
  223. }
  224. }
  225. out:
  226. scb->proc_info = entry;
  227. }
  228. }
  229. #endif /* CONFIG_PROC_FS */
  230. static struct dsp_scb_descriptor *
  231. _dsp_create_generic_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data, u32 dest,
  232. struct dsp_symbol_entry * task_entry,
  233. struct dsp_scb_descriptor * parent_scb,
  234. int scb_child_type)
  235. {
  236. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  237. struct dsp_scb_descriptor * scb;
  238. unsigned long flags;
  239. if (snd_BUG_ON(!ins->the_null_scb))
  240. return NULL;
  241. /* fill the data that will be wroten to DSP */
  242. scb_data[SCBsubListPtr] =
  243. (ins->the_null_scb->address << 0x10) | ins->the_null_scb->address;
  244. scb_data[SCBfuncEntryPtr] &= 0xFFFF0000;
  245. scb_data[SCBfuncEntryPtr] |= task_entry->address;
  246. snd_printdd("dsp_spos: creating SCB <%s>\n",name);
  247. scb = cs46xx_dsp_create_scb(chip,name,scb_data,dest);
  248. scb->sub_list_ptr = ins->the_null_scb;
  249. scb->next_scb_ptr = ins->the_null_scb;
  250. scb->parent_scb_ptr = parent_scb;
  251. scb->task_entry = task_entry;
  252. /* update parent SCB */
  253. if (scb->parent_scb_ptr) {
  254. #if 0
  255. printk ("scb->parent_scb_ptr = %s\n",scb->parent_scb_ptr->scb_name);
  256. printk ("scb->parent_scb_ptr->next_scb_ptr = %s\n",scb->parent_scb_ptr->next_scb_ptr->scb_name);
  257. printk ("scb->parent_scb_ptr->sub_list_ptr = %s\n",scb->parent_scb_ptr->sub_list_ptr->scb_name);
  258. #endif
  259. /* link to parent SCB */
  260. if (scb_child_type == SCB_ON_PARENT_NEXT_SCB) {
  261. if (snd_BUG_ON(scb->parent_scb_ptr->next_scb_ptr !=
  262. ins->the_null_scb))
  263. return NULL;
  264. scb->parent_scb_ptr->next_scb_ptr = scb;
  265. } else if (scb_child_type == SCB_ON_PARENT_SUBLIST_SCB) {
  266. if (snd_BUG_ON(scb->parent_scb_ptr->sub_list_ptr !=
  267. ins->the_null_scb))
  268. return NULL;
  269. scb->parent_scb_ptr->sub_list_ptr = scb;
  270. } else {
  271. snd_BUG();
  272. }
  273. spin_lock_irqsave(&chip->reg_lock, flags);
  274. /* update entry in DSP RAM */
  275. cs46xx_dsp_spos_update_scb(chip,scb->parent_scb_ptr);
  276. spin_unlock_irqrestore(&chip->reg_lock, flags);
  277. }
  278. cs46xx_dsp_proc_register_scb_desc (chip,scb);
  279. return scb;
  280. }
  281. static struct dsp_scb_descriptor *
  282. cs46xx_dsp_create_generic_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data,
  283. u32 dest, char * task_entry_name,
  284. struct dsp_scb_descriptor * parent_scb,
  285. int scb_child_type)
  286. {
  287. struct dsp_symbol_entry * task_entry;
  288. task_entry = cs46xx_dsp_lookup_symbol (chip,task_entry_name,
  289. SYMBOL_CODE);
  290. if (task_entry == NULL) {
  291. snd_printk (KERN_ERR "dsp_spos: symbol %s not found\n",task_entry_name);
  292. return NULL;
  293. }
  294. return _dsp_create_generic_scb (chip,name,scb_data,dest,task_entry,
  295. parent_scb,scb_child_type);
  296. }
  297. struct dsp_scb_descriptor *
  298. cs46xx_dsp_create_timing_master_scb (struct snd_cs46xx *chip)
  299. {
  300. struct dsp_scb_descriptor * scb;
  301. struct dsp_timing_master_scb timing_master_scb = {
  302. { 0,
  303. 0,
  304. 0,
  305. 0
  306. },
  307. { 0,
  308. 0,
  309. 0,
  310. 0,
  311. 0
  312. },
  313. 0,0,
  314. 0,NULL_SCB_ADDR,
  315. 0,0, /* extraSampleAccum:TMreserved */
  316. 0,0, /* codecFIFOptr:codecFIFOsyncd */
  317. 0x0001,0x8000, /* fracSampAccumQm1:TMfrmsLeftInGroup */
  318. 0x0001,0x0000, /* fracSampCorrectionQm1:TMfrmGroupLength */
  319. 0x00060000 /* nSampPerFrmQ15 */
  320. };
  321. scb = cs46xx_dsp_create_generic_scb(chip,"TimingMasterSCBInst",(u32 *)&timing_master_scb,
  322. TIMINGMASTER_SCB_ADDR,
  323. "TIMINGMASTER",NULL,SCB_NO_PARENT);
  324. return scb;
  325. }
  326. struct dsp_scb_descriptor *
  327. cs46xx_dsp_create_codec_out_scb(struct snd_cs46xx * chip, char * codec_name,
  328. u16 channel_disp, u16 fifo_addr, u16 child_scb_addr,
  329. u32 dest, struct dsp_scb_descriptor * parent_scb,
  330. int scb_child_type)
  331. {
  332. struct dsp_scb_descriptor * scb;
  333. struct dsp_codec_output_scb codec_out_scb = {
  334. { 0,
  335. 0,
  336. 0,
  337. 0
  338. },
  339. {
  340. 0,
  341. 0,
  342. 0,
  343. 0,
  344. 0
  345. },
  346. 0,0,
  347. 0,NULL_SCB_ADDR,
  348. 0, /* COstrmRsConfig */
  349. 0, /* COstrmBufPtr */
  350. channel_disp,fifo_addr, /* leftChanBaseIOaddr:rightChanIOdisp */
  351. 0x0000,0x0080, /* (!AC97!) COexpVolChangeRate:COscaleShiftCount */
  352. 0,child_scb_addr /* COreserved - need child scb to work with rom code */
  353. };
  354. scb = cs46xx_dsp_create_generic_scb(chip,codec_name,(u32 *)&codec_out_scb,
  355. dest,"S16_CODECOUTPUTTASK",parent_scb,
  356. scb_child_type);
  357. return scb;
  358. }
  359. struct dsp_scb_descriptor *
  360. cs46xx_dsp_create_codec_in_scb(struct snd_cs46xx * chip, char * codec_name,
  361. u16 channel_disp, u16 fifo_addr, u16 sample_buffer_addr,
  362. u32 dest, struct dsp_scb_descriptor * parent_scb,
  363. int scb_child_type)
  364. {
  365. struct dsp_scb_descriptor * scb;
  366. struct dsp_codec_input_scb codec_input_scb = {
  367. { 0,
  368. 0,
  369. 0,
  370. 0
  371. },
  372. {
  373. 0,
  374. 0,
  375. 0,
  376. 0,
  377. 0
  378. },
  379. #if 0 /* cs4620 */
  380. SyncIOSCB,NULL_SCB_ADDR
  381. #else
  382. 0 , 0,
  383. #endif
  384. 0,0,
  385. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64, /* strmRsConfig */
  386. sample_buffer_addr << 0x10, /* strmBufPtr; defined as a dword ptr, used as a byte ptr */
  387. channel_disp,fifo_addr, /* (!AC97!) leftChanBaseINaddr=AC97primary
  388. link input slot 3 :rightChanINdisp=""slot 4 */
  389. 0x0000,0x0000, /* (!AC97!) ????:scaleShiftCount; no shift needed
  390. because AC97 is already 20 bits */
  391. 0x80008000 /* ??clw cwcgame.scb has 0 */
  392. };
  393. scb = cs46xx_dsp_create_generic_scb(chip,codec_name,(u32 *)&codec_input_scb,
  394. dest,"S16_CODECINPUTTASK",parent_scb,
  395. scb_child_type);
  396. return scb;
  397. }
  398. static struct dsp_scb_descriptor *
  399. cs46xx_dsp_create_pcm_reader_scb(struct snd_cs46xx * chip, char * scb_name,
  400. u16 sample_buffer_addr, u32 dest,
  401. int virtual_channel, u32 playback_hw_addr,
  402. struct dsp_scb_descriptor * parent_scb,
  403. int scb_child_type)
  404. {
  405. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  406. struct dsp_scb_descriptor * scb;
  407. struct dsp_generic_scb pcm_reader_scb = {
  408. /*
  409. Play DMA Task xfers data from host buffer to SP buffer
  410. init/runtime variables:
  411. PlayAC: Play Audio Data Conversion - SCB loc: 2nd dword, mask: 0x0000F000L
  412. DATA_FMT_16BIT_ST_LTLEND(0x00000000L) from 16-bit stereo, little-endian
  413. DATA_FMT_8_BIT_ST_SIGNED(0x00001000L) from 8-bit stereo, signed
  414. DATA_FMT_16BIT_MN_LTLEND(0x00002000L) from 16-bit mono, little-endian
  415. DATA_FMT_8_BIT_MN_SIGNED(0x00003000L) from 8-bit mono, signed
  416. DATA_FMT_16BIT_ST_BIGEND(0x00004000L) from 16-bit stereo, big-endian
  417. DATA_FMT_16BIT_MN_BIGEND(0x00006000L) from 16-bit mono, big-endian
  418. DATA_FMT_8_BIT_ST_UNSIGNED(0x00009000L) from 8-bit stereo, unsigned
  419. DATA_FMT_8_BIT_MN_UNSIGNED(0x0000b000L) from 8-bit mono, unsigned
  420. ? Other combinations possible from:
  421. DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000L
  422. DMA_RQ_C2_AC_NONE 0x00000000L
  423. DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000L
  424. DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000L
  425. DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000L
  426. DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000L
  427. HostBuffAddr: Host Buffer Physical Byte Address - SCB loc:3rd dword, Mask: 0xFFFFFFFFL
  428. aligned to dword boundary
  429. */
  430. /* Basic (non scatter/gather) DMA requestor (4 ints) */
  431. { DMA_RQ_C1_SOURCE_ON_HOST + /* source buffer is on the host */
  432. DMA_RQ_C1_SOURCE_MOD1024 + /* source buffer is 1024 dwords (4096 bytes) */
  433. DMA_RQ_C1_DEST_MOD32 + /* dest buffer(PCMreaderBuf) is 32 dwords*/
  434. DMA_RQ_C1_WRITEBACK_SRC_FLAG + /* ?? */
  435. DMA_RQ_C1_WRITEBACK_DEST_FLAG + /* ?? */
  436. 15, /* DwordCount-1: picked 16 for DwordCount because Jim */
  437. /* Barnette said that is what we should use since */
  438. /* we are not running in optimized mode? */
  439. DMA_RQ_C2_AC_NONE +
  440. DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG + /* set play interrupt (bit0) in HISR when source */
  441. /* buffer (on host) crosses half-way point */
  442. virtual_channel, /* Play DMA channel arbitrarily set to 0 */
  443. playback_hw_addr, /* HostBuffAddr (source) */
  444. DMA_RQ_SD_SP_SAMPLE_ADDR + /* destination buffer is in SP Sample Memory */
  445. sample_buffer_addr /* SP Buffer Address (destination) */
  446. },
  447. /* Scatter/gather DMA requestor extension (5 ints) */
  448. {
  449. 0,
  450. 0,
  451. 0,
  452. 0,
  453. 0
  454. },
  455. /* Sublist pointer & next stream control block (SCB) link. */
  456. NULL_SCB_ADDR,NULL_SCB_ADDR,
  457. /* Pointer to this tasks parameter block & stream function pointer */
  458. 0,NULL_SCB_ADDR,
  459. /* rsConfig register for stream buffer (rsDMA reg. is loaded from basicReq.daw */
  460. /* for incoming streams, or basicReq.saw, for outgoing streams) */
  461. RSCONFIG_DMA_ENABLE + /* enable DMA */
  462. (19 << RSCONFIG_MAX_DMA_SIZE_SHIFT) + /* MAX_DMA_SIZE picked to be 19 since SPUD */
  463. /* uses it for some reason */
  464. ((dest >> 4) << RSCONFIG_STREAM_NUM_SHIFT) + /* stream number = SCBaddr/16 */
  465. RSCONFIG_SAMPLE_16STEREO +
  466. RSCONFIG_MODULO_32, /* dest buffer(PCMreaderBuf) is 32 dwords (256 bytes) */
  467. /* Stream sample pointer & MAC-unit mode for this stream */
  468. (sample_buffer_addr << 0x10),
  469. /* Fractional increment per output sample in the input sample buffer */
  470. 0,
  471. {
  472. /* Standard stereo volume control
  473. default muted */
  474. 0xffff,0xffff,
  475. 0xffff,0xffff
  476. }
  477. };
  478. if (ins->null_algorithm == NULL) {
  479. ins->null_algorithm = cs46xx_dsp_lookup_symbol (chip,"NULLALGORITHM",
  480. SYMBOL_CODE);
  481. if (ins->null_algorithm == NULL) {
  482. snd_printk (KERN_ERR "dsp_spos: symbol NULLALGORITHM not found\n");
  483. return NULL;
  484. }
  485. }
  486. scb = _dsp_create_generic_scb(chip,scb_name,(u32 *)&pcm_reader_scb,
  487. dest,ins->null_algorithm,parent_scb,
  488. scb_child_type);
  489. return scb;
  490. }
  491. #define GOF_PER_SEC 200
  492. struct dsp_scb_descriptor *
  493. cs46xx_dsp_create_src_task_scb(struct snd_cs46xx * chip, char * scb_name,
  494. int rate,
  495. u16 src_buffer_addr,
  496. u16 src_delay_buffer_addr, u32 dest,
  497. struct dsp_scb_descriptor * parent_scb,
  498. int scb_child_type,
  499. int pass_through)
  500. {
  501. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  502. struct dsp_scb_descriptor * scb;
  503. unsigned int tmp1, tmp2;
  504. unsigned int phiIncr;
  505. unsigned int correctionPerGOF, correctionPerSec;
  506. snd_printdd( "dsp_spos: setting %s rate to %u\n",scb_name,rate);
  507. /*
  508. * Compute the values used to drive the actual sample rate conversion.
  509. * The following formulas are being computed, using inline assembly
  510. * since we need to use 64 bit arithmetic to compute the values:
  511. *
  512. * phiIncr = floor((Fs,in * 2^26) / Fs,out)
  513. * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
  514. * GOF_PER_SEC)
  515. * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
  516. * GOF_PER_SEC * correctionPerGOF
  517. *
  518. * i.e.
  519. *
  520. * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
  521. * correctionPerGOF:correctionPerSec =
  522. * dividend:remainder(ulOther / GOF_PER_SEC)
  523. */
  524. tmp1 = rate << 16;
  525. phiIncr = tmp1 / 48000;
  526. tmp1 -= phiIncr * 48000;
  527. tmp1 <<= 10;
  528. phiIncr <<= 10;
  529. tmp2 = tmp1 / 48000;
  530. phiIncr += tmp2;
  531. tmp1 -= tmp2 * 48000;
  532. correctionPerGOF = tmp1 / GOF_PER_SEC;
  533. tmp1 -= correctionPerGOF * GOF_PER_SEC;
  534. correctionPerSec = tmp1;
  535. {
  536. struct dsp_src_task_scb src_task_scb = {
  537. 0x0028,0x00c8,
  538. 0x5555,0x0000,
  539. 0x0000,0x0000,
  540. src_buffer_addr,1,
  541. correctionPerGOF,correctionPerSec,
  542. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_32,
  543. 0x0000,src_delay_buffer_addr,
  544. 0x0,
  545. 0x080,(src_delay_buffer_addr + (24 * 4)),
  546. 0,0, /* next_scb, sub_list_ptr */
  547. 0,0, /* entry, this_spb */
  548. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_8,
  549. src_buffer_addr << 0x10,
  550. phiIncr,
  551. {
  552. 0xffff - ins->dac_volume_right,0xffff - ins->dac_volume_left,
  553. 0xffff - ins->dac_volume_right,0xffff - ins->dac_volume_left
  554. }
  555. };
  556. if (ins->s16_up == NULL) {
  557. ins->s16_up = cs46xx_dsp_lookup_symbol (chip,"S16_UPSRC",
  558. SYMBOL_CODE);
  559. if (ins->s16_up == NULL) {
  560. snd_printk (KERN_ERR "dsp_spos: symbol S16_UPSRC not found\n");
  561. return NULL;
  562. }
  563. }
  564. /* clear buffers */
  565. _dsp_clear_sample_buffer (chip,src_buffer_addr,8);
  566. _dsp_clear_sample_buffer (chip,src_delay_buffer_addr,32);
  567. if (pass_through) {
  568. /* wont work with any other rate than
  569. the native DSP rate */
  570. snd_BUG_ON(rate != 48000);
  571. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&src_task_scb,
  572. dest,"DMAREADER",parent_scb,
  573. scb_child_type);
  574. } else {
  575. scb = _dsp_create_generic_scb(chip,scb_name,(u32 *)&src_task_scb,
  576. dest,ins->s16_up,parent_scb,
  577. scb_child_type);
  578. }
  579. }
  580. return scb;
  581. }
  582. #if 0 /* not used */
  583. struct dsp_scb_descriptor *
  584. cs46xx_dsp_create_filter_scb(struct snd_cs46xx * chip, char * scb_name,
  585. u16 buffer_addr, u32 dest,
  586. struct dsp_scb_descriptor * parent_scb,
  587. int scb_child_type) {
  588. struct dsp_scb_descriptor * scb;
  589. struct dsp_filter_scb filter_scb = {
  590. .a0_right = 0x41a9,
  591. .a0_left = 0x41a9,
  592. .a1_right = 0xb8e4,
  593. .a1_left = 0xb8e4,
  594. .a2_right = 0x3e55,
  595. .a2_left = 0x3e55,
  596. .filter_unused3 = 0x0000,
  597. .filter_unused2 = 0x0000,
  598. .output_buf_ptr = buffer_addr,
  599. .init = 0x000,
  600. .prev_sample_output1 = 0x00000000,
  601. .prev_sample_output2 = 0x00000000,
  602. .prev_sample_input1 = 0x00000000,
  603. .prev_sample_input2 = 0x00000000,
  604. .next_scb_ptr = 0x0000,
  605. .sub_list_ptr = 0x0000,
  606. .entry_point = 0x0000,
  607. .spb_ptr = 0x0000,
  608. .b0_right = 0x0e38,
  609. .b0_left = 0x0e38,
  610. .b1_right = 0x1c71,
  611. .b1_left = 0x1c71,
  612. .b2_right = 0x0e38,
  613. .b2_left = 0x0e38,
  614. };
  615. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&filter_scb,
  616. dest,"FILTERTASK",parent_scb,
  617. scb_child_type);
  618. return scb;
  619. }
  620. #endif /* not used */
  621. struct dsp_scb_descriptor *
  622. cs46xx_dsp_create_mix_only_scb(struct snd_cs46xx * chip, char * scb_name,
  623. u16 mix_buffer_addr, u32 dest,
  624. struct dsp_scb_descriptor * parent_scb,
  625. int scb_child_type)
  626. {
  627. struct dsp_scb_descriptor * scb;
  628. struct dsp_mix_only_scb master_mix_scb = {
  629. /* 0 */ { 0,
  630. /* 1 */ 0,
  631. /* 2 */ mix_buffer_addr,
  632. /* 3 */ 0
  633. /* */ },
  634. {
  635. /* 4 */ 0,
  636. /* 5 */ 0,
  637. /* 6 */ 0,
  638. /* 7 */ 0,
  639. /* 8 */ 0x00000080
  640. },
  641. /* 9 */ 0,0,
  642. /* A */ 0,0,
  643. /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_32,
  644. /* C */ (mix_buffer_addr + (16 * 4)) << 0x10,
  645. /* D */ 0,
  646. {
  647. /* E */ 0x8000,0x8000,
  648. /* F */ 0x8000,0x8000
  649. }
  650. };
  651. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&master_mix_scb,
  652. dest,"S16_MIX",parent_scb,
  653. scb_child_type);
  654. return scb;
  655. }
  656. struct dsp_scb_descriptor *
  657. cs46xx_dsp_create_mix_to_ostream_scb(struct snd_cs46xx * chip, char * scb_name,
  658. u16 mix_buffer_addr, u16 writeback_spb, u32 dest,
  659. struct dsp_scb_descriptor * parent_scb,
  660. int scb_child_type)
  661. {
  662. struct dsp_scb_descriptor * scb;
  663. struct dsp_mix2_ostream_scb mix2_ostream_scb = {
  664. /* Basic (non scatter/gather) DMA requestor (4 ints) */
  665. {
  666. DMA_RQ_C1_SOURCE_MOD64 +
  667. DMA_RQ_C1_DEST_ON_HOST +
  668. DMA_RQ_C1_DEST_MOD1024 +
  669. DMA_RQ_C1_WRITEBACK_SRC_FLAG +
  670. DMA_RQ_C1_WRITEBACK_DEST_FLAG +
  671. 15,
  672. DMA_RQ_C2_AC_NONE +
  673. DMA_RQ_C2_SIGNAL_DEST_PINGPONG +
  674. CS46XX_DSP_CAPTURE_CHANNEL,
  675. DMA_RQ_SD_SP_SAMPLE_ADDR +
  676. mix_buffer_addr,
  677. 0x0
  678. },
  679. { 0, 0, 0, 0, 0, },
  680. 0,0,
  681. 0,writeback_spb,
  682. RSCONFIG_DMA_ENABLE +
  683. (19 << RSCONFIG_MAX_DMA_SIZE_SHIFT) +
  684. ((dest >> 4) << RSCONFIG_STREAM_NUM_SHIFT) +
  685. RSCONFIG_DMA_TO_HOST +
  686. RSCONFIG_SAMPLE_16STEREO +
  687. RSCONFIG_MODULO_64,
  688. (mix_buffer_addr + (32 * 4)) << 0x10,
  689. 1,0,
  690. 0x0001,0x0080,
  691. 0xFFFF,0
  692. };
  693. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&mix2_ostream_scb,
  694. dest,"S16_MIX_TO_OSTREAM",parent_scb,
  695. scb_child_type);
  696. return scb;
  697. }
  698. struct dsp_scb_descriptor *
  699. cs46xx_dsp_create_vari_decimate_scb(struct snd_cs46xx * chip,char * scb_name,
  700. u16 vari_buffer_addr0,
  701. u16 vari_buffer_addr1,
  702. u32 dest,
  703. struct dsp_scb_descriptor * parent_scb,
  704. int scb_child_type)
  705. {
  706. struct dsp_scb_descriptor * scb;
  707. struct dsp_vari_decimate_scb vari_decimate_scb = {
  708. 0x0028,0x00c8,
  709. 0x5555,0x0000,
  710. 0x0000,0x0000,
  711. vari_buffer_addr0,vari_buffer_addr1,
  712. 0x0028,0x00c8,
  713. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_256,
  714. 0xFF800000,
  715. 0,
  716. 0x0080,vari_buffer_addr1 + (25 * 4),
  717. 0,0,
  718. 0,0,
  719. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_8,
  720. vari_buffer_addr0 << 0x10,
  721. 0x04000000,
  722. {
  723. 0x8000,0x8000,
  724. 0xFFFF,0xFFFF
  725. }
  726. };
  727. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&vari_decimate_scb,
  728. dest,"VARIDECIMATE",parent_scb,
  729. scb_child_type);
  730. return scb;
  731. }
  732. static struct dsp_scb_descriptor *
  733. cs46xx_dsp_create_pcm_serial_input_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  734. struct dsp_scb_descriptor * input_scb,
  735. struct dsp_scb_descriptor * parent_scb,
  736. int scb_child_type)
  737. {
  738. struct dsp_scb_descriptor * scb;
  739. struct dsp_pcm_serial_input_scb pcm_serial_input_scb = {
  740. { 0,
  741. 0,
  742. 0,
  743. 0
  744. },
  745. {
  746. 0,
  747. 0,
  748. 0,
  749. 0,
  750. 0
  751. },
  752. 0,0,
  753. 0,0,
  754. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_16,
  755. 0,
  756. /* 0xD */ 0,input_scb->address,
  757. {
  758. /* 0xE */ 0x8000,0x8000,
  759. /* 0xF */ 0x8000,0x8000
  760. }
  761. };
  762. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&pcm_serial_input_scb,
  763. dest,"PCMSERIALINPUTTASK",parent_scb,
  764. scb_child_type);
  765. return scb;
  766. }
  767. static struct dsp_scb_descriptor *
  768. cs46xx_dsp_create_asynch_fg_tx_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  769. u16 hfg_scb_address,
  770. u16 asynch_buffer_address,
  771. struct dsp_scb_descriptor * parent_scb,
  772. int scb_child_type)
  773. {
  774. struct dsp_scb_descriptor * scb;
  775. struct dsp_asynch_fg_tx_scb asynch_fg_tx_scb = {
  776. 0xfc00,0x03ff, /* Prototype sample buffer size of 256 dwords */
  777. 0x0058,0x0028, /* Min Delta 7 dwords == 28 bytes */
  778. /* : Max delta 25 dwords == 100 bytes */
  779. 0,hfg_scb_address, /* Point to HFG task SCB */
  780. 0,0, /* Initialize current Delta and Consumer ptr adjustment count */
  781. 0, /* Initialize accumulated Phi to 0 */
  782. 0,0x2aab, /* Const 1/3 */
  783. {
  784. 0, /* Define the unused elements */
  785. 0,
  786. 0
  787. },
  788. 0,0,
  789. 0,dest + AFGTxAccumPhi,
  790. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_256, /* Stereo, 256 dword */
  791. (asynch_buffer_address) << 0x10, /* This should be automagically synchronized
  792. to the producer pointer */
  793. /* There is no correct initial value, it will depend upon the detected
  794. rate etc */
  795. 0x18000000, /* Phi increment for approx 32k operation */
  796. 0x8000,0x8000, /* Volume controls are unused at this time */
  797. 0x8000,0x8000
  798. };
  799. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&asynch_fg_tx_scb,
  800. dest,"ASYNCHFGTXCODE",parent_scb,
  801. scb_child_type);
  802. return scb;
  803. }
  804. struct dsp_scb_descriptor *
  805. cs46xx_dsp_create_asynch_fg_rx_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  806. u16 hfg_scb_address,
  807. u16 asynch_buffer_address,
  808. struct dsp_scb_descriptor * parent_scb,
  809. int scb_child_type)
  810. {
  811. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  812. struct dsp_scb_descriptor * scb;
  813. struct dsp_asynch_fg_rx_scb asynch_fg_rx_scb = {
  814. 0xfe00,0x01ff, /* Prototype sample buffer size of 128 dwords */
  815. 0x0064,0x001c, /* Min Delta 7 dwords == 28 bytes */
  816. /* : Max delta 25 dwords == 100 bytes */
  817. 0,hfg_scb_address, /* Point to HFG task SCB */
  818. 0,0, /* Initialize current Delta and Consumer ptr adjustment count */
  819. {
  820. 0, /* Define the unused elements */
  821. 0,
  822. 0,
  823. 0,
  824. 0
  825. },
  826. 0,0,
  827. 0,dest,
  828. RSCONFIG_MODULO_128 |
  829. RSCONFIG_SAMPLE_16STEREO, /* Stereo, 128 dword */
  830. ( (asynch_buffer_address + (16 * 4)) << 0x10), /* This should be automagically
  831. synchrinized to the producer pointer */
  832. /* There is no correct initial value, it will depend upon the detected
  833. rate etc */
  834. 0x18000000,
  835. /* Set IEC958 input volume */
  836. 0xffff - ins->spdif_input_volume_right,0xffff - ins->spdif_input_volume_left,
  837. 0xffff - ins->spdif_input_volume_right,0xffff - ins->spdif_input_volume_left,
  838. };
  839. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&asynch_fg_rx_scb,
  840. dest,"ASYNCHFGRXCODE",parent_scb,
  841. scb_child_type);
  842. return scb;
  843. }
  844. #if 0 /* not used */
  845. struct dsp_scb_descriptor *
  846. cs46xx_dsp_create_output_snoop_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  847. u16 snoop_buffer_address,
  848. struct dsp_scb_descriptor * snoop_scb,
  849. struct dsp_scb_descriptor * parent_scb,
  850. int scb_child_type)
  851. {
  852. struct dsp_scb_descriptor * scb;
  853. struct dsp_output_snoop_scb output_snoop_scb = {
  854. { 0, /* not used. Zero */
  855. 0,
  856. 0,
  857. 0,
  858. },
  859. {
  860. 0, /* not used. Zero */
  861. 0,
  862. 0,
  863. 0,
  864. 0
  865. },
  866. 0,0,
  867. 0,0,
  868. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
  869. snoop_buffer_address << 0x10,
  870. 0,0,
  871. 0,
  872. 0,snoop_scb->address
  873. };
  874. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&output_snoop_scb,
  875. dest,"OUTPUTSNOOP",parent_scb,
  876. scb_child_type);
  877. return scb;
  878. }
  879. #endif /* not used */
  880. struct dsp_scb_descriptor *
  881. cs46xx_dsp_create_spio_write_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  882. struct dsp_scb_descriptor * parent_scb,
  883. int scb_child_type)
  884. {
  885. struct dsp_scb_descriptor * scb;
  886. struct dsp_spio_write_scb spio_write_scb = {
  887. 0,0, /* SPIOWAddress2:SPIOWAddress1; */
  888. 0, /* SPIOWData1; */
  889. 0, /* SPIOWData2; */
  890. 0,0, /* SPIOWAddress4:SPIOWAddress3; */
  891. 0, /* SPIOWData3; */
  892. 0, /* SPIOWData4; */
  893. 0,0, /* SPIOWDataPtr:Unused1; */
  894. { 0,0 }, /* Unused2[2]; */
  895. 0,0, /* SPIOWChildPtr:SPIOWSiblingPtr; */
  896. 0,0, /* SPIOWThisPtr:SPIOWEntryPoint; */
  897. {
  898. 0,
  899. 0,
  900. 0,
  901. 0,
  902. 0 /* Unused3[5]; */
  903. }
  904. };
  905. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&spio_write_scb,
  906. dest,"SPIOWRITE",parent_scb,
  907. scb_child_type);
  908. return scb;
  909. }
  910. struct dsp_scb_descriptor *
  911. cs46xx_dsp_create_magic_snoop_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  912. u16 snoop_buffer_address,
  913. struct dsp_scb_descriptor * snoop_scb,
  914. struct dsp_scb_descriptor * parent_scb,
  915. int scb_child_type)
  916. {
  917. struct dsp_scb_descriptor * scb;
  918. struct dsp_magic_snoop_task magic_snoop_scb = {
  919. /* 0 */ 0, /* i0 */
  920. /* 1 */ 0, /* i1 */
  921. /* 2 */ snoop_buffer_address << 0x10,
  922. /* 3 */ 0,snoop_scb->address,
  923. /* 4 */ 0, /* i3 */
  924. /* 5 */ 0, /* i4 */
  925. /* 6 */ 0, /* i5 */
  926. /* 7 */ 0, /* i6 */
  927. /* 8 */ 0, /* i7 */
  928. /* 9 */ 0,0, /* next_scb, sub_list_ptr */
  929. /* A */ 0,0, /* entry_point, this_ptr */
  930. /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
  931. /* C */ snoop_buffer_address << 0x10,
  932. /* D */ 0,
  933. /* E */ { 0x8000,0x8000,
  934. /* F */ 0xffff,0xffff
  935. }
  936. };
  937. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&magic_snoop_scb,
  938. dest,"MAGICSNOOPTASK",parent_scb,
  939. scb_child_type);
  940. return scb;
  941. }
  942. static struct dsp_scb_descriptor *
  943. find_next_free_scb (struct snd_cs46xx * chip, struct dsp_scb_descriptor * from)
  944. {
  945. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  946. struct dsp_scb_descriptor * scb = from;
  947. while (scb->next_scb_ptr != ins->the_null_scb) {
  948. if (snd_BUG_ON(!scb->next_scb_ptr))
  949. return NULL;
  950. scb = scb->next_scb_ptr;
  951. }
  952. return scb;
  953. }
  954. static u32 pcm_reader_buffer_addr[DSP_MAX_PCM_CHANNELS] = {
  955. 0x0600, /* 1 */
  956. 0x1500, /* 2 */
  957. 0x1580, /* 3 */
  958. 0x1600, /* 4 */
  959. 0x1680, /* 5 */
  960. 0x1700, /* 6 */
  961. 0x1780, /* 7 */
  962. 0x1800, /* 8 */
  963. 0x1880, /* 9 */
  964. 0x1900, /* 10 */
  965. 0x1980, /* 11 */
  966. 0x1A00, /* 12 */
  967. 0x1A80, /* 13 */
  968. 0x1B00, /* 14 */
  969. 0x1B80, /* 15 */
  970. 0x1C00, /* 16 */
  971. 0x1C80, /* 17 */
  972. 0x1D00, /* 18 */
  973. 0x1D80, /* 19 */
  974. 0x1E00, /* 20 */
  975. 0x1E80, /* 21 */
  976. 0x1F00, /* 22 */
  977. 0x1F80, /* 23 */
  978. 0x2000, /* 24 */
  979. 0x2080, /* 25 */
  980. 0x2100, /* 26 */
  981. 0x2180, /* 27 */
  982. 0x2200, /* 28 */
  983. 0x2280, /* 29 */
  984. 0x2300, /* 30 */
  985. 0x2380, /* 31 */
  986. 0x2400, /* 32 */
  987. };
  988. static u32 src_output_buffer_addr[DSP_MAX_SRC_NR] = {
  989. 0x2B80,
  990. 0x2BA0,
  991. 0x2BC0,
  992. 0x2BE0,
  993. 0x2D00,
  994. 0x2D20,
  995. 0x2D40,
  996. 0x2D60,
  997. 0x2D80,
  998. 0x2DA0,
  999. 0x2DC0,
  1000. 0x2DE0,
  1001. 0x2E00,
  1002. 0x2E20
  1003. };
  1004. static u32 src_delay_buffer_addr[DSP_MAX_SRC_NR] = {
  1005. 0x2480,
  1006. 0x2500,
  1007. 0x2580,
  1008. 0x2600,
  1009. 0x2680,
  1010. 0x2700,
  1011. 0x2780,
  1012. 0x2800,
  1013. 0x2880,
  1014. 0x2900,
  1015. 0x2980,
  1016. 0x2A00,
  1017. 0x2A80,
  1018. 0x2B00
  1019. };
  1020. struct dsp_pcm_channel_descriptor *
  1021. cs46xx_dsp_create_pcm_channel (struct snd_cs46xx * chip,
  1022. u32 sample_rate, void * private_data,
  1023. u32 hw_dma_addr,
  1024. int pcm_channel_id)
  1025. {
  1026. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1027. struct dsp_scb_descriptor * src_scb = NULL, * pcm_scb, * mixer_scb = NULL;
  1028. struct dsp_scb_descriptor * src_parent_scb = NULL;
  1029. /* struct dsp_scb_descriptor * pcm_parent_scb; */
  1030. char scb_name[DSP_MAX_SCB_NAME];
  1031. int i, pcm_index = -1, insert_point, src_index = -1, pass_through = 0;
  1032. unsigned long flags;
  1033. switch (pcm_channel_id) {
  1034. case DSP_PCM_MAIN_CHANNEL:
  1035. mixer_scb = ins->master_mix_scb;
  1036. break;
  1037. case DSP_PCM_REAR_CHANNEL:
  1038. mixer_scb = ins->rear_mix_scb;
  1039. break;
  1040. case DSP_PCM_CENTER_LFE_CHANNEL:
  1041. mixer_scb = ins->center_lfe_mix_scb;
  1042. break;
  1043. case DSP_PCM_S71_CHANNEL:
  1044. /* TODO */
  1045. snd_BUG();
  1046. break;
  1047. case DSP_IEC958_CHANNEL:
  1048. if (snd_BUG_ON(!ins->asynch_tx_scb))
  1049. return NULL;
  1050. mixer_scb = ins->asynch_tx_scb;
  1051. /* if sample rate is set to 48khz we pass
  1052. the Sample Rate Converted (which could
  1053. alter the raw data stream ...) */
  1054. if (sample_rate == 48000) {
  1055. snd_printdd ("IEC958 pass through\n");
  1056. /* Hack to bypass creating a new SRC */
  1057. pass_through = 1;
  1058. }
  1059. break;
  1060. default:
  1061. snd_BUG();
  1062. return NULL;
  1063. }
  1064. /* default sample rate is 44100 */
  1065. if (!sample_rate) sample_rate = 44100;
  1066. /* search for a already created SRC SCB with the same sample rate */
  1067. for (i = 0; i < DSP_MAX_PCM_CHANNELS &&
  1068. (pcm_index == -1 || src_scb == NULL); ++i) {
  1069. /* virtual channel reserved
  1070. for capture */
  1071. if (i == CS46XX_DSP_CAPTURE_CHANNEL) continue;
  1072. if (ins->pcm_channels[i].active) {
  1073. if (!src_scb &&
  1074. ins->pcm_channels[i].sample_rate == sample_rate &&
  1075. ins->pcm_channels[i].mixer_scb == mixer_scb) {
  1076. src_scb = ins->pcm_channels[i].src_scb;
  1077. ins->pcm_channels[i].src_scb->ref_count ++;
  1078. src_index = ins->pcm_channels[i].src_slot;
  1079. }
  1080. } else if (pcm_index == -1) {
  1081. pcm_index = i;
  1082. }
  1083. }
  1084. if (pcm_index == -1) {
  1085. snd_printk (KERN_ERR "dsp_spos: no free PCM channel\n");
  1086. return NULL;
  1087. }
  1088. if (src_scb == NULL) {
  1089. if (ins->nsrc_scb >= DSP_MAX_SRC_NR) {
  1090. snd_printk(KERN_ERR "dsp_spos: to many SRC instances\n!");
  1091. return NULL;
  1092. }
  1093. /* find a free slot */
  1094. for (i = 0; i < DSP_MAX_SRC_NR; ++i) {
  1095. if (ins->src_scb_slots[i] == 0) {
  1096. src_index = i;
  1097. ins->src_scb_slots[i] = 1;
  1098. break;
  1099. }
  1100. }
  1101. if (snd_BUG_ON(src_index == -1))
  1102. return NULL;
  1103. /* we need to create a new SRC SCB */
  1104. if (mixer_scb->sub_list_ptr == ins->the_null_scb) {
  1105. src_parent_scb = mixer_scb;
  1106. insert_point = SCB_ON_PARENT_SUBLIST_SCB;
  1107. } else {
  1108. src_parent_scb = find_next_free_scb(chip,mixer_scb->sub_list_ptr);
  1109. insert_point = SCB_ON_PARENT_NEXT_SCB;
  1110. }
  1111. snprintf (scb_name,DSP_MAX_SCB_NAME,"SrcTask_SCB%d",src_index);
  1112. snd_printdd( "dsp_spos: creating SRC \"%s\"\n",scb_name);
  1113. src_scb = cs46xx_dsp_create_src_task_scb(chip,scb_name,
  1114. sample_rate,
  1115. src_output_buffer_addr[src_index],
  1116. src_delay_buffer_addr[src_index],
  1117. /* 0x400 - 0x600 source SCBs */
  1118. 0x400 + (src_index * 0x10) ,
  1119. src_parent_scb,
  1120. insert_point,
  1121. pass_through);
  1122. if (!src_scb) {
  1123. snd_printk (KERN_ERR "dsp_spos: failed to create SRCtaskSCB\n");
  1124. return NULL;
  1125. }
  1126. /* cs46xx_dsp_set_src_sample_rate(chip,src_scb,sample_rate); */
  1127. ins->nsrc_scb ++;
  1128. }
  1129. snprintf (scb_name,DSP_MAX_SCB_NAME,"PCMReader_SCB%d",pcm_index);
  1130. snd_printdd( "dsp_spos: creating PCM \"%s\" (%d)\n",scb_name,
  1131. pcm_channel_id);
  1132. pcm_scb = cs46xx_dsp_create_pcm_reader_scb(chip,scb_name,
  1133. pcm_reader_buffer_addr[pcm_index],
  1134. /* 0x200 - 400 PCMreader SCBs */
  1135. (pcm_index * 0x10) + 0x200,
  1136. pcm_index, /* virtual channel 0-31 */
  1137. hw_dma_addr, /* pcm hw addr */
  1138. NULL, /* parent SCB ptr */
  1139. 0 /* insert point */
  1140. );
  1141. if (!pcm_scb) {
  1142. snd_printk (KERN_ERR "dsp_spos: failed to create PCMreaderSCB\n");
  1143. return NULL;
  1144. }
  1145. spin_lock_irqsave(&chip->reg_lock, flags);
  1146. ins->pcm_channels[pcm_index].sample_rate = sample_rate;
  1147. ins->pcm_channels[pcm_index].pcm_reader_scb = pcm_scb;
  1148. ins->pcm_channels[pcm_index].src_scb = src_scb;
  1149. ins->pcm_channels[pcm_index].unlinked = 1;
  1150. ins->pcm_channels[pcm_index].private_data = private_data;
  1151. ins->pcm_channels[pcm_index].src_slot = src_index;
  1152. ins->pcm_channels[pcm_index].active = 1;
  1153. ins->pcm_channels[pcm_index].pcm_slot = pcm_index;
  1154. ins->pcm_channels[pcm_index].mixer_scb = mixer_scb;
  1155. ins->npcm_channels ++;
  1156. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1157. return (ins->pcm_channels + pcm_index);
  1158. }
  1159. int cs46xx_dsp_pcm_channel_set_period (struct snd_cs46xx * chip,
  1160. struct dsp_pcm_channel_descriptor * pcm_channel,
  1161. int period_size)
  1162. {
  1163. u32 temp = snd_cs46xx_peek (chip,pcm_channel->pcm_reader_scb->address << 2);
  1164. temp &= ~DMA_RQ_C1_SOURCE_SIZE_MASK;
  1165. switch (period_size) {
  1166. case 2048:
  1167. temp |= DMA_RQ_C1_SOURCE_MOD1024;
  1168. break;
  1169. case 1024:
  1170. temp |= DMA_RQ_C1_SOURCE_MOD512;
  1171. break;
  1172. case 512:
  1173. temp |= DMA_RQ_C1_SOURCE_MOD256;
  1174. break;
  1175. case 256:
  1176. temp |= DMA_RQ_C1_SOURCE_MOD128;
  1177. break;
  1178. case 128:
  1179. temp |= DMA_RQ_C1_SOURCE_MOD64;
  1180. break;
  1181. case 64:
  1182. temp |= DMA_RQ_C1_SOURCE_MOD32;
  1183. break;
  1184. case 32:
  1185. temp |= DMA_RQ_C1_SOURCE_MOD16;
  1186. break;
  1187. default:
  1188. snd_printdd ("period size (%d) not supported by HW\n", period_size);
  1189. return -EINVAL;
  1190. }
  1191. snd_cs46xx_poke (chip,pcm_channel->pcm_reader_scb->address << 2,temp);
  1192. return 0;
  1193. }
  1194. int cs46xx_dsp_pcm_ostream_set_period (struct snd_cs46xx * chip,
  1195. int period_size)
  1196. {
  1197. u32 temp = snd_cs46xx_peek (chip,WRITEBACK_SCB_ADDR << 2);
  1198. temp &= ~DMA_RQ_C1_DEST_SIZE_MASK;
  1199. switch (period_size) {
  1200. case 2048:
  1201. temp |= DMA_RQ_C1_DEST_MOD1024;
  1202. break;
  1203. case 1024:
  1204. temp |= DMA_RQ_C1_DEST_MOD512;
  1205. break;
  1206. case 512:
  1207. temp |= DMA_RQ_C1_DEST_MOD256;
  1208. break;
  1209. case 256:
  1210. temp |= DMA_RQ_C1_DEST_MOD128;
  1211. break;
  1212. case 128:
  1213. temp |= DMA_RQ_C1_DEST_MOD64;
  1214. break;
  1215. case 64:
  1216. temp |= DMA_RQ_C1_DEST_MOD32;
  1217. break;
  1218. case 32:
  1219. temp |= DMA_RQ_C1_DEST_MOD16;
  1220. break;
  1221. default:
  1222. snd_printdd ("period size (%d) not supported by HW\n", period_size);
  1223. return -EINVAL;
  1224. }
  1225. snd_cs46xx_poke (chip,WRITEBACK_SCB_ADDR << 2,temp);
  1226. return 0;
  1227. }
  1228. void cs46xx_dsp_destroy_pcm_channel (struct snd_cs46xx * chip,
  1229. struct dsp_pcm_channel_descriptor * pcm_channel)
  1230. {
  1231. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1232. unsigned long flags;
  1233. if (snd_BUG_ON(!pcm_channel->active ||
  1234. ins->npcm_channels <= 0 ||
  1235. pcm_channel->src_scb->ref_count <= 0))
  1236. return;
  1237. spin_lock_irqsave(&chip->reg_lock, flags);
  1238. pcm_channel->unlinked = 1;
  1239. pcm_channel->active = 0;
  1240. pcm_channel->private_data = NULL;
  1241. pcm_channel->src_scb->ref_count --;
  1242. ins->npcm_channels --;
  1243. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1244. cs46xx_dsp_remove_scb(chip,pcm_channel->pcm_reader_scb);
  1245. if (!pcm_channel->src_scb->ref_count) {
  1246. cs46xx_dsp_remove_scb(chip,pcm_channel->src_scb);
  1247. if (snd_BUG_ON(pcm_channel->src_slot < 0 ||
  1248. pcm_channel->src_slot >= DSP_MAX_SRC_NR))
  1249. return;
  1250. ins->src_scb_slots[pcm_channel->src_slot] = 0;
  1251. ins->nsrc_scb --;
  1252. }
  1253. }
  1254. int cs46xx_dsp_pcm_unlink (struct snd_cs46xx * chip,
  1255. struct dsp_pcm_channel_descriptor * pcm_channel)
  1256. {
  1257. unsigned long flags;
  1258. if (snd_BUG_ON(!pcm_channel->active ||
  1259. chip->dsp_spos_instance->npcm_channels <= 0))
  1260. return -EIO;
  1261. spin_lock(&pcm_channel->src_scb->lock);
  1262. if (pcm_channel->unlinked) {
  1263. spin_unlock(&pcm_channel->src_scb->lock);
  1264. return -EIO;
  1265. }
  1266. spin_lock_irqsave(&chip->reg_lock, flags);
  1267. pcm_channel->unlinked = 1;
  1268. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1269. _dsp_unlink_scb (chip,pcm_channel->pcm_reader_scb);
  1270. spin_unlock(&pcm_channel->src_scb->lock);
  1271. return 0;
  1272. }
  1273. int cs46xx_dsp_pcm_link (struct snd_cs46xx * chip,
  1274. struct dsp_pcm_channel_descriptor * pcm_channel)
  1275. {
  1276. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1277. struct dsp_scb_descriptor * parent_scb;
  1278. struct dsp_scb_descriptor * src_scb = pcm_channel->src_scb;
  1279. unsigned long flags;
  1280. spin_lock(&pcm_channel->src_scb->lock);
  1281. if (pcm_channel->unlinked == 0) {
  1282. spin_unlock(&pcm_channel->src_scb->lock);
  1283. return -EIO;
  1284. }
  1285. parent_scb = src_scb;
  1286. if (src_scb->sub_list_ptr != ins->the_null_scb) {
  1287. src_scb->sub_list_ptr->parent_scb_ptr = pcm_channel->pcm_reader_scb;
  1288. pcm_channel->pcm_reader_scb->next_scb_ptr = src_scb->sub_list_ptr;
  1289. }
  1290. src_scb->sub_list_ptr = pcm_channel->pcm_reader_scb;
  1291. snd_BUG_ON(pcm_channel->pcm_reader_scb->parent_scb_ptr);
  1292. pcm_channel->pcm_reader_scb->parent_scb_ptr = parent_scb;
  1293. spin_lock_irqsave(&chip->reg_lock, flags);
  1294. /* update SCB entry in DSP RAM */
  1295. cs46xx_dsp_spos_update_scb(chip,pcm_channel->pcm_reader_scb);
  1296. /* update parent SCB entry */
  1297. cs46xx_dsp_spos_update_scb(chip,parent_scb);
  1298. pcm_channel->unlinked = 0;
  1299. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1300. spin_unlock(&pcm_channel->src_scb->lock);
  1301. return 0;
  1302. }
  1303. struct dsp_scb_descriptor *
  1304. cs46xx_add_record_source (struct snd_cs46xx *chip, struct dsp_scb_descriptor * source,
  1305. u16 addr, char * scb_name)
  1306. {
  1307. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1308. struct dsp_scb_descriptor * parent;
  1309. struct dsp_scb_descriptor * pcm_input;
  1310. int insert_point;
  1311. if (snd_BUG_ON(!ins->record_mixer_scb))
  1312. return NULL;
  1313. if (ins->record_mixer_scb->sub_list_ptr != ins->the_null_scb) {
  1314. parent = find_next_free_scb (chip,ins->record_mixer_scb->sub_list_ptr);
  1315. insert_point = SCB_ON_PARENT_NEXT_SCB;
  1316. } else {
  1317. parent = ins->record_mixer_scb;
  1318. insert_point = SCB_ON_PARENT_SUBLIST_SCB;
  1319. }
  1320. pcm_input = cs46xx_dsp_create_pcm_serial_input_scb(chip,scb_name,addr,
  1321. source, parent,
  1322. insert_point);
  1323. return pcm_input;
  1324. }
  1325. int cs46xx_src_unlink(struct snd_cs46xx *chip, struct dsp_scb_descriptor * src)
  1326. {
  1327. if (snd_BUG_ON(!src->parent_scb_ptr))
  1328. return -EINVAL;
  1329. /* mute SCB */
  1330. cs46xx_dsp_scb_set_volume (chip,src,0,0);
  1331. _dsp_unlink_scb (chip,src);
  1332. return 0;
  1333. }
  1334. int cs46xx_src_link(struct snd_cs46xx *chip, struct dsp_scb_descriptor * src)
  1335. {
  1336. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1337. struct dsp_scb_descriptor * parent_scb;
  1338. if (snd_BUG_ON(src->parent_scb_ptr))
  1339. return -EINVAL;
  1340. if (snd_BUG_ON(!ins->master_mix_scb))
  1341. return -EINVAL;
  1342. if (ins->master_mix_scb->sub_list_ptr != ins->the_null_scb) {
  1343. parent_scb = find_next_free_scb (chip,ins->master_mix_scb->sub_list_ptr);
  1344. parent_scb->next_scb_ptr = src;
  1345. } else {
  1346. parent_scb = ins->master_mix_scb;
  1347. parent_scb->sub_list_ptr = src;
  1348. }
  1349. src->parent_scb_ptr = parent_scb;
  1350. /* update entry in DSP RAM */
  1351. cs46xx_dsp_spos_update_scb(chip,parent_scb);
  1352. return 0;
  1353. }
  1354. int cs46xx_dsp_enable_spdif_out (struct snd_cs46xx *chip)
  1355. {
  1356. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1357. if ( ! (ins->spdif_status_out & DSP_SPDIF_STATUS_HW_ENABLED) ) {
  1358. cs46xx_dsp_enable_spdif_hw (chip);
  1359. }
  1360. /* dont touch anything if SPDIF is open */
  1361. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) {
  1362. /* when cs46xx_iec958_post_close(...) is called it
  1363. will call this function if necessary depending on
  1364. this bit */
  1365. ins->spdif_status_out |= DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1366. return -EBUSY;
  1367. }
  1368. if (snd_BUG_ON(ins->asynch_tx_scb))
  1369. return -EINVAL;
  1370. if (snd_BUG_ON(ins->master_mix_scb->next_scb_ptr !=
  1371. ins->the_null_scb))
  1372. return -EINVAL;
  1373. /* reset output snooper sample buffer pointer */
  1374. snd_cs46xx_poke (chip, (ins->ref_snoop_scb->address + 2) << 2,
  1375. (OUTPUT_SNOOP_BUFFER + 0x10) << 0x10 );
  1376. /* The asynch. transfer task */
  1377. ins->asynch_tx_scb = cs46xx_dsp_create_asynch_fg_tx_scb(chip,"AsynchFGTxSCB",ASYNCTX_SCB_ADDR,
  1378. SPDIFO_SCB_INST,
  1379. SPDIFO_IP_OUTPUT_BUFFER1,
  1380. ins->master_mix_scb,
  1381. SCB_ON_PARENT_NEXT_SCB);
  1382. if (!ins->asynch_tx_scb) return -ENOMEM;
  1383. ins->spdif_pcm_input_scb = cs46xx_dsp_create_pcm_serial_input_scb(chip,"PCMSerialInput_II",
  1384. PCMSERIALINII_SCB_ADDR,
  1385. ins->ref_snoop_scb,
  1386. ins->asynch_tx_scb,
  1387. SCB_ON_PARENT_SUBLIST_SCB);
  1388. if (!ins->spdif_pcm_input_scb) return -ENOMEM;
  1389. /* monitor state */
  1390. ins->spdif_status_out |= DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1391. return 0;
  1392. }
  1393. int cs46xx_dsp_disable_spdif_out (struct snd_cs46xx *chip)
  1394. {
  1395. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1396. /* dont touch anything if SPDIF is open */
  1397. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) {
  1398. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1399. return -EBUSY;
  1400. }
  1401. /* check integrety */
  1402. if (snd_BUG_ON(!ins->asynch_tx_scb))
  1403. return -EINVAL;
  1404. if (snd_BUG_ON(!ins->spdif_pcm_input_scb))
  1405. return -EINVAL;
  1406. if (snd_BUG_ON(ins->master_mix_scb->next_scb_ptr != ins->asynch_tx_scb))
  1407. return -EINVAL;
  1408. if (snd_BUG_ON(ins->asynch_tx_scb->parent_scb_ptr !=
  1409. ins->master_mix_scb))
  1410. return -EINVAL;
  1411. cs46xx_dsp_remove_scb (chip,ins->spdif_pcm_input_scb);
  1412. cs46xx_dsp_remove_scb (chip,ins->asynch_tx_scb);
  1413. ins->spdif_pcm_input_scb = NULL;
  1414. ins->asynch_tx_scb = NULL;
  1415. /* clear buffer to prevent any undesired noise */
  1416. _dsp_clear_sample_buffer(chip,SPDIFO_IP_OUTPUT_BUFFER1,256);
  1417. /* monitor state */
  1418. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1419. return 0;
  1420. }
  1421. int cs46xx_iec958_pre_open (struct snd_cs46xx *chip)
  1422. {
  1423. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1424. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED ) {
  1425. /* remove AsynchFGTxSCB and and PCMSerialInput_II */
  1426. cs46xx_dsp_disable_spdif_out (chip);
  1427. /* save state */
  1428. ins->spdif_status_out |= DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1429. }
  1430. /* if not enabled already */
  1431. if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_HW_ENABLED) ) {
  1432. cs46xx_dsp_enable_spdif_hw (chip);
  1433. }
  1434. /* Create the asynch. transfer task for playback */
  1435. ins->asynch_tx_scb = cs46xx_dsp_create_asynch_fg_tx_scb(chip,"AsynchFGTxSCB",ASYNCTX_SCB_ADDR,
  1436. SPDIFO_SCB_INST,
  1437. SPDIFO_IP_OUTPUT_BUFFER1,
  1438. ins->master_mix_scb,
  1439. SCB_ON_PARENT_NEXT_SCB);
  1440. /* set spdif channel status value for streaming */
  1441. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_stream);
  1442. ins->spdif_status_out |= DSP_SPDIF_STATUS_PLAYBACK_OPEN;
  1443. return 0;
  1444. }
  1445. int cs46xx_iec958_post_close (struct snd_cs46xx *chip)
  1446. {
  1447. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1448. if (snd_BUG_ON(!ins->asynch_tx_scb))
  1449. return -EINVAL;
  1450. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_PLAYBACK_OPEN;
  1451. /* restore settings */
  1452. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);
  1453. /* deallocate stuff */
  1454. if (ins->spdif_pcm_input_scb != NULL) {
  1455. cs46xx_dsp_remove_scb (chip,ins->spdif_pcm_input_scb);
  1456. ins->spdif_pcm_input_scb = NULL;
  1457. }
  1458. cs46xx_dsp_remove_scb (chip,ins->asynch_tx_scb);
  1459. ins->asynch_tx_scb = NULL;
  1460. /* clear buffer to prevent any undesired noise */
  1461. _dsp_clear_sample_buffer(chip,SPDIFO_IP_OUTPUT_BUFFER1,256);
  1462. /* restore state */
  1463. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED ) {
  1464. cs46xx_dsp_enable_spdif_out (chip);
  1465. }
  1466. return 0;
  1467. }