tegra124-mc.h 1.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H
  3. #define DT_BINDINGS_MEMORY_TEGRA124_MC_H
  4. #define TEGRA_SWGROUP_PTC 0
  5. #define TEGRA_SWGROUP_DC 1
  6. #define TEGRA_SWGROUP_DCB 2
  7. #define TEGRA_SWGROUP_AFI 3
  8. #define TEGRA_SWGROUP_AVPC 4
  9. #define TEGRA_SWGROUP_HDA 5
  10. #define TEGRA_SWGROUP_HC 6
  11. #define TEGRA_SWGROUP_MSENC 7
  12. #define TEGRA_SWGROUP_PPCS 8
  13. #define TEGRA_SWGROUP_SATA 9
  14. #define TEGRA_SWGROUP_VDE 10
  15. #define TEGRA_SWGROUP_MPCORELP 11
  16. #define TEGRA_SWGROUP_MPCORE 12
  17. #define TEGRA_SWGROUP_ISP2 13
  18. #define TEGRA_SWGROUP_XUSB_HOST 14
  19. #define TEGRA_SWGROUP_XUSB_DEV 15
  20. #define TEGRA_SWGROUP_ISP2B 16
  21. #define TEGRA_SWGROUP_TSEC 17
  22. #define TEGRA_SWGROUP_A9AVP 18
  23. #define TEGRA_SWGROUP_GPU 19
  24. #define TEGRA_SWGROUP_SDMMC1A 20
  25. #define TEGRA_SWGROUP_SDMMC2A 21
  26. #define TEGRA_SWGROUP_SDMMC3A 22
  27. #define TEGRA_SWGROUP_SDMMC4A 23
  28. #define TEGRA_SWGROUP_VIC 24
  29. #define TEGRA_SWGROUP_VI 25
  30. #define TEGRA124_MC_RESET_AFI 0
  31. #define TEGRA124_MC_RESET_AVPC 1
  32. #define TEGRA124_MC_RESET_DC 2
  33. #define TEGRA124_MC_RESET_DCB 3
  34. #define TEGRA124_MC_RESET_HC 4
  35. #define TEGRA124_MC_RESET_HDA 5
  36. #define TEGRA124_MC_RESET_ISP2 6
  37. #define TEGRA124_MC_RESET_MPCORE 7
  38. #define TEGRA124_MC_RESET_MPCORELP 8
  39. #define TEGRA124_MC_RESET_MSENC 9
  40. #define TEGRA124_MC_RESET_PPCS 10
  41. #define TEGRA124_MC_RESET_SATA 11
  42. #define TEGRA124_MC_RESET_VDE 12
  43. #define TEGRA124_MC_RESET_VI 13
  44. #define TEGRA124_MC_RESET_VIC 14
  45. #define TEGRA124_MC_RESET_XUSB_HOST 15
  46. #define TEGRA124_MC_RESET_XUSB_DEV 16
  47. #define TEGRA124_MC_RESET_TSEC 17
  48. #define TEGRA124_MC_RESET_SDMMC1 18
  49. #define TEGRA124_MC_RESET_SDMMC2 19
  50. #define TEGRA124_MC_RESET_SDMMC3 20
  51. #define TEGRA124_MC_RESET_SDMMC4 21
  52. #define TEGRA124_MC_RESET_ISP2B 22
  53. #define TEGRA124_MC_RESET_GPU 23
  54. #endif