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linux-phytium
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dt-bindings
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clock
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r8a7796-cpg-mssr.h

r8a7796-cpg-mssr.h 2.0 KB
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  1. /*
    2. 

  2.  * Copyright (C) 2016 Renesas Electronics Corp.
    3. 

  3.  *
    4. 

  4.  * This program is free software; you can redistribute it and/or modify
    5. 

  5.  * it under the terms of the GNU General Public License as published by
    6. 

  6.  * the Free Software Foundation; either version 2 of the License, or
    7. 

  7.  * (at your option) any later version.
    8. 

  8.  */
    9. 

  9. #ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
    10. 

  10. #define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
    11. 

  11. 

  12. #include <dt-bindings/clock/renesas-cpg-mssr.h>
    13. 

  13. 

  14. /* r8a7796 CPG Core Clocks */
    15. 

  15. #define R8A7796_CLK_Z			0
    16. 

  16. #define R8A7796_CLK_Z2			1
    17. 

  17. #define R8A7796_CLK_ZR			2
    18. 

  18. #define R8A7796_CLK_ZG			3
    19. 

  19. #define R8A7796_CLK_ZTR			4
    20. 

  20. #define R8A7796_CLK_ZTRD2		5
    21. 

  21. #define R8A7796_CLK_ZT			6
    22. 

  22. #define R8A7796_CLK_ZX			7
    23. 

  23. #define R8A7796_CLK_S0D1		8
    24. 

  24. #define R8A7796_CLK_S0D2		9
    25. 

  25. #define R8A7796_CLK_S0D3		10
    26. 

  26. #define R8A7796_CLK_S0D4		11
    27. 

  27. #define R8A7796_CLK_S0D6		12
    28. 

  28. #define R8A7796_CLK_S0D8		13
    29. 

  29. #define R8A7796_CLK_S0D12		14
    30. 

  30. #define R8A7796_CLK_S1D1		15
    31. 

  31. #define R8A7796_CLK_S1D2		16
    32. 

  32. #define R8A7796_CLK_S1D4		17
    33. 

  33. #define R8A7796_CLK_S2D1		18
    34. 

  34. #define R8A7796_CLK_S2D2		19
    35. 

  35. #define R8A7796_CLK_S2D4		20
    36. 

  36. #define R8A7796_CLK_S3D1		21
    37. 

  37. #define R8A7796_CLK_S3D2		22
    38. 

  38. #define R8A7796_CLK_S3D4		23
    39. 

  39. #define R8A7796_CLK_LB			24
    40. 

  40. #define R8A7796_CLK_CL			25
    41. 

  41. #define R8A7796_CLK_ZB3			26
    42. 

  42. #define R8A7796_CLK_ZB3D2		27
    43. 

  43. #define R8A7796_CLK_ZB3D4		28
    44. 

  44. #define R8A7796_CLK_CR			29
    45. 

  45. #define R8A7796_CLK_CRD2		30
    46. 

  46. #define R8A7796_CLK_SD0H		31
    47. 

  47. #define R8A7796_CLK_SD0			32
    48. 

  48. #define R8A7796_CLK_SD1H		33
    49. 

  49. #define R8A7796_CLK_SD1			34
    50. 

  50. #define R8A7796_CLK_SD2H		35
    51. 

  51. #define R8A7796_CLK_SD2			36
    52. 

  52. #define R8A7796_CLK_SD3H		37
    53. 

  53. #define R8A7796_CLK_SD3			38
    54. 

  54. #define R8A7796_CLK_SSP2		39
    55. 

  55. #define R8A7796_CLK_SSP1		40
    56. 

  56. #define R8A7796_CLK_SSPRS		41
    57. 

  57. #define R8A7796_CLK_RPC			42
    58. 

  58. #define R8A7796_CLK_RPCD2		43
    59. 

  59. #define R8A7796_CLK_MSO			44
    60. 

  60. #define R8A7796_CLK_CANFD		45
    61. 

  61. #define R8A7796_CLK_HDMI		46
    62. 

  62. #define R8A7796_CLK_CSI0		47
    63. 

  63. #define R8A7796_CLK_CSIREF		48
    64. 

  64. #define R8A7796_CLK_CP			49
    65. 

  65. #define R8A7796_CLK_CPEX		50
    66. 

  66. #define R8A7796_CLK_R			51
    67. 

  67. #define R8A7796_CLK_OSC			52
    68. 

  68. 

  69. #endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */
    70. 

  70.