mtu3_host.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * mtu3_dr.c - dual role switch and host glue layer
  4. *
  5. * Copyright (C) 2016 MediaTek Inc.
  6. *
  7. * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/iopoll.h>
  11. #include <linux/irq.h>
  12. #include <linux/kernel.h>
  13. #include <linux/mfd/syscon.h>
  14. #include <linux/of_device.h>
  15. #include <linux/regmap.h>
  16. #include "mtu3.h"
  17. #include "mtu3_dr.h"
  18. /* mt8173 etc */
  19. #define PERI_WK_CTRL1 0x4
  20. #define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */
  21. #define WC1_IS_EN BIT(25)
  22. #define WC1_IS_P BIT(6) /* polarity for ip sleep */
  23. /* mt2712 etc */
  24. #define PERI_SSUSB_SPM_CTRL 0x0
  25. #define SSC_IP_SLEEP_EN BIT(4)
  26. #define SSC_SPM_INT_EN BIT(1)
  27. enum ssusb_uwk_vers {
  28. SSUSB_UWK_V1 = 1,
  29. SSUSB_UWK_V2,
  30. };
  31. /*
  32. * ip-sleep wakeup mode:
  33. * all clocks can be turn off, but power domain should be kept on
  34. */
  35. static void ssusb_wakeup_ip_sleep_set(struct ssusb_mtk *ssusb, bool enable)
  36. {
  37. u32 reg, msk, val;
  38. switch (ssusb->uwk_vers) {
  39. case SSUSB_UWK_V1:
  40. reg = ssusb->uwk_reg_base + PERI_WK_CTRL1;
  41. msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
  42. val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0;
  43. break;
  44. case SSUSB_UWK_V2:
  45. reg = ssusb->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
  46. msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
  47. val = enable ? msk : 0;
  48. break;
  49. default:
  50. return;
  51. }
  52. regmap_update_bits(ssusb->uwk, reg, msk, val);
  53. }
  54. int ssusb_wakeup_of_property_parse(struct ssusb_mtk *ssusb,
  55. struct device_node *dn)
  56. {
  57. struct of_phandle_args args;
  58. int ret;
  59. /* wakeup function is optional */
  60. ssusb->uwk_en = of_property_read_bool(dn, "wakeup-source");
  61. if (!ssusb->uwk_en)
  62. return 0;
  63. ret = of_parse_phandle_with_fixed_args(dn,
  64. "mediatek,syscon-wakeup", 2, 0, &args);
  65. if (ret)
  66. return ret;
  67. ssusb->uwk_reg_base = args.args[0];
  68. ssusb->uwk_vers = args.args[1];
  69. ssusb->uwk = syscon_node_to_regmap(args.np);
  70. of_node_put(args.np);
  71. dev_info(ssusb->dev, "uwk - reg:0x%x, version:%d\n",
  72. ssusb->uwk_reg_base, ssusb->uwk_vers);
  73. return PTR_ERR_OR_ZERO(ssusb->uwk);
  74. }
  75. void ssusb_wakeup_set(struct ssusb_mtk *ssusb, bool enable)
  76. {
  77. if (ssusb->uwk_en)
  78. ssusb_wakeup_ip_sleep_set(ssusb, enable);
  79. }
  80. static void host_ports_num_get(struct ssusb_mtk *ssusb)
  81. {
  82. u32 xhci_cap;
  83. xhci_cap = mtu3_readl(ssusb->ippc_base, U3D_SSUSB_IP_XHCI_CAP);
  84. ssusb->u2_ports = SSUSB_IP_XHCI_U2_PORT_NUM(xhci_cap);
  85. ssusb->u3_ports = SSUSB_IP_XHCI_U3_PORT_NUM(xhci_cap);
  86. dev_dbg(ssusb->dev, "host - u2_ports:%d, u3_ports:%d\n",
  87. ssusb->u2_ports, ssusb->u3_ports);
  88. }
  89. /* only configure ports will be used later */
  90. int ssusb_host_enable(struct ssusb_mtk *ssusb)
  91. {
  92. void __iomem *ibase = ssusb->ippc_base;
  93. int num_u3p = ssusb->u3_ports;
  94. int num_u2p = ssusb->u2_ports;
  95. int u3_ports_disabed;
  96. u32 check_clk;
  97. u32 value;
  98. int i;
  99. /* power on host ip */
  100. mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN);
  101. /* power on and enable u3 ports except skipped ones */
  102. u3_ports_disabed = 0;
  103. for (i = 0; i < num_u3p; i++) {
  104. if ((0x1 << i) & ssusb->u3p_dis_msk) {
  105. u3_ports_disabed++;
  106. continue;
  107. }
  108. value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
  109. value &= ~(SSUSB_U3_PORT_PDN | SSUSB_U3_PORT_DIS);
  110. value |= SSUSB_U3_PORT_HOST_SEL;
  111. mtu3_writel(ibase, SSUSB_U3_CTRL(i), value);
  112. }
  113. /* power on and enable all u2 ports */
  114. for (i = 0; i < num_u2p; i++) {
  115. value = mtu3_readl(ibase, SSUSB_U2_CTRL(i));
  116. value &= ~(SSUSB_U2_PORT_PDN | SSUSB_U2_PORT_DIS);
  117. value |= SSUSB_U2_PORT_HOST_SEL;
  118. mtu3_writel(ibase, SSUSB_U2_CTRL(i), value);
  119. }
  120. check_clk = SSUSB_XHCI_RST_B_STS;
  121. if (num_u3p > u3_ports_disabed)
  122. check_clk = SSUSB_U3_MAC_RST_B_STS;
  123. return ssusb_check_clocks(ssusb, check_clk);
  124. }
  125. int ssusb_host_disable(struct ssusb_mtk *ssusb, bool suspend)
  126. {
  127. void __iomem *ibase = ssusb->ippc_base;
  128. int num_u3p = ssusb->u3_ports;
  129. int num_u2p = ssusb->u2_ports;
  130. u32 value;
  131. int ret;
  132. int i;
  133. /* power down and disable u3 ports except skipped ones */
  134. for (i = 0; i < num_u3p; i++) {
  135. if ((0x1 << i) & ssusb->u3p_dis_msk)
  136. continue;
  137. value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
  138. value |= SSUSB_U3_PORT_PDN;
  139. value |= suspend ? 0 : SSUSB_U3_PORT_DIS;
  140. mtu3_writel(ibase, SSUSB_U3_CTRL(i), value);
  141. }
  142. /* power down and disable all u2 ports */
  143. for (i = 0; i < num_u2p; i++) {
  144. value = mtu3_readl(ibase, SSUSB_U2_CTRL(i));
  145. value |= SSUSB_U2_PORT_PDN;
  146. value |= suspend ? 0 : SSUSB_U2_PORT_DIS;
  147. mtu3_writel(ibase, SSUSB_U2_CTRL(i), value);
  148. }
  149. /* power down host ip */
  150. mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN);
  151. if (!suspend)
  152. return 0;
  153. /* wait for host ip to sleep */
  154. ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
  155. (value & SSUSB_IP_SLEEP_STS), 100, 100000);
  156. if (ret)
  157. dev_err(ssusb->dev, "ip sleep failed!!!\n");
  158. return ret;
  159. }
  160. static void ssusb_host_setup(struct ssusb_mtk *ssusb)
  161. {
  162. struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
  163. host_ports_num_get(ssusb);
  164. /*
  165. * power on host and power on/enable all ports
  166. * if support OTG, gadget driver will switch port0 to device mode
  167. */
  168. ssusb_host_enable(ssusb);
  169. if (otg_sx->manual_drd_enabled)
  170. ssusb_set_force_mode(ssusb, MTU3_DR_FORCE_HOST);
  171. /* if port0 supports dual-role, works as host mode by default */
  172. ssusb_set_vbus(&ssusb->otg_switch, 1);
  173. }
  174. static void ssusb_host_cleanup(struct ssusb_mtk *ssusb)
  175. {
  176. if (ssusb->is_host)
  177. ssusb_set_vbus(&ssusb->otg_switch, 0);
  178. ssusb_host_disable(ssusb, false);
  179. }
  180. /*
  181. * If host supports multiple ports, the VBUSes(5V) of ports except port0
  182. * which supports OTG are better to be enabled by default in DTS.
  183. * Because the host driver will keep link with devices attached when system
  184. * enters suspend mode, so no need to control VBUSes after initialization.
  185. */
  186. int ssusb_host_init(struct ssusb_mtk *ssusb, struct device_node *parent_dn)
  187. {
  188. struct device *parent_dev = ssusb->dev;
  189. int ret;
  190. ssusb_host_setup(ssusb);
  191. ret = of_platform_populate(parent_dn, NULL, NULL, parent_dev);
  192. if (ret) {
  193. dev_dbg(parent_dev, "failed to create child devices at %pOF\n",
  194. parent_dn);
  195. return ret;
  196. }
  197. dev_info(parent_dev, "xHCI platform device register success...\n");
  198. return 0;
  199. }
  200. void ssusb_host_exit(struct ssusb_mtk *ssusb)
  201. {
  202. of_platform_depopulate(ssusb->dev);
  203. ssusb_host_cleanup(ssusb);
  204. }