platform.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553
  1. // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2. /*
  3. * platform.c - DesignWare HS OTG Controller platform driver
  4. *
  5. * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
  6. *
  7. * Redistribution and use in source and binary forms, with or without
  8. * modification, are permitted provided that the following conditions
  9. * are met:
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions, and the following disclaimer,
  12. * without modification.
  13. * 2. Redistributions in binary form must reproduce the above copyright
  14. * notice, this list of conditions and the following disclaimer in the
  15. * documentation and/or other materials provided with the distribution.
  16. * 3. The names of the above-listed copyright holders may not be used
  17. * to endorse or promote products derived from this software without
  18. * specific prior written permission.
  19. *
  20. * ALTERNATIVELY, this software may be distributed under the terms of the
  21. * GNU General Public License ("GPL") as published by the Free Software
  22. * Foundation; either version 2 of the License, or (at your option) any
  23. * later version.
  24. *
  25. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  26. * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  27. * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  29. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  30. * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  31. * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  32. * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  33. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  34. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36. */
  37. #include <linux/kernel.h>
  38. #include <linux/module.h>
  39. #include <linux/slab.h>
  40. #include <linux/clk.h>
  41. #include <linux/device.h>
  42. #include <linux/dma-mapping.h>
  43. #include <linux/of_device.h>
  44. #include <linux/mutex.h>
  45. #include <linux/platform_device.h>
  46. #include <linux/phy/phy.h>
  47. #include <linux/platform_data/s3c-hsotg.h>
  48. #include <linux/reset.h>
  49. #include <linux/usb/of.h>
  50. #include "core.h"
  51. #include "hcd.h"
  52. #include "debug.h"
  53. static const char dwc2_driver_name[] = "dwc2";
  54. /*
  55. * Check the dr_mode against the module configuration and hardware
  56. * capabilities.
  57. *
  58. * The hardware, module, and dr_mode, can each be set to host, device,
  59. * or otg. Check that all these values are compatible and adjust the
  60. * value of dr_mode if possible.
  61. *
  62. * actual
  63. * HW MOD dr_mode dr_mode
  64. * ------------------------------
  65. * HST HST any : HST
  66. * HST DEV any : ---
  67. * HST OTG any : HST
  68. *
  69. * DEV HST any : ---
  70. * DEV DEV any : DEV
  71. * DEV OTG any : DEV
  72. *
  73. * OTG HST any : HST
  74. * OTG DEV any : DEV
  75. * OTG OTG any : dr_mode
  76. */
  77. static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg)
  78. {
  79. enum usb_dr_mode mode;
  80. hsotg->dr_mode = usb_get_dr_mode(hsotg->dev);
  81. if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN)
  82. hsotg->dr_mode = USB_DR_MODE_OTG;
  83. mode = hsotg->dr_mode;
  84. if (dwc2_hw_is_device(hsotg)) {
  85. if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) {
  86. dev_err(hsotg->dev,
  87. "Controller does not support host mode.\n");
  88. return -EINVAL;
  89. }
  90. mode = USB_DR_MODE_PERIPHERAL;
  91. } else if (dwc2_hw_is_host(hsotg)) {
  92. if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) {
  93. dev_err(hsotg->dev,
  94. "Controller does not support device mode.\n");
  95. return -EINVAL;
  96. }
  97. mode = USB_DR_MODE_HOST;
  98. } else {
  99. if (IS_ENABLED(CONFIG_USB_DWC2_HOST))
  100. mode = USB_DR_MODE_HOST;
  101. else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL))
  102. mode = USB_DR_MODE_PERIPHERAL;
  103. }
  104. if (mode != hsotg->dr_mode) {
  105. dev_warn(hsotg->dev,
  106. "Configuration mismatch. dr_mode forced to %s\n",
  107. mode == USB_DR_MODE_HOST ? "host" : "device");
  108. hsotg->dr_mode = mode;
  109. }
  110. return 0;
  111. }
  112. static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
  113. {
  114. struct platform_device *pdev = to_platform_device(hsotg->dev);
  115. int ret;
  116. ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
  117. hsotg->supplies);
  118. if (ret)
  119. return ret;
  120. if (hsotg->clk) {
  121. ret = clk_prepare_enable(hsotg->clk);
  122. if (ret)
  123. return ret;
  124. }
  125. if (hsotg->uphy) {
  126. ret = usb_phy_init(hsotg->uphy);
  127. } else if (hsotg->plat && hsotg->plat->phy_init) {
  128. ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
  129. } else {
  130. ret = phy_power_on(hsotg->phy);
  131. if (ret == 0)
  132. ret = phy_init(hsotg->phy);
  133. }
  134. return ret;
  135. }
  136. /**
  137. * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
  138. * @hsotg: The driver state
  139. *
  140. * A wrapper for platform code responsible for controlling
  141. * low-level USB platform resources (phy, clock, regulators)
  142. */
  143. int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
  144. {
  145. int ret = __dwc2_lowlevel_hw_enable(hsotg);
  146. if (ret == 0)
  147. hsotg->ll_hw_enabled = true;
  148. return ret;
  149. }
  150. static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
  151. {
  152. struct platform_device *pdev = to_platform_device(hsotg->dev);
  153. int ret = 0;
  154. if (hsotg->uphy) {
  155. usb_phy_shutdown(hsotg->uphy);
  156. } else if (hsotg->plat && hsotg->plat->phy_exit) {
  157. ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
  158. } else {
  159. ret = phy_exit(hsotg->phy);
  160. if (ret == 0)
  161. ret = phy_power_off(hsotg->phy);
  162. }
  163. if (ret)
  164. return ret;
  165. if (hsotg->clk)
  166. clk_disable_unprepare(hsotg->clk);
  167. ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
  168. hsotg->supplies);
  169. return ret;
  170. }
  171. /**
  172. * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
  173. * @hsotg: The driver state
  174. *
  175. * A wrapper for platform code responsible for controlling
  176. * low-level USB platform resources (phy, clock, regulators)
  177. */
  178. int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
  179. {
  180. int ret = __dwc2_lowlevel_hw_disable(hsotg);
  181. if (ret == 0)
  182. hsotg->ll_hw_enabled = false;
  183. return ret;
  184. }
  185. static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
  186. {
  187. int i, ret;
  188. hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2");
  189. if (IS_ERR(hsotg->reset)) {
  190. ret = PTR_ERR(hsotg->reset);
  191. dev_err(hsotg->dev, "error getting reset control %d\n", ret);
  192. return ret;
  193. }
  194. reset_control_deassert(hsotg->reset);
  195. hsotg->reset_ecc = devm_reset_control_get_optional(hsotg->dev, "dwc2-ecc");
  196. if (IS_ERR(hsotg->reset_ecc)) {
  197. ret = PTR_ERR(hsotg->reset_ecc);
  198. dev_err(hsotg->dev, "error getting reset control for ecc %d\n", ret);
  199. return ret;
  200. }
  201. reset_control_deassert(hsotg->reset_ecc);
  202. /* Set default UTMI width */
  203. hsotg->phyif = GUSBCFG_PHYIF16;
  204. /*
  205. * Attempt to find a generic PHY, then look for an old style
  206. * USB PHY and then fall back to pdata
  207. */
  208. hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
  209. if (IS_ERR(hsotg->phy)) {
  210. ret = PTR_ERR(hsotg->phy);
  211. switch (ret) {
  212. case -ENODEV:
  213. case -ENOSYS:
  214. hsotg->phy = NULL;
  215. break;
  216. case -EPROBE_DEFER:
  217. return ret;
  218. default:
  219. dev_err(hsotg->dev, "error getting phy %d\n", ret);
  220. return ret;
  221. }
  222. }
  223. if (!hsotg->phy) {
  224. hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
  225. if (IS_ERR(hsotg->uphy)) {
  226. ret = PTR_ERR(hsotg->uphy);
  227. switch (ret) {
  228. case -ENODEV:
  229. case -ENXIO:
  230. hsotg->uphy = NULL;
  231. break;
  232. case -EPROBE_DEFER:
  233. return ret;
  234. default:
  235. dev_err(hsotg->dev, "error getting usb phy %d\n",
  236. ret);
  237. return ret;
  238. }
  239. }
  240. }
  241. hsotg->plat = dev_get_platdata(hsotg->dev);
  242. if (hsotg->phy) {
  243. /*
  244. * If using the generic PHY framework, check if the PHY bus
  245. * width is 8-bit and set the phyif appropriately.
  246. */
  247. if (phy_get_bus_width(hsotg->phy) == 8)
  248. hsotg->phyif = GUSBCFG_PHYIF8;
  249. }
  250. /* Clock */
  251. hsotg->clk = devm_clk_get(hsotg->dev, "otg");
  252. if (IS_ERR(hsotg->clk)) {
  253. hsotg->clk = NULL;
  254. dev_dbg(hsotg->dev, "cannot get otg clock\n");
  255. }
  256. /* Regulators */
  257. for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
  258. hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
  259. ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
  260. hsotg->supplies);
  261. if (ret) {
  262. dev_err(hsotg->dev, "failed to request supplies: %d\n", ret);
  263. return ret;
  264. }
  265. return 0;
  266. }
  267. /**
  268. * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
  269. * DWC_otg driver
  270. *
  271. * @dev: Platform device
  272. *
  273. * This routine is called, for example, when the rmmod command is executed. The
  274. * device may or may not be electrically present. If it is present, the driver
  275. * stops device processing. Any resources used on behalf of this device are
  276. * freed.
  277. */
  278. static int dwc2_driver_remove(struct platform_device *dev)
  279. {
  280. struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
  281. dwc2_debugfs_exit(hsotg);
  282. if (hsotg->hcd_enabled)
  283. dwc2_hcd_remove(hsotg);
  284. if (hsotg->gadget_enabled)
  285. dwc2_hsotg_remove(hsotg);
  286. if (hsotg->ll_hw_enabled)
  287. dwc2_lowlevel_hw_disable(hsotg);
  288. reset_control_assert(hsotg->reset);
  289. reset_control_assert(hsotg->reset_ecc);
  290. return 0;
  291. }
  292. /**
  293. * dwc2_driver_shutdown() - Called on device shutdown
  294. *
  295. * @dev: Platform device
  296. *
  297. * In specific conditions (involving usb hubs) dwc2 devices can create a
  298. * lot of interrupts, even to the point of overwhelming devices running
  299. * at low frequencies. Some devices need to do special clock handling
  300. * at shutdown-time which may bring the system clock below the threshold
  301. * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs
  302. * prevents reboots/poweroffs from getting stuck in such cases.
  303. */
  304. static void dwc2_driver_shutdown(struct platform_device *dev)
  305. {
  306. struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
  307. disable_irq(hsotg->irq);
  308. }
  309. /**
  310. * dwc2_check_core_endianness() - Returns true if core and AHB have
  311. * opposite endianness.
  312. * @hsotg: Programming view of the DWC_otg controller.
  313. */
  314. static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg)
  315. {
  316. u32 snpsid;
  317. snpsid = ioread32(hsotg->regs + GSNPSID);
  318. if ((snpsid & GSNPSID_ID_MASK) == DWC2_OTG_ID ||
  319. (snpsid & GSNPSID_ID_MASK) == DWC2_FS_IOT_ID ||
  320. (snpsid & GSNPSID_ID_MASK) == DWC2_HS_IOT_ID)
  321. return false;
  322. return true;
  323. }
  324. /**
  325. * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
  326. * driver
  327. *
  328. * @dev: Platform device
  329. *
  330. * This routine creates the driver components required to control the device
  331. * (core, HCD, and PCD) and initializes the device. The driver components are
  332. * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
  333. * in the device private data. This allows the driver to access the dwc2_hsotg
  334. * structure on subsequent calls to driver methods for this device.
  335. */
  336. static int dwc2_driver_probe(struct platform_device *dev)
  337. {
  338. struct dwc2_hsotg *hsotg;
  339. struct resource *res;
  340. int retval;
  341. hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
  342. if (!hsotg)
  343. return -ENOMEM;
  344. hsotg->dev = &dev->dev;
  345. /*
  346. * Use reasonable defaults so platforms don't have to provide these.
  347. */
  348. if (!dev->dev.dma_mask)
  349. dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
  350. retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
  351. if (retval) {
  352. dev_err(&dev->dev, "can't set coherent DMA mask: %d\n", retval);
  353. return retval;
  354. }
  355. res = platform_get_resource(dev, IORESOURCE_MEM, 0);
  356. hsotg->regs = devm_ioremap_resource(&dev->dev, res);
  357. if (IS_ERR(hsotg->regs))
  358. return PTR_ERR(hsotg->regs);
  359. dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
  360. (unsigned long)res->start, hsotg->regs);
  361. retval = dwc2_lowlevel_hw_init(hsotg);
  362. if (retval)
  363. return retval;
  364. spin_lock_init(&hsotg->lock);
  365. hsotg->irq = platform_get_irq(dev, 0);
  366. if (hsotg->irq < 0) {
  367. dev_err(&dev->dev, "missing IRQ resource\n");
  368. return hsotg->irq;
  369. }
  370. dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
  371. hsotg->irq);
  372. retval = devm_request_irq(hsotg->dev, hsotg->irq,
  373. dwc2_handle_common_intr, IRQF_SHARED,
  374. dev_name(hsotg->dev), hsotg);
  375. if (retval)
  376. return retval;
  377. retval = dwc2_lowlevel_hw_enable(hsotg);
  378. if (retval)
  379. return retval;
  380. hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
  381. retval = dwc2_get_dr_mode(hsotg);
  382. if (retval)
  383. goto error;
  384. /*
  385. * Reset before dwc2_get_hwparams() then it could get power-on real
  386. * reset value form registers.
  387. */
  388. retval = dwc2_core_reset(hsotg, false);
  389. if (retval)
  390. goto error;
  391. /* Detect config values from hardware */
  392. retval = dwc2_get_hwparams(hsotg);
  393. if (retval)
  394. goto error;
  395. /*
  396. * For OTG cores, set the force mode bits to reflect the value
  397. * of dr_mode. Force mode bits should not be touched at any
  398. * other time after this.
  399. */
  400. dwc2_force_dr_mode(hsotg);
  401. retval = dwc2_init_params(hsotg);
  402. if (retval)
  403. goto error;
  404. if (hsotg->dr_mode != USB_DR_MODE_HOST) {
  405. retval = dwc2_gadget_init(hsotg);
  406. if (retval)
  407. goto error;
  408. hsotg->gadget_enabled = 1;
  409. }
  410. if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
  411. retval = dwc2_hcd_init(hsotg);
  412. if (retval) {
  413. if (hsotg->gadget_enabled)
  414. dwc2_hsotg_remove(hsotg);
  415. goto error;
  416. }
  417. hsotg->hcd_enabled = 1;
  418. }
  419. platform_set_drvdata(dev, hsotg);
  420. hsotg->hibernated = 0;
  421. dwc2_debugfs_init(hsotg);
  422. /* Gadget code manages lowlevel hw on its own */
  423. if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
  424. dwc2_lowlevel_hw_disable(hsotg);
  425. return 0;
  426. error:
  427. dwc2_lowlevel_hw_disable(hsotg);
  428. return retval;
  429. }
  430. static int __maybe_unused dwc2_suspend(struct device *dev)
  431. {
  432. struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
  433. int ret = 0;
  434. if (dwc2_is_device_mode(dwc2))
  435. dwc2_hsotg_suspend(dwc2);
  436. if (dwc2->ll_hw_enabled)
  437. ret = __dwc2_lowlevel_hw_disable(dwc2);
  438. return ret;
  439. }
  440. static int __maybe_unused dwc2_resume(struct device *dev)
  441. {
  442. struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
  443. int ret = 0;
  444. if (dwc2->ll_hw_enabled) {
  445. ret = __dwc2_lowlevel_hw_enable(dwc2);
  446. if (ret)
  447. return ret;
  448. }
  449. if (dwc2_is_device_mode(dwc2))
  450. ret = dwc2_hsotg_resume(dwc2);
  451. return ret;
  452. }
  453. static const struct dev_pm_ops dwc2_dev_pm_ops = {
  454. SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
  455. };
  456. static struct platform_driver dwc2_platform_driver = {
  457. .driver = {
  458. .name = dwc2_driver_name,
  459. .of_match_table = dwc2_of_match_table,
  460. .pm = &dwc2_dev_pm_ops,
  461. },
  462. .probe = dwc2_driver_probe,
  463. .remove = dwc2_driver_remove,
  464. .shutdown = dwc2_driver_shutdown,
  465. };
  466. module_platform_driver(dwc2_platform_driver);
  467. MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue");
  468. MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>");
  469. MODULE_LICENSE("Dual BSD/GPL");