spi-iproc-qspi.c 4.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164
  1. /*
  2. * Copyright 2016 Broadcom Limited
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/device.h>
  14. #include <linux/io.h>
  15. #include <linux/ioport.h>
  16. #include <linux/module.h>
  17. #include <linux/of.h>
  18. #include <linux/of_address.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/slab.h>
  21. #include "spi-bcm-qspi.h"
  22. #define INTR_BASE_BIT_SHIFT 0x02
  23. #define INTR_COUNT 0x07
  24. struct bcm_iproc_intc {
  25. struct bcm_qspi_soc_intc soc_intc;
  26. struct platform_device *pdev;
  27. void __iomem *int_reg;
  28. void __iomem *int_status_reg;
  29. spinlock_t soclock;
  30. bool big_endian;
  31. };
  32. static u32 bcm_iproc_qspi_get_l2_int_status(struct bcm_qspi_soc_intc *soc_intc)
  33. {
  34. struct bcm_iproc_intc *priv =
  35. container_of(soc_intc, struct bcm_iproc_intc, soc_intc);
  36. void __iomem *mmio = priv->int_status_reg;
  37. int i;
  38. u32 val = 0, sts = 0;
  39. for (i = 0; i < INTR_COUNT; i++) {
  40. if (bcm_qspi_readl(priv->big_endian, mmio + (i * 4)))
  41. val |= 1UL << i;
  42. }
  43. if (val & INTR_MSPI_DONE_MASK)
  44. sts |= MSPI_DONE;
  45. if (val & BSPI_LR_INTERRUPTS_ALL)
  46. sts |= BSPI_DONE;
  47. if (val & BSPI_LR_INTERRUPTS_ERROR)
  48. sts |= BSPI_ERR;
  49. return sts;
  50. }
  51. static void bcm_iproc_qspi_int_ack(struct bcm_qspi_soc_intc *soc_intc, int type)
  52. {
  53. struct bcm_iproc_intc *priv =
  54. container_of(soc_intc, struct bcm_iproc_intc, soc_intc);
  55. void __iomem *mmio = priv->int_status_reg;
  56. u32 mask = get_qspi_mask(type);
  57. int i;
  58. for (i = 0; i < INTR_COUNT; i++) {
  59. if (mask & (1UL << i))
  60. bcm_qspi_writel(priv->big_endian, 1, mmio + (i * 4));
  61. }
  62. }
  63. static void bcm_iproc_qspi_int_set(struct bcm_qspi_soc_intc *soc_intc, int type,
  64. bool en)
  65. {
  66. struct bcm_iproc_intc *priv =
  67. container_of(soc_intc, struct bcm_iproc_intc, soc_intc);
  68. void __iomem *mmio = priv->int_reg;
  69. u32 mask = get_qspi_mask(type);
  70. u32 val;
  71. unsigned long flags;
  72. spin_lock_irqsave(&priv->soclock, flags);
  73. val = bcm_qspi_readl(priv->big_endian, mmio);
  74. if (en)
  75. val = val | (mask << INTR_BASE_BIT_SHIFT);
  76. else
  77. val = val & ~(mask << INTR_BASE_BIT_SHIFT);
  78. bcm_qspi_writel(priv->big_endian, val, mmio);
  79. spin_unlock_irqrestore(&priv->soclock, flags);
  80. }
  81. static int bcm_iproc_probe(struct platform_device *pdev)
  82. {
  83. struct device *dev = &pdev->dev;
  84. struct bcm_iproc_intc *priv;
  85. struct bcm_qspi_soc_intc *soc_intc;
  86. struct resource *res;
  87. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  88. if (!priv)
  89. return -ENOMEM;
  90. soc_intc = &priv->soc_intc;
  91. priv->pdev = pdev;
  92. spin_lock_init(&priv->soclock);
  93. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr_regs");
  94. priv->int_reg = devm_ioremap_resource(dev, res);
  95. if (IS_ERR(priv->int_reg))
  96. return PTR_ERR(priv->int_reg);
  97. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  98. "intr_status_reg");
  99. priv->int_status_reg = devm_ioremap_resource(dev, res);
  100. if (IS_ERR(priv->int_status_reg))
  101. return PTR_ERR(priv->int_status_reg);
  102. priv->big_endian = of_device_is_big_endian(dev->of_node);
  103. bcm_iproc_qspi_int_ack(soc_intc, MSPI_BSPI_DONE);
  104. bcm_iproc_qspi_int_set(soc_intc, MSPI_BSPI_DONE, false);
  105. soc_intc->bcm_qspi_int_ack = bcm_iproc_qspi_int_ack;
  106. soc_intc->bcm_qspi_int_set = bcm_iproc_qspi_int_set;
  107. soc_intc->bcm_qspi_get_int_status = bcm_iproc_qspi_get_l2_int_status;
  108. return bcm_qspi_probe(pdev, soc_intc);
  109. }
  110. static int bcm_iproc_remove(struct platform_device *pdev)
  111. {
  112. return bcm_qspi_remove(pdev);
  113. }
  114. static const struct of_device_id bcm_iproc_of_match[] = {
  115. { .compatible = "brcm,spi-nsp-qspi" },
  116. { .compatible = "brcm,spi-ns2-qspi" },
  117. {},
  118. };
  119. MODULE_DEVICE_TABLE(of, bcm_iproc_of_match);
  120. static struct platform_driver bcm_iproc_driver = {
  121. .probe = bcm_iproc_probe,
  122. .remove = bcm_iproc_remove,
  123. .driver = {
  124. .name = "bcm_iproc",
  125. .pm = &bcm_qspi_pm_ops,
  126. .of_match_table = bcm_iproc_of_match,
  127. }
  128. };
  129. module_platform_driver(bcm_iproc_driver);
  130. MODULE_LICENSE("GPL v2");
  131. MODULE_AUTHOR("Kamal Dasu");
  132. MODULE_DESCRIPTION("SPI flash driver for Broadcom iProc SoCs");