qman_portal.c 9.4 KB

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  1. /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
  2. *
  3. * Redistribution and use in source and binary forms, with or without
  4. * modification, are permitted provided that the following conditions are met:
  5. * * Redistributions of source code must retain the above copyright
  6. * notice, this list of conditions and the following disclaimer.
  7. * * Redistributions in binary form must reproduce the above copyright
  8. * notice, this list of conditions and the following disclaimer in the
  9. * documentation and/or other materials provided with the distribution.
  10. * * Neither the name of Freescale Semiconductor nor the
  11. * names of its contributors may be used to endorse or promote products
  12. * derived from this software without specific prior written permission.
  13. *
  14. * ALTERNATIVELY, this software may be distributed under the terms of the
  15. * GNU General Public License ("GPL") as published by the Free Software
  16. * Foundation, either version 2 of that License or (at your option) any
  17. * later version.
  18. *
  19. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  20. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  21. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  22. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  23. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  25. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  26. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29. */
  30. #include "qman_priv.h"
  31. struct qman_portal *qman_dma_portal;
  32. EXPORT_SYMBOL(qman_dma_portal);
  33. /* Enable portal interupts (as opposed to polling mode) */
  34. #define CONFIG_FSL_DPA_PIRQ_SLOW 1
  35. #define CONFIG_FSL_DPA_PIRQ_FAST 1
  36. static struct cpumask portal_cpus;
  37. /* protect qman global registers and global data shared among portals */
  38. static DEFINE_SPINLOCK(qman_lock);
  39. static void portal_set_cpu(struct qm_portal_config *pcfg, int cpu)
  40. {
  41. #ifdef CONFIG_FSL_PAMU
  42. struct device *dev = pcfg->dev;
  43. int window_count = 1;
  44. struct iommu_domain_geometry geom_attr;
  45. struct pamu_stash_attribute stash_attr;
  46. int ret;
  47. pcfg->iommu_domain = iommu_domain_alloc(&platform_bus_type);
  48. if (!pcfg->iommu_domain) {
  49. dev_err(dev, "%s(): iommu_domain_alloc() failed", __func__);
  50. goto no_iommu;
  51. }
  52. geom_attr.aperture_start = 0;
  53. geom_attr.aperture_end =
  54. ((dma_addr_t)1 << min(8 * sizeof(dma_addr_t), (size_t)36)) - 1;
  55. geom_attr.force_aperture = true;
  56. ret = iommu_domain_set_attr(pcfg->iommu_domain, DOMAIN_ATTR_GEOMETRY,
  57. &geom_attr);
  58. if (ret < 0) {
  59. dev_err(dev, "%s(): iommu_domain_set_attr() = %d", __func__,
  60. ret);
  61. goto out_domain_free;
  62. }
  63. ret = iommu_domain_set_attr(pcfg->iommu_domain, DOMAIN_ATTR_WINDOWS,
  64. &window_count);
  65. if (ret < 0) {
  66. dev_err(dev, "%s(): iommu_domain_set_attr() = %d", __func__,
  67. ret);
  68. goto out_domain_free;
  69. }
  70. stash_attr.cpu = cpu;
  71. stash_attr.cache = PAMU_ATTR_CACHE_L1;
  72. ret = iommu_domain_set_attr(pcfg->iommu_domain,
  73. DOMAIN_ATTR_FSL_PAMU_STASH,
  74. &stash_attr);
  75. if (ret < 0) {
  76. dev_err(dev, "%s(): iommu_domain_set_attr() = %d",
  77. __func__, ret);
  78. goto out_domain_free;
  79. }
  80. ret = iommu_domain_window_enable(pcfg->iommu_domain, 0, 0, 1ULL << 36,
  81. IOMMU_READ | IOMMU_WRITE);
  82. if (ret < 0) {
  83. dev_err(dev, "%s(): iommu_domain_window_enable() = %d",
  84. __func__, ret);
  85. goto out_domain_free;
  86. }
  87. ret = iommu_attach_device(pcfg->iommu_domain, dev);
  88. if (ret < 0) {
  89. dev_err(dev, "%s(): iommu_device_attach() = %d", __func__,
  90. ret);
  91. goto out_domain_free;
  92. }
  93. ret = iommu_domain_set_attr(pcfg->iommu_domain,
  94. DOMAIN_ATTR_FSL_PAMU_ENABLE,
  95. &window_count);
  96. if (ret < 0) {
  97. dev_err(dev, "%s(): iommu_domain_set_attr() = %d", __func__,
  98. ret);
  99. goto out_detach_device;
  100. }
  101. no_iommu:
  102. #endif
  103. qman_set_sdest(pcfg->channel, cpu);
  104. return;
  105. #ifdef CONFIG_FSL_PAMU
  106. out_detach_device:
  107. iommu_detach_device(pcfg->iommu_domain, NULL);
  108. out_domain_free:
  109. iommu_domain_free(pcfg->iommu_domain);
  110. pcfg->iommu_domain = NULL;
  111. #endif
  112. }
  113. static struct qman_portal *init_pcfg(struct qm_portal_config *pcfg)
  114. {
  115. struct qman_portal *p;
  116. u32 irq_sources = 0;
  117. /* We need the same LIODN offset for all portals */
  118. qman_liodn_fixup(pcfg->channel);
  119. pcfg->iommu_domain = NULL;
  120. portal_set_cpu(pcfg, pcfg->cpu);
  121. p = qman_create_affine_portal(pcfg, NULL);
  122. if (!p) {
  123. dev_crit(pcfg->dev, "%s: Portal failure on cpu %d\n",
  124. __func__, pcfg->cpu);
  125. return NULL;
  126. }
  127. /* Determine what should be interrupt-vs-poll driven */
  128. #ifdef CONFIG_FSL_DPA_PIRQ_SLOW
  129. irq_sources |= QM_PIRQ_EQCI | QM_PIRQ_EQRI | QM_PIRQ_MRI |
  130. QM_PIRQ_CSCI;
  131. #endif
  132. #ifdef CONFIG_FSL_DPA_PIRQ_FAST
  133. irq_sources |= QM_PIRQ_DQRI;
  134. #endif
  135. qman_p_irqsource_add(p, irq_sources);
  136. spin_lock(&qman_lock);
  137. if (cpumask_equal(&portal_cpus, cpu_possible_mask)) {
  138. /* all assigned portals are initialized now */
  139. qman_init_cgr_all();
  140. }
  141. if (!qman_dma_portal)
  142. qman_dma_portal = p;
  143. spin_unlock(&qman_lock);
  144. dev_info(pcfg->dev, "Portal initialised, cpu %d\n", pcfg->cpu);
  145. return p;
  146. }
  147. static void qman_portal_update_sdest(const struct qm_portal_config *pcfg,
  148. unsigned int cpu)
  149. {
  150. #ifdef CONFIG_FSL_PAMU /* TODO */
  151. struct pamu_stash_attribute stash_attr;
  152. int ret;
  153. if (pcfg->iommu_domain) {
  154. stash_attr.cpu = cpu;
  155. stash_attr.cache = PAMU_ATTR_CACHE_L1;
  156. ret = iommu_domain_set_attr(pcfg->iommu_domain,
  157. DOMAIN_ATTR_FSL_PAMU_STASH, &stash_attr);
  158. if (ret < 0) {
  159. dev_err(pcfg->dev,
  160. "Failed to update pamu stash setting\n");
  161. return;
  162. }
  163. }
  164. #endif
  165. qman_set_sdest(pcfg->channel, cpu);
  166. }
  167. static int qman_offline_cpu(unsigned int cpu)
  168. {
  169. struct qman_portal *p;
  170. const struct qm_portal_config *pcfg;
  171. p = affine_portals[cpu];
  172. if (p) {
  173. pcfg = qman_get_qm_portal_config(p);
  174. if (pcfg) {
  175. irq_set_affinity(pcfg->irq, cpumask_of(0));
  176. qman_portal_update_sdest(pcfg, 0);
  177. }
  178. }
  179. return 0;
  180. }
  181. static int qman_online_cpu(unsigned int cpu)
  182. {
  183. struct qman_portal *p;
  184. const struct qm_portal_config *pcfg;
  185. p = affine_portals[cpu];
  186. if (p) {
  187. pcfg = qman_get_qm_portal_config(p);
  188. if (pcfg) {
  189. irq_set_affinity(pcfg->irq, cpumask_of(cpu));
  190. qman_portal_update_sdest(pcfg, cpu);
  191. }
  192. }
  193. return 0;
  194. }
  195. static int qman_portal_probe(struct platform_device *pdev)
  196. {
  197. struct device *dev = &pdev->dev;
  198. struct device_node *node = dev->of_node;
  199. struct qm_portal_config *pcfg;
  200. struct resource *addr_phys[2];
  201. int irq, cpu, err;
  202. u32 val;
  203. err = qman_is_probed();
  204. if (!err)
  205. return -EPROBE_DEFER;
  206. if (err < 0) {
  207. dev_err(&pdev->dev, "failing probe due to qman probe error\n");
  208. return -ENODEV;
  209. }
  210. pcfg = devm_kmalloc(dev, sizeof(*pcfg), GFP_KERNEL);
  211. if (!pcfg)
  212. return -ENOMEM;
  213. pcfg->dev = dev;
  214. addr_phys[0] = platform_get_resource(pdev, IORESOURCE_MEM,
  215. DPAA_PORTAL_CE);
  216. if (!addr_phys[0]) {
  217. dev_err(dev, "Can't get %pOF property 'reg::CE'\n", node);
  218. return -ENXIO;
  219. }
  220. addr_phys[1] = platform_get_resource(pdev, IORESOURCE_MEM,
  221. DPAA_PORTAL_CI);
  222. if (!addr_phys[1]) {
  223. dev_err(dev, "Can't get %pOF property 'reg::CI'\n", node);
  224. return -ENXIO;
  225. }
  226. err = of_property_read_u32(node, "cell-index", &val);
  227. if (err) {
  228. dev_err(dev, "Can't get %pOF property 'cell-index'\n", node);
  229. return err;
  230. }
  231. pcfg->channel = val;
  232. pcfg->cpu = -1;
  233. irq = platform_get_irq(pdev, 0);
  234. if (irq <= 0) {
  235. dev_err(dev, "Can't get %pOF IRQ\n", node);
  236. return -ENXIO;
  237. }
  238. pcfg->irq = irq;
  239. pcfg->addr_virt_ce = memremap(addr_phys[0]->start,
  240. resource_size(addr_phys[0]),
  241. QBMAN_MEMREMAP_ATTR);
  242. if (!pcfg->addr_virt_ce) {
  243. dev_err(dev, "memremap::CE failed\n");
  244. goto err_ioremap1;
  245. }
  246. pcfg->addr_virt_ci = ioremap(addr_phys[1]->start,
  247. resource_size(addr_phys[1]));
  248. if (!pcfg->addr_virt_ci) {
  249. dev_err(dev, "ioremap::CI failed\n");
  250. goto err_ioremap2;
  251. }
  252. pcfg->pools = qm_get_pools_sdqcr();
  253. spin_lock(&qman_lock);
  254. cpu = cpumask_next_zero(-1, &portal_cpus);
  255. if (cpu >= nr_cpu_ids) {
  256. /* unassigned portal, skip init */
  257. spin_unlock(&qman_lock);
  258. return 0;
  259. }
  260. cpumask_set_cpu(cpu, &portal_cpus);
  261. spin_unlock(&qman_lock);
  262. pcfg->cpu = cpu;
  263. if (dma_set_mask(dev, DMA_BIT_MASK(40))) {
  264. dev_err(dev, "dma_set_mask() failed\n");
  265. goto err_portal_init;
  266. }
  267. if (!init_pcfg(pcfg)) {
  268. dev_err(dev, "portal init failed\n");
  269. goto err_portal_init;
  270. }
  271. /* clear irq affinity if assigned cpu is offline */
  272. if (!cpu_online(cpu))
  273. qman_offline_cpu(cpu);
  274. return 0;
  275. err_portal_init:
  276. iounmap(pcfg->addr_virt_ci);
  277. err_ioremap2:
  278. memunmap(pcfg->addr_virt_ce);
  279. err_ioremap1:
  280. return -ENXIO;
  281. }
  282. static const struct of_device_id qman_portal_ids[] = {
  283. {
  284. .compatible = "fsl,qman-portal",
  285. },
  286. {}
  287. };
  288. MODULE_DEVICE_TABLE(of, qman_portal_ids);
  289. static struct platform_driver qman_portal_driver = {
  290. .driver = {
  291. .name = KBUILD_MODNAME,
  292. .of_match_table = qman_portal_ids,
  293. },
  294. .probe = qman_portal_probe,
  295. };
  296. static int __init qman_portal_driver_register(struct platform_driver *drv)
  297. {
  298. int ret;
  299. ret = platform_driver_register(drv);
  300. if (ret < 0)
  301. return ret;
  302. ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
  303. "soc/qman_portal:online",
  304. qman_online_cpu, qman_offline_cpu);
  305. if (ret < 0) {
  306. pr_err("qman: failed to register hotplug callbacks.\n");
  307. platform_driver_unregister(drv);
  308. return ret;
  309. }
  310. return 0;
  311. }
  312. module_driver(qman_portal_driver,
  313. qman_portal_driver_register, platform_driver_unregister);