halbtc8192e2ant.c 101 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2012 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * The full GNU General Public License is included in this distribution in the
  15. * file called LICENSE.
  16. *
  17. * Contact Information:
  18. * wlanfae <wlanfae@realtek.com>
  19. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20. * Hsinchu 300, Taiwan.
  21. *
  22. * Larry Finger <Larry.Finger@lwfinger.net>
  23. *
  24. *****************************************************************************/
  25. /**************************************************************
  26. * Description:
  27. *
  28. * This file is for RTL8192E Co-exist mechanism
  29. *
  30. * History
  31. * 2012/11/15 Cosa first check in.
  32. *
  33. **************************************************************/
  34. /**************************************************************
  35. * include files
  36. **************************************************************/
  37. #include "halbt_precomp.h"
  38. /**************************************************************
  39. * Global variables, these are static variables
  40. **************************************************************/
  41. static struct coex_dm_8192e_2ant glcoex_dm_8192e_2ant;
  42. static struct coex_dm_8192e_2ant *coex_dm = &glcoex_dm_8192e_2ant;
  43. static struct coex_sta_8192e_2ant glcoex_sta_8192e_2ant;
  44. static struct coex_sta_8192e_2ant *coex_sta = &glcoex_sta_8192e_2ant;
  45. static const char *const glbt_info_src_8192e_2ant[] = {
  46. "BT Info[wifi fw]",
  47. "BT Info[bt rsp]",
  48. "BT Info[bt auto report]",
  49. };
  50. static u32 glcoex_ver_date_8192e_2ant = 20130902;
  51. static u32 glcoex_ver_8192e_2ant = 0x34;
  52. /**************************************************************
  53. * local function proto type if needed
  54. **************************************************************/
  55. /**************************************************************
  56. * local function start with btc8192e2ant_
  57. **************************************************************/
  58. static u8 btc8192e2ant_bt_rssi_state(struct btc_coexist *btcoexist,
  59. u8 level_num, u8 rssi_thresh,
  60. u8 rssi_thresh1)
  61. {
  62. struct rtl_priv *rtlpriv = btcoexist->adapter;
  63. int bt_rssi = 0;
  64. u8 bt_rssi_state = coex_sta->pre_bt_rssi_state;
  65. bt_rssi = coex_sta->bt_rssi;
  66. if (level_num == 2) {
  67. if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  68. (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  69. if (bt_rssi >=
  70. (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
  71. bt_rssi_state = BTC_RSSI_STATE_HIGH;
  72. else
  73. bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
  74. } else {
  75. if (bt_rssi < rssi_thresh)
  76. bt_rssi_state = BTC_RSSI_STATE_LOW;
  77. else
  78. bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
  79. }
  80. } else if (level_num == 3) {
  81. if (rssi_thresh > rssi_thresh1) {
  82. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  83. "[BTCoex], BT Rssi thresh error!!\n");
  84. return coex_sta->pre_bt_rssi_state;
  85. }
  86. if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  87. (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  88. if (bt_rssi >=
  89. (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
  90. bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
  91. else
  92. bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
  93. } else if ((coex_sta->pre_bt_rssi_state ==
  94. BTC_RSSI_STATE_MEDIUM) ||
  95. (coex_sta->pre_bt_rssi_state ==
  96. BTC_RSSI_STATE_STAY_MEDIUM)) {
  97. if (bt_rssi >= (rssi_thresh1 +
  98. BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
  99. bt_rssi_state = BTC_RSSI_STATE_HIGH;
  100. else if (bt_rssi < rssi_thresh)
  101. bt_rssi_state = BTC_RSSI_STATE_LOW;
  102. else
  103. bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
  104. } else {
  105. if (bt_rssi < rssi_thresh1)
  106. bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
  107. else
  108. bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
  109. }
  110. }
  111. coex_sta->pre_bt_rssi_state = bt_rssi_state;
  112. return bt_rssi_state;
  113. }
  114. static u8 btc8192e2ant_wifi_rssi_state(struct btc_coexist *btcoexist,
  115. u8 index, u8 level_num, u8 rssi_thresh,
  116. u8 rssi_thresh1)
  117. {
  118. struct rtl_priv *rtlpriv = btcoexist->adapter;
  119. int wifi_rssi = 0;
  120. u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
  121. btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
  122. if (level_num == 2) {
  123. if ((coex_sta->pre_wifi_rssi_state[index] ==
  124. BTC_RSSI_STATE_LOW) ||
  125. (coex_sta->pre_wifi_rssi_state[index] ==
  126. BTC_RSSI_STATE_STAY_LOW)) {
  127. if (wifi_rssi >=
  128. (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
  129. wifi_rssi_state = BTC_RSSI_STATE_HIGH;
  130. else
  131. wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
  132. } else {
  133. if (wifi_rssi < rssi_thresh)
  134. wifi_rssi_state = BTC_RSSI_STATE_LOW;
  135. else
  136. wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
  137. }
  138. } else if (level_num == 3) {
  139. if (rssi_thresh > rssi_thresh1) {
  140. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  141. "[BTCoex], wifi RSSI thresh error!!\n");
  142. return coex_sta->pre_wifi_rssi_state[index];
  143. }
  144. if ((coex_sta->pre_wifi_rssi_state[index] ==
  145. BTC_RSSI_STATE_LOW) ||
  146. (coex_sta->pre_wifi_rssi_state[index] ==
  147. BTC_RSSI_STATE_STAY_LOW)) {
  148. if (wifi_rssi >=
  149. (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
  150. wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
  151. else
  152. wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
  153. } else if ((coex_sta->pre_wifi_rssi_state[index] ==
  154. BTC_RSSI_STATE_MEDIUM) ||
  155. (coex_sta->pre_wifi_rssi_state[index] ==
  156. BTC_RSSI_STATE_STAY_MEDIUM)) {
  157. if (wifi_rssi >= (rssi_thresh1 +
  158. BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
  159. wifi_rssi_state = BTC_RSSI_STATE_HIGH;
  160. else if (wifi_rssi < rssi_thresh)
  161. wifi_rssi_state = BTC_RSSI_STATE_LOW;
  162. else
  163. wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
  164. } else {
  165. if (wifi_rssi < rssi_thresh1)
  166. wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
  167. else
  168. wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
  169. }
  170. }
  171. coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
  172. return wifi_rssi_state;
  173. }
  174. static void btc8192e2ant_monitor_bt_enable_disable(struct btc_coexist
  175. *btcoexist)
  176. {
  177. struct rtl_priv *rtlpriv = btcoexist->adapter;
  178. static bool pre_bt_disabled;
  179. static u32 bt_disable_cnt;
  180. bool bt_active = true, bt_disabled = false;
  181. /* This function check if bt is disabled */
  182. if (coex_sta->high_priority_tx == 0 &&
  183. coex_sta->high_priority_rx == 0 &&
  184. coex_sta->low_priority_tx == 0 &&
  185. coex_sta->low_priority_rx == 0)
  186. bt_active = false;
  187. if (coex_sta->high_priority_tx == 0xffff &&
  188. coex_sta->high_priority_rx == 0xffff &&
  189. coex_sta->low_priority_tx == 0xffff &&
  190. coex_sta->low_priority_rx == 0xffff)
  191. bt_active = false;
  192. if (bt_active) {
  193. bt_disable_cnt = 0;
  194. bt_disabled = false;
  195. btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
  196. &bt_disabled);
  197. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  198. "[BTCoex], BT is enabled !!\n");
  199. } else {
  200. bt_disable_cnt++;
  201. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  202. "[BTCoex], bt all counters = 0, %d times!!\n",
  203. bt_disable_cnt);
  204. if (bt_disable_cnt >= 2) {
  205. bt_disabled = true;
  206. btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
  207. &bt_disabled);
  208. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  209. "[BTCoex], BT is disabled !!\n");
  210. }
  211. }
  212. if (pre_bt_disabled != bt_disabled) {
  213. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  214. "[BTCoex], BT is from %s to %s!!\n",
  215. (pre_bt_disabled ? "disabled" : "enabled"),
  216. (bt_disabled ? "disabled" : "enabled"));
  217. pre_bt_disabled = bt_disabled;
  218. }
  219. }
  220. static u32 btc8192e2ant_decide_ra_mask(struct btc_coexist *btcoexist,
  221. u8 ss_type, u32 ra_mask_type)
  222. {
  223. u32 dis_ra_mask = 0x0;
  224. switch (ra_mask_type) {
  225. case 0: /* normal mode */
  226. if (ss_type == 2)
  227. dis_ra_mask = 0x0; /* enable 2ss */
  228. else
  229. dis_ra_mask = 0xfff00000; /* disable 2ss */
  230. break;
  231. case 1: /* disable cck 1/2 */
  232. if (ss_type == 2)
  233. dis_ra_mask = 0x00000003; /* enable 2ss */
  234. else
  235. dis_ra_mask = 0xfff00003; /* disable 2ss */
  236. break;
  237. case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
  238. if (ss_type == 2)
  239. dis_ra_mask = 0x0001f1f7; /* enable 2ss */
  240. else
  241. dis_ra_mask = 0xfff1f1f7; /* disable 2ss */
  242. break;
  243. default:
  244. break;
  245. }
  246. return dis_ra_mask;
  247. }
  248. static void btc8192e2ant_update_ra_mask(struct btc_coexist *btcoexist,
  249. bool force_exec, u32 dis_rate_mask)
  250. {
  251. coex_dm->cur_ra_mask = dis_rate_mask;
  252. if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
  253. btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
  254. &coex_dm->cur_ra_mask);
  255. coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
  256. }
  257. static void btc8192e2ant_auto_rate_fallback_retry(struct btc_coexist *btcoexist,
  258. bool force_exec, u8 type)
  259. {
  260. bool wifi_under_b_mode = false;
  261. coex_dm->cur_arfr_type = type;
  262. if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
  263. switch (coex_dm->cur_arfr_type) {
  264. case 0: /* normal mode */
  265. btcoexist->btc_write_4byte(btcoexist, 0x430,
  266. coex_dm->backup_arfr_cnt1);
  267. btcoexist->btc_write_4byte(btcoexist, 0x434,
  268. coex_dm->backup_arfr_cnt2);
  269. break;
  270. case 1:
  271. btcoexist->btc_get(btcoexist,
  272. BTC_GET_BL_WIFI_UNDER_B_MODE,
  273. &wifi_under_b_mode);
  274. if (wifi_under_b_mode) {
  275. btcoexist->btc_write_4byte(btcoexist, 0x430,
  276. 0x0);
  277. btcoexist->btc_write_4byte(btcoexist, 0x434,
  278. 0x01010101);
  279. } else {
  280. btcoexist->btc_write_4byte(btcoexist, 0x430,
  281. 0x0);
  282. btcoexist->btc_write_4byte(btcoexist, 0x434,
  283. 0x04030201);
  284. }
  285. break;
  286. default:
  287. break;
  288. }
  289. }
  290. coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
  291. }
  292. static void btc8192e2ant_retry_limit(struct btc_coexist *btcoexist,
  293. bool force_exec, u8 type)
  294. {
  295. coex_dm->cur_retry_limit_type = type;
  296. if (force_exec || (coex_dm->pre_retry_limit_type !=
  297. coex_dm->cur_retry_limit_type)) {
  298. switch (coex_dm->cur_retry_limit_type) {
  299. case 0: /* normal mode */
  300. btcoexist->btc_write_2byte(btcoexist, 0x42a,
  301. coex_dm->backup_retry_limit);
  302. break;
  303. case 1: /* retry limit = 8 */
  304. btcoexist->btc_write_2byte(btcoexist, 0x42a, 0x0808);
  305. break;
  306. default:
  307. break;
  308. }
  309. }
  310. coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
  311. }
  312. static void btc8192e2ant_ampdu_maxtime(struct btc_coexist *btcoexist,
  313. bool force_exec, u8 type)
  314. {
  315. coex_dm->cur_ampdu_time_type = type;
  316. if (force_exec || (coex_dm->pre_ampdu_time_type !=
  317. coex_dm->cur_ampdu_time_type)) {
  318. switch (coex_dm->cur_ampdu_time_type) {
  319. case 0: /* normal mode */
  320. btcoexist->btc_write_1byte(btcoexist, 0x456,
  321. coex_dm->backup_ampdu_maxtime);
  322. break;
  323. case 1: /* AMPDU time = 0x38 * 32us */
  324. btcoexist->btc_write_1byte(btcoexist, 0x456, 0x38);
  325. break;
  326. default:
  327. break;
  328. }
  329. }
  330. coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
  331. }
  332. static void btc8192e2ant_limited_tx(struct btc_coexist *btcoexist,
  333. bool force_exec, u8 ra_mask_type,
  334. u8 arfr_type, u8 retry_limit_type,
  335. u8 ampdu_time_type)
  336. {
  337. u32 dis_ra_mask = 0x0;
  338. coex_dm->cur_ra_mask_type = ra_mask_type;
  339. dis_ra_mask =
  340. btc8192e2ant_decide_ra_mask(btcoexist, coex_dm->cur_ss_type,
  341. ra_mask_type);
  342. btc8192e2ant_update_ra_mask(btcoexist, force_exec, dis_ra_mask);
  343. btc8192e2ant_auto_rate_fallback_retry(btcoexist, force_exec, arfr_type);
  344. btc8192e2ant_retry_limit(btcoexist, force_exec, retry_limit_type);
  345. btc8192e2ant_ampdu_maxtime(btcoexist, force_exec, ampdu_time_type);
  346. }
  347. static void btc8192e2ant_limited_rx(struct btc_coexist *btcoexist,
  348. bool force_exec, bool rej_ap_agg_pkt,
  349. bool bt_ctrl_agg_buf_size,
  350. u8 agg_buf_size)
  351. {
  352. bool reject_rx_agg = rej_ap_agg_pkt;
  353. bool bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
  354. u8 rx_agg_size = agg_buf_size;
  355. /*********************************************
  356. * Rx Aggregation related setting
  357. *********************************************/
  358. btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
  359. &reject_rx_agg);
  360. /* decide BT control aggregation buf size or not */
  361. btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
  362. &bt_ctrl_rx_agg_size);
  363. /* aggregation buf size, only work
  364. * when BT control Rx aggregation size.
  365. */
  366. btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
  367. /* real update aggregation setting */
  368. btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
  369. }
  370. static void btc8192e2ant_monitor_bt_ctr(struct btc_coexist *btcoexist)
  371. {
  372. struct rtl_priv *rtlpriv = btcoexist->adapter;
  373. u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
  374. u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
  375. reg_hp_txrx = 0x770;
  376. reg_lp_txrx = 0x774;
  377. u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
  378. reg_hp_tx = u32tmp & MASKLWORD;
  379. reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
  380. u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
  381. reg_lp_tx = u32tmp & MASKLWORD;
  382. reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
  383. coex_sta->high_priority_tx = reg_hp_tx;
  384. coex_sta->high_priority_rx = reg_hp_rx;
  385. coex_sta->low_priority_tx = reg_lp_tx;
  386. coex_sta->low_priority_rx = reg_lp_rx;
  387. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  388. "[BTCoex] High Priority Tx/Rx (reg 0x%x) = 0x%x(%d)/0x%x(%d)\n",
  389. reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx);
  390. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  391. "[BTCoex] Low Priority Tx/Rx (reg 0x%x) = 0x%x(%d)/0x%x(%d)\n",
  392. reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx);
  393. /* reset counter */
  394. btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
  395. }
  396. static void btc8192e2ant_query_bt_info(struct btc_coexist *btcoexist)
  397. {
  398. struct rtl_priv *rtlpriv = btcoexist->adapter;
  399. u8 h2c_parameter[1] = {0};
  400. coex_sta->c2h_bt_info_req_sent = true;
  401. h2c_parameter[0] |= BIT0; /* trigger */
  402. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  403. "[BTCoex], Query Bt Info, FW write 0x61 = 0x%x\n",
  404. h2c_parameter[0]);
  405. btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
  406. }
  407. static
  408. bool btc8192e2ant_is_wifi_status_changed(struct btc_coexist *btcoexist)
  409. {
  410. static bool pre_wifi_busy = false, pre_under_4way = false,
  411. pre_bt_hs_on = false;
  412. bool wifi_busy = false, under_4way = false, bt_hs_on = false;
  413. bool wifi_connected = false;
  414. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
  415. &wifi_connected);
  416. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
  417. btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
  418. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
  419. &under_4way);
  420. if (wifi_connected) {
  421. if (wifi_busy != pre_wifi_busy) {
  422. pre_wifi_busy = wifi_busy;
  423. return true;
  424. }
  425. if (under_4way != pre_under_4way) {
  426. pre_under_4way = under_4way;
  427. return true;
  428. }
  429. if (bt_hs_on != pre_bt_hs_on) {
  430. pre_bt_hs_on = bt_hs_on;
  431. return true;
  432. }
  433. }
  434. return false;
  435. }
  436. static void btc8192e2ant_update_bt_link_info(struct btc_coexist *btcoexist)
  437. {
  438. struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
  439. bool bt_hs_on = false;
  440. btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
  441. bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
  442. bt_link_info->sco_exist = coex_sta->sco_exist;
  443. bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
  444. bt_link_info->pan_exist = coex_sta->pan_exist;
  445. bt_link_info->hid_exist = coex_sta->hid_exist;
  446. /* work around for HS mode. */
  447. if (bt_hs_on) {
  448. bt_link_info->pan_exist = true;
  449. bt_link_info->bt_link_exist = true;
  450. }
  451. /* check if Sco only */
  452. if (bt_link_info->sco_exist &&
  453. !bt_link_info->a2dp_exist &&
  454. !bt_link_info->pan_exist &&
  455. !bt_link_info->hid_exist)
  456. bt_link_info->sco_only = true;
  457. else
  458. bt_link_info->sco_only = false;
  459. /* check if A2dp only */
  460. if (!bt_link_info->sco_exist &&
  461. bt_link_info->a2dp_exist &&
  462. !bt_link_info->pan_exist &&
  463. !bt_link_info->hid_exist)
  464. bt_link_info->a2dp_only = true;
  465. else
  466. bt_link_info->a2dp_only = false;
  467. /* check if Pan only */
  468. if (!bt_link_info->sco_exist &&
  469. !bt_link_info->a2dp_exist &&
  470. bt_link_info->pan_exist &&
  471. !bt_link_info->hid_exist)
  472. bt_link_info->pan_only = true;
  473. else
  474. bt_link_info->pan_only = false;
  475. /* check if Hid only */
  476. if (!bt_link_info->sco_exist &&
  477. !bt_link_info->a2dp_exist &&
  478. !bt_link_info->pan_exist &&
  479. bt_link_info->hid_exist)
  480. bt_link_info->hid_only = true;
  481. else
  482. bt_link_info->hid_only = false;
  483. }
  484. static u8 btc8192e2ant_action_algorithm(struct btc_coexist *btcoexist)
  485. {
  486. struct rtl_priv *rtlpriv = btcoexist->adapter;
  487. struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
  488. struct btc_stack_info *stack_info = &btcoexist->stack_info;
  489. bool bt_hs_on = false;
  490. u8 algorithm = BT_8192E_2ANT_COEX_ALGO_UNDEFINED;
  491. u8 num_of_diff_profile = 0;
  492. btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
  493. if (!bt_link_info->bt_link_exist) {
  494. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  495. "No BT link exists!!!\n");
  496. return algorithm;
  497. }
  498. if (bt_link_info->sco_exist)
  499. num_of_diff_profile++;
  500. if (bt_link_info->hid_exist)
  501. num_of_diff_profile++;
  502. if (bt_link_info->pan_exist)
  503. num_of_diff_profile++;
  504. if (bt_link_info->a2dp_exist)
  505. num_of_diff_profile++;
  506. if (num_of_diff_profile == 1) {
  507. if (bt_link_info->sco_exist) {
  508. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  509. "SCO only\n");
  510. algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
  511. } else {
  512. if (bt_link_info->hid_exist) {
  513. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  514. "HID only\n");
  515. algorithm = BT_8192E_2ANT_COEX_ALGO_HID;
  516. } else if (bt_link_info->a2dp_exist) {
  517. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  518. "A2DP only\n");
  519. algorithm = BT_8192E_2ANT_COEX_ALGO_A2DP;
  520. } else if (bt_link_info->pan_exist) {
  521. if (bt_hs_on) {
  522. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  523. DBG_LOUD,
  524. "PAN(HS) only\n");
  525. algorithm =
  526. BT_8192E_2ANT_COEX_ALGO_PANHS;
  527. } else {
  528. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  529. DBG_LOUD,
  530. "PAN(EDR) only\n");
  531. algorithm =
  532. BT_8192E_2ANT_COEX_ALGO_PANEDR;
  533. }
  534. }
  535. }
  536. } else if (num_of_diff_profile == 2) {
  537. if (bt_link_info->sco_exist) {
  538. if (bt_link_info->hid_exist) {
  539. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  540. "SCO + HID\n");
  541. algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
  542. } else if (bt_link_info->a2dp_exist) {
  543. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  544. "SCO + A2DP ==> SCO\n");
  545. algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
  546. } else if (bt_link_info->pan_exist) {
  547. if (bt_hs_on) {
  548. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  549. DBG_LOUD,
  550. "SCO + PAN(HS)\n");
  551. algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
  552. } else {
  553. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  554. DBG_LOUD,
  555. "SCO + PAN(EDR)\n");
  556. algorithm =
  557. BT_8192E_2ANT_COEX_ALGO_SCO_PAN;
  558. }
  559. }
  560. } else {
  561. if (bt_link_info->hid_exist &&
  562. bt_link_info->a2dp_exist) {
  563. if (stack_info->num_of_hid >= 2) {
  564. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  565. DBG_LOUD,
  566. "HID*2 + A2DP\n");
  567. algorithm =
  568. BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
  569. } else {
  570. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  571. DBG_LOUD,
  572. "HID + A2DP\n");
  573. algorithm =
  574. BT_8192E_2ANT_COEX_ALGO_HID_A2DP;
  575. }
  576. } else if (bt_link_info->hid_exist &&
  577. bt_link_info->pan_exist) {
  578. if (bt_hs_on) {
  579. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  580. DBG_LOUD,
  581. "HID + PAN(HS)\n");
  582. algorithm = BT_8192E_2ANT_COEX_ALGO_HID;
  583. } else {
  584. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  585. DBG_LOUD,
  586. "HID + PAN(EDR)\n");
  587. algorithm =
  588. BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
  589. }
  590. } else if (bt_link_info->pan_exist &&
  591. bt_link_info->a2dp_exist) {
  592. if (bt_hs_on) {
  593. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  594. DBG_LOUD,
  595. "A2DP + PAN(HS)\n");
  596. algorithm =
  597. BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS;
  598. } else {
  599. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  600. DBG_LOUD,
  601. "A2DP + PAN(EDR)\n");
  602. algorithm =
  603. BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP;
  604. }
  605. }
  606. }
  607. } else if (num_of_diff_profile == 3) {
  608. if (bt_link_info->sco_exist) {
  609. if (bt_link_info->hid_exist &&
  610. bt_link_info->a2dp_exist) {
  611. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  612. "SCO + HID + A2DP ==> HID\n");
  613. algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
  614. } else if (bt_link_info->hid_exist &&
  615. bt_link_info->pan_exist) {
  616. if (bt_hs_on) {
  617. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  618. DBG_LOUD,
  619. "SCO + HID + PAN(HS)\n");
  620. algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
  621. } else {
  622. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  623. DBG_LOUD,
  624. "SCO + HID + PAN(EDR)\n");
  625. algorithm =
  626. BT_8192E_2ANT_COEX_ALGO_SCO_PAN;
  627. }
  628. } else if (bt_link_info->pan_exist &&
  629. bt_link_info->a2dp_exist) {
  630. if (bt_hs_on) {
  631. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  632. DBG_LOUD,
  633. "SCO + A2DP + PAN(HS)\n");
  634. algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
  635. } else {
  636. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  637. DBG_LOUD,
  638. "SCO + A2DP + PAN(EDR)\n");
  639. algorithm =
  640. BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
  641. }
  642. }
  643. } else {
  644. if (bt_link_info->hid_exist &&
  645. bt_link_info->pan_exist &&
  646. bt_link_info->a2dp_exist) {
  647. if (bt_hs_on) {
  648. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  649. DBG_LOUD,
  650. "HID + A2DP + PAN(HS)\n");
  651. algorithm =
  652. BT_8192E_2ANT_COEX_ALGO_HID_A2DP;
  653. } else {
  654. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  655. DBG_LOUD,
  656. "HID + A2DP + PAN(EDR)\n");
  657. algorithm =
  658. BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
  659. }
  660. }
  661. }
  662. } else if (num_of_diff_profile >= 3) {
  663. if (bt_link_info->sco_exist) {
  664. if (bt_link_info->hid_exist &&
  665. bt_link_info->pan_exist &&
  666. bt_link_info->a2dp_exist) {
  667. if (bt_hs_on) {
  668. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  669. DBG_LOUD,
  670. "ErrorSCO+HID+A2DP+PAN(HS)\n");
  671. } else {
  672. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  673. DBG_LOUD,
  674. "SCO+HID+A2DP+PAN(EDR)\n");
  675. algorithm =
  676. BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
  677. }
  678. }
  679. }
  680. }
  681. return algorithm;
  682. }
  683. static void btc8192e2ant_set_fw_dac_swing_level(struct btc_coexist *btcoexist,
  684. u8 dac_swing_lvl)
  685. {
  686. struct rtl_priv *rtlpriv = btcoexist->adapter;
  687. u8 h2c_parameter[1] = {0};
  688. /* There are several type of dacswing
  689. * 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6
  690. */
  691. h2c_parameter[0] = dac_swing_lvl;
  692. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  693. "[BTCoex], Set Dac Swing Level = 0x%x\n", dac_swing_lvl);
  694. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  695. "[BTCoex], FW write 0x64 = 0x%x\n", h2c_parameter[0]);
  696. btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter);
  697. }
  698. static void btc8192e2ant_set_fw_dec_bt_pwr(struct btc_coexist *btcoexist,
  699. u8 dec_bt_pwr_lvl)
  700. {
  701. struct rtl_priv *rtlpriv = btcoexist->adapter;
  702. u8 h2c_parameter[1] = {0};
  703. h2c_parameter[0] = dec_bt_pwr_lvl;
  704. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  705. "[BTCoex] decrease Bt Power level = %d, FW write 0x62 = 0x%x\n",
  706. dec_bt_pwr_lvl, h2c_parameter[0]);
  707. btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter);
  708. }
  709. static void btc8192e2ant_dec_bt_pwr(struct btc_coexist *btcoexist,
  710. bool force_exec, u8 dec_bt_pwr_lvl)
  711. {
  712. struct rtl_priv *rtlpriv = btcoexist->adapter;
  713. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  714. "[BTCoex], %s Dec BT power level = %d\n",
  715. force_exec ? "force to" : "", dec_bt_pwr_lvl);
  716. coex_dm->cur_dec_bt_pwr = dec_bt_pwr_lvl;
  717. if (!force_exec) {
  718. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  719. "[BTCoex], preBtDecPwrLvl=%d, curBtDecPwrLvl=%d\n",
  720. coex_dm->pre_dec_bt_pwr, coex_dm->cur_dec_bt_pwr);
  721. }
  722. btc8192e2ant_set_fw_dec_bt_pwr(btcoexist, coex_dm->cur_dec_bt_pwr);
  723. coex_dm->pre_dec_bt_pwr = coex_dm->cur_dec_bt_pwr;
  724. }
  725. static void btc8192e2ant_set_bt_auto_report(struct btc_coexist *btcoexist,
  726. bool enable_auto_report)
  727. {
  728. struct rtl_priv *rtlpriv = btcoexist->adapter;
  729. u8 h2c_parameter[1] = {0};
  730. h2c_parameter[0] = 0;
  731. if (enable_auto_report)
  732. h2c_parameter[0] |= BIT0;
  733. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  734. "[BTCoex], BT FW auto report : %s, FW write 0x68 = 0x%x\n",
  735. (enable_auto_report ? "Enabled!!" : "Disabled!!"),
  736. h2c_parameter[0]);
  737. btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
  738. }
  739. static void btc8192e2ant_bt_auto_report(struct btc_coexist *btcoexist,
  740. bool force_exec,
  741. bool enable_auto_report)
  742. {
  743. struct rtl_priv *rtlpriv = btcoexist->adapter;
  744. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  745. "[BTCoex], %s BT Auto report = %s\n",
  746. (force_exec ? "force to" : ""),
  747. ((enable_auto_report) ? "Enabled" : "Disabled"));
  748. coex_dm->cur_bt_auto_report = enable_auto_report;
  749. if (!force_exec) {
  750. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  751. "[BTCoex] bPreBtAutoReport=%d, bCurBtAutoReport=%d\n",
  752. coex_dm->pre_bt_auto_report,
  753. coex_dm->cur_bt_auto_report);
  754. if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
  755. return;
  756. }
  757. btc8192e2ant_set_bt_auto_report(btcoexist,
  758. coex_dm->cur_bt_auto_report);
  759. coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
  760. }
  761. static void btc8192e2ant_fw_dac_swing_lvl(struct btc_coexist *btcoexist,
  762. bool force_exec, u8 fw_dac_swing_lvl)
  763. {
  764. struct rtl_priv *rtlpriv = btcoexist->adapter;
  765. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  766. "[BTCoex], %s set FW Dac Swing level = %d\n",
  767. (force_exec ? "force to" : ""), fw_dac_swing_lvl);
  768. coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl;
  769. if (!force_exec) {
  770. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  771. "[BTCoex] preFwDacSwingLvl=%d, curFwDacSwingLvl=%d\n",
  772. coex_dm->pre_fw_dac_swing_lvl,
  773. coex_dm->cur_fw_dac_swing_lvl);
  774. if (coex_dm->pre_fw_dac_swing_lvl ==
  775. coex_dm->cur_fw_dac_swing_lvl)
  776. return;
  777. }
  778. btc8192e2ant_set_fw_dac_swing_level(btcoexist,
  779. coex_dm->cur_fw_dac_swing_lvl);
  780. coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
  781. }
  782. static void btc8192e2ant_set_sw_rf_rx_lpf_corner(struct btc_coexist *btcoexist,
  783. bool rx_rf_shrink_on)
  784. {
  785. struct rtl_priv *rtlpriv = btcoexist->adapter;
  786. if (rx_rf_shrink_on) {
  787. /* Shrink RF Rx LPF corner */
  788. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  789. "[BTCoex], Shrink RF Rx LPF corner!!\n");
  790. btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
  791. 0xfffff, 0xffffc);
  792. } else {
  793. /* Resume RF Rx LPF corner
  794. * After initialized, we can use coex_dm->btRf0x1eBackup
  795. */
  796. if (btcoexist->initilized) {
  797. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  798. "[BTCoex], Resume RF Rx LPF corner!!\n");
  799. btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
  800. 0xfffff,
  801. coex_dm->bt_rf0x1e_backup);
  802. }
  803. }
  804. }
  805. static void btc8192e2ant_rf_shrink(struct btc_coexist *btcoexist,
  806. bool force_exec, bool rx_rf_shrink_on)
  807. {
  808. struct rtl_priv *rtlpriv = btcoexist->adapter;
  809. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  810. "[BTCoex], %s turn Rx RF Shrink = %s\n",
  811. (force_exec ? "force to" : ""),
  812. ((rx_rf_shrink_on) ? "ON" : "OFF"));
  813. coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on;
  814. if (!force_exec) {
  815. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  816. "[BTCoex]bPreRfRxLpfShrink=%d,bCurRfRxLpfShrink=%d\n",
  817. coex_dm->pre_rf_rx_lpf_shrink,
  818. coex_dm->cur_rf_rx_lpf_shrink);
  819. if (coex_dm->pre_rf_rx_lpf_shrink ==
  820. coex_dm->cur_rf_rx_lpf_shrink)
  821. return;
  822. }
  823. btc8192e2ant_set_sw_rf_rx_lpf_corner(btcoexist,
  824. coex_dm->cur_rf_rx_lpf_shrink);
  825. coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink;
  826. }
  827. static void btc8192e2ant_set_dac_swing_reg(struct btc_coexist *btcoexist,
  828. u32 level)
  829. {
  830. struct rtl_priv *rtlpriv = btcoexist->adapter;
  831. u8 val = (u8)level;
  832. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  833. "[BTCoex], Write SwDacSwing = 0x%x\n", level);
  834. btcoexist->btc_write_1byte_bitmask(btcoexist, 0x883, 0x3e, val);
  835. }
  836. static void btc8192e2ant_set_sw_full_swing(struct btc_coexist *btcoexist,
  837. bool sw_dac_swing_on,
  838. u32 sw_dac_swing_lvl)
  839. {
  840. if (sw_dac_swing_on)
  841. btc8192e2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl);
  842. else
  843. btc8192e2ant_set_dac_swing_reg(btcoexist, 0x18);
  844. }
  845. static void btc8192e2ant_dac_swing(struct btc_coexist *btcoexist,
  846. bool force_exec, bool dac_swing_on,
  847. u32 dac_swing_lvl)
  848. {
  849. struct rtl_priv *rtlpriv = btcoexist->adapter;
  850. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  851. "[BTCoex], %s turn DacSwing=%s, dac_swing_lvl = 0x%x\n",
  852. (force_exec ? "force to" : ""),
  853. ((dac_swing_on) ? "ON" : "OFF"), dac_swing_lvl);
  854. coex_dm->cur_dac_swing_on = dac_swing_on;
  855. coex_dm->cur_dac_swing_lvl = dac_swing_lvl;
  856. if (!force_exec) {
  857. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  858. "[BTCoex], bPreDacSwingOn=%d, preDacSwingLvl = 0x%x, ",
  859. coex_dm->pre_dac_swing_on,
  860. coex_dm->pre_dac_swing_lvl);
  861. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  862. "bCurDacSwingOn=%d, curDacSwingLvl = 0x%x\n",
  863. coex_dm->cur_dac_swing_on,
  864. coex_dm->cur_dac_swing_lvl);
  865. if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) &&
  866. (coex_dm->pre_dac_swing_lvl == coex_dm->cur_dac_swing_lvl))
  867. return;
  868. }
  869. mdelay(30);
  870. btc8192e2ant_set_sw_full_swing(btcoexist, dac_swing_on, dac_swing_lvl);
  871. coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on;
  872. coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl;
  873. }
  874. static void btc8192e2ant_set_agc_table(struct btc_coexist *btcoexist,
  875. bool agc_table_en)
  876. {
  877. struct rtl_priv *rtlpriv = btcoexist->adapter;
  878. /* BB AGC Gain Table */
  879. if (agc_table_en) {
  880. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  881. "[BTCoex], BB Agc Table On!\n");
  882. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x0a1A0001);
  883. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x091B0001);
  884. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x081C0001);
  885. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x071D0001);
  886. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x061E0001);
  887. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x051F0001);
  888. } else {
  889. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  890. "[BTCoex], BB Agc Table Off!\n");
  891. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001);
  892. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001);
  893. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001);
  894. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001);
  895. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001);
  896. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001);
  897. }
  898. }
  899. static void btc8192e2ant_agc_table(struct btc_coexist *btcoexist,
  900. bool force_exec, bool agc_table_en)
  901. {
  902. struct rtl_priv *rtlpriv = btcoexist->adapter;
  903. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  904. "[BTCoex], %s %s Agc Table\n",
  905. (force_exec ? "force to" : ""),
  906. ((agc_table_en) ? "Enable" : "Disable"));
  907. coex_dm->cur_agc_table_en = agc_table_en;
  908. if (!force_exec) {
  909. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  910. "[BTCoex], bPreAgcTableEn=%d, bCurAgcTableEn=%d\n",
  911. coex_dm->pre_agc_table_en,
  912. coex_dm->cur_agc_table_en);
  913. if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en)
  914. return;
  915. }
  916. btc8192e2ant_set_agc_table(btcoexist, agc_table_en);
  917. coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en;
  918. }
  919. static void btc8192e2ant_set_coex_table(struct btc_coexist *btcoexist,
  920. u32 val0x6c0, u32 val0x6c4,
  921. u32 val0x6c8, u8 val0x6cc)
  922. {
  923. struct rtl_priv *rtlpriv = btcoexist->adapter;
  924. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  925. "[BTCoex], set coex table, set 0x6c0 = 0x%x\n", val0x6c0);
  926. btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
  927. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  928. "[BTCoex], set coex table, set 0x6c4 = 0x%x\n", val0x6c4);
  929. btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
  930. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  931. "[BTCoex], set coex table, set 0x6c8 = 0x%x\n", val0x6c8);
  932. btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
  933. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  934. "[BTCoex], set coex table, set 0x6cc = 0x%x\n", val0x6cc);
  935. btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
  936. }
  937. static void btc8192e2ant_coex_table(struct btc_coexist *btcoexist,
  938. bool force_exec, u32 val0x6c0, u32 val0x6c4,
  939. u32 val0x6c8, u8 val0x6cc)
  940. {
  941. struct rtl_priv *rtlpriv = btcoexist->adapter;
  942. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  943. "[BTCoex], %s write Coex Table 0x6c0 = 0x%x, ",
  944. (force_exec ? "force to" : ""), val0x6c0);
  945. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  946. "0x6c4 = 0x%x, 0x6c8 = 0x%x, 0x6cc = 0x%x\n",
  947. val0x6c4, val0x6c8, val0x6cc);
  948. coex_dm->cur_val0x6c0 = val0x6c0;
  949. coex_dm->cur_val0x6c4 = val0x6c4;
  950. coex_dm->cur_val0x6c8 = val0x6c8;
  951. coex_dm->cur_val0x6cc = val0x6cc;
  952. if (!force_exec) {
  953. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  954. "[BTCoex], preVal0x6c0 = 0x%x, preVal0x6c4 = 0x%x, ",
  955. coex_dm->pre_val0x6c0, coex_dm->pre_val0x6c4);
  956. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  957. "preVal0x6c8 = 0x%x, preVal0x6cc = 0x%x !!\n",
  958. coex_dm->pre_val0x6c8, coex_dm->pre_val0x6cc);
  959. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  960. "[BTCoex], curVal0x6c0 = 0x%x, curVal0x6c4 = 0x%x\n",
  961. coex_dm->cur_val0x6c0, coex_dm->cur_val0x6c4);
  962. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  963. "curVal0x6c8 = 0x%x, curVal0x6cc = 0x%x !!\n",
  964. coex_dm->cur_val0x6c8, coex_dm->cur_val0x6cc);
  965. if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
  966. (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
  967. (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
  968. (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
  969. return;
  970. }
  971. btc8192e2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
  972. val0x6cc);
  973. coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
  974. coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
  975. coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
  976. coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
  977. }
  978. static void btc8192e2ant_coex_table_with_type(struct btc_coexist *btcoexist,
  979. bool force_exec, u8 type)
  980. {
  981. switch (type) {
  982. case 0:
  983. btc8192e2ant_coex_table(btcoexist, force_exec, 0x55555555,
  984. 0x5a5a5a5a, 0xffffff, 0x3);
  985. break;
  986. case 1:
  987. btc8192e2ant_coex_table(btcoexist, force_exec, 0x5a5a5a5a,
  988. 0x5a5a5a5a, 0xffffff, 0x3);
  989. break;
  990. case 2:
  991. btc8192e2ant_coex_table(btcoexist, force_exec, 0x55555555,
  992. 0x5ffb5ffb, 0xffffff, 0x3);
  993. break;
  994. case 3:
  995. btc8192e2ant_coex_table(btcoexist, force_exec, 0xdfffdfff,
  996. 0x5fdb5fdb, 0xffffff, 0x3);
  997. break;
  998. case 4:
  999. btc8192e2ant_coex_table(btcoexist, force_exec, 0xdfffdfff,
  1000. 0x5ffb5ffb, 0xffffff, 0x3);
  1001. break;
  1002. default:
  1003. break;
  1004. }
  1005. }
  1006. static void btc8192e2ant_set_fw_ignore_wlan_act(struct btc_coexist *btcoexist,
  1007. bool enable)
  1008. {
  1009. struct rtl_priv *rtlpriv = btcoexist->adapter;
  1010. u8 h2c_parameter[1] = {0};
  1011. if (enable)
  1012. h2c_parameter[0] |= BIT0; /* function enable */
  1013. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1014. "[BTCoex]set FW for BT Ignore Wlan_Act, FW write 0x63 = 0x%x\n",
  1015. h2c_parameter[0]);
  1016. btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
  1017. }
  1018. static void btc8192e2ant_ignore_wlan_act(struct btc_coexist *btcoexist,
  1019. bool force_exec, bool enable)
  1020. {
  1021. struct rtl_priv *rtlpriv = btcoexist->adapter;
  1022. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1023. "[BTCoex], %s turn Ignore WlanAct %s\n",
  1024. (force_exec ? "force to" : ""), (enable ? "ON" : "OFF"));
  1025. coex_dm->cur_ignore_wlan_act = enable;
  1026. if (!force_exec) {
  1027. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1028. "[BTCoex], bPreIgnoreWlanAct = %d ",
  1029. coex_dm->pre_ignore_wlan_act);
  1030. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1031. "bCurIgnoreWlanAct = %d!!\n",
  1032. coex_dm->cur_ignore_wlan_act);
  1033. if (coex_dm->pre_ignore_wlan_act ==
  1034. coex_dm->cur_ignore_wlan_act)
  1035. return;
  1036. }
  1037. btc8192e2ant_set_fw_ignore_wlan_act(btcoexist, enable);
  1038. coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
  1039. }
  1040. static void btc8192e2ant_set_fw_ps_tdma(struct btc_coexist *btcoexist, u8 byte1,
  1041. u8 byte2, u8 byte3, u8 byte4, u8 byte5)
  1042. {
  1043. struct rtl_priv *rtlpriv = btcoexist->adapter;
  1044. u8 h2c_parameter[5] = {0};
  1045. h2c_parameter[0] = byte1;
  1046. h2c_parameter[1] = byte2;
  1047. h2c_parameter[2] = byte3;
  1048. h2c_parameter[3] = byte4;
  1049. h2c_parameter[4] = byte5;
  1050. coex_dm->ps_tdma_para[0] = byte1;
  1051. coex_dm->ps_tdma_para[1] = byte2;
  1052. coex_dm->ps_tdma_para[2] = byte3;
  1053. coex_dm->ps_tdma_para[3] = byte4;
  1054. coex_dm->ps_tdma_para[4] = byte5;
  1055. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1056. "[BTCoex], FW write 0x60(5bytes) = 0x%x%08x\n",
  1057. h2c_parameter[0],
  1058. h2c_parameter[1] << 24 | h2c_parameter[2] << 16 |
  1059. h2c_parameter[3] << 8 | h2c_parameter[4]);
  1060. btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
  1061. }
  1062. static void btc8192e2ant_sw_mechanism1(struct btc_coexist *btcoexist,
  1063. bool shrink_rx_lpf, bool low_penalty_ra,
  1064. bool limited_dig, bool btlan_constrain)
  1065. {
  1066. btc8192e2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf);
  1067. }
  1068. static void btc8192e2ant_sw_mechanism2(struct btc_coexist *btcoexist,
  1069. bool agc_table_shift, bool adc_backoff,
  1070. bool sw_dac_swing, u32 dac_swing_lvl)
  1071. {
  1072. btc8192e2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift);
  1073. btc8192e2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing,
  1074. dac_swing_lvl);
  1075. }
  1076. static void btc8192e2ant_ps_tdma(struct btc_coexist *btcoexist,
  1077. bool force_exec, bool turn_on, u8 type)
  1078. {
  1079. struct rtl_priv *rtlpriv = btcoexist->adapter;
  1080. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1081. "[BTCoex], %s turn %s PS TDMA, type=%d\n",
  1082. (force_exec ? "force to" : ""),
  1083. (turn_on ? "ON" : "OFF"), type);
  1084. coex_dm->cur_ps_tdma_on = turn_on;
  1085. coex_dm->cur_ps_tdma = type;
  1086. if (!force_exec) {
  1087. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1088. "[BTCoex], bPrePsTdmaOn = %d, bCurPsTdmaOn = %d!!\n",
  1089. coex_dm->pre_ps_tdma_on, coex_dm->cur_ps_tdma_on);
  1090. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1091. "[BTCoex], prePsTdma = %d, curPsTdma = %d!!\n",
  1092. coex_dm->pre_ps_tdma, coex_dm->cur_ps_tdma);
  1093. if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
  1094. (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
  1095. return;
  1096. }
  1097. if (turn_on) {
  1098. switch (type) {
  1099. case 1:
  1100. default:
  1101. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1a,
  1102. 0x1a, 0xe1, 0x90);
  1103. break;
  1104. case 2:
  1105. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x12,
  1106. 0x12, 0xe1, 0x90);
  1107. break;
  1108. case 3:
  1109. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1c,
  1110. 0x3, 0xf1, 0x90);
  1111. break;
  1112. case 4:
  1113. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x10,
  1114. 0x3, 0xf1, 0x90);
  1115. break;
  1116. case 5:
  1117. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1a,
  1118. 0x1a, 0x60, 0x90);
  1119. break;
  1120. case 6:
  1121. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x12,
  1122. 0x12, 0x60, 0x90);
  1123. break;
  1124. case 7:
  1125. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1c,
  1126. 0x3, 0x70, 0x90);
  1127. break;
  1128. case 8:
  1129. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xa3, 0x10,
  1130. 0x3, 0x70, 0x90);
  1131. break;
  1132. case 9:
  1133. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1a,
  1134. 0x1a, 0xe1, 0x10);
  1135. break;
  1136. case 10:
  1137. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x12,
  1138. 0x12, 0xe1, 0x10);
  1139. break;
  1140. case 11:
  1141. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1c,
  1142. 0x3, 0xf1, 0x10);
  1143. break;
  1144. case 12:
  1145. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x10,
  1146. 0x3, 0xf1, 0x10);
  1147. break;
  1148. case 13:
  1149. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1a,
  1150. 0x1a, 0xe0, 0x10);
  1151. break;
  1152. case 14:
  1153. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x12,
  1154. 0x12, 0xe0, 0x10);
  1155. break;
  1156. case 15:
  1157. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1c,
  1158. 0x3, 0xf0, 0x10);
  1159. break;
  1160. case 16:
  1161. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x12,
  1162. 0x3, 0xf0, 0x10);
  1163. break;
  1164. case 17:
  1165. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0x61, 0x20,
  1166. 0x03, 0x10, 0x10);
  1167. break;
  1168. case 18:
  1169. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x5,
  1170. 0x5, 0xe1, 0x90);
  1171. break;
  1172. case 19:
  1173. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x25,
  1174. 0x25, 0xe1, 0x90);
  1175. break;
  1176. case 20:
  1177. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x25,
  1178. 0x25, 0x60, 0x90);
  1179. break;
  1180. case 21:
  1181. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x15,
  1182. 0x03, 0x70, 0x90);
  1183. break;
  1184. case 71:
  1185. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1a,
  1186. 0x1a, 0xe1, 0x90);
  1187. break;
  1188. }
  1189. } else {
  1190. /* disable PS tdma */
  1191. switch (type) {
  1192. default:
  1193. case 0:
  1194. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0x8, 0x0, 0x0,
  1195. 0x0, 0x0);
  1196. btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4);
  1197. break;
  1198. case 1:
  1199. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0x0, 0x0, 0x0,
  1200. 0x8, 0x0);
  1201. mdelay(5);
  1202. btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20);
  1203. break;
  1204. }
  1205. }
  1206. /* update pre state */
  1207. coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
  1208. coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
  1209. }
  1210. static void btc8192e2ant_set_switch_ss_type(struct btc_coexist *btcoexist,
  1211. u8 ss_type)
  1212. {
  1213. struct rtl_priv *rtlpriv = btcoexist->adapter;
  1214. u8 mimops = BTC_MIMO_PS_DYNAMIC;
  1215. u32 dis_ra_mask = 0x0;
  1216. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1217. "[BTCoex], REAL set SS Type = %d\n", ss_type);
  1218. dis_ra_mask = btc8192e2ant_decide_ra_mask(btcoexist, ss_type,
  1219. coex_dm->cur_ra_mask_type);
  1220. btc8192e2ant_update_ra_mask(btcoexist, FORCE_EXEC, dis_ra_mask);
  1221. if (ss_type == 1) {
  1222. btc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);
  1223. /* switch ofdm path */
  1224. btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x11);
  1225. btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x1);
  1226. btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81111111);
  1227. /* switch cck patch */
  1228. btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x1);
  1229. btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x81);
  1230. mimops = BTC_MIMO_PS_STATIC;
  1231. } else if (ss_type == 2) {
  1232. btc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
  1233. btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x33);
  1234. btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x3);
  1235. btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81121313);
  1236. btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x0);
  1237. btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x41);
  1238. mimops = BTC_MIMO_PS_DYNAMIC;
  1239. }
  1240. /* set rx 1ss or 2ss */
  1241. btcoexist->btc_set(btcoexist, BTC_SET_ACT_SEND_MIMO_PS, &mimops);
  1242. }
  1243. static void btc8192e2ant_switch_ss_type(struct btc_coexist *btcoexist,
  1244. bool force_exec, u8 new_ss_type)
  1245. {
  1246. struct rtl_priv *rtlpriv = btcoexist->adapter;
  1247. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1248. "[BTCoex], %s Switch SS Type = %d\n",
  1249. (force_exec ? "force to" : ""), new_ss_type);
  1250. coex_dm->cur_ss_type = new_ss_type;
  1251. if (!force_exec) {
  1252. if (coex_dm->pre_ss_type == coex_dm->cur_ss_type)
  1253. return;
  1254. }
  1255. btc8192e2ant_set_switch_ss_type(btcoexist, coex_dm->cur_ss_type);
  1256. coex_dm->pre_ss_type = coex_dm->cur_ss_type;
  1257. }
  1258. static void btc8192e2ant_coex_all_off(struct btc_coexist *btcoexist)
  1259. {
  1260. /* fw all off */
  1261. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
  1262. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  1263. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1264. /* sw all off */
  1265. btc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
  1266. btc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
  1267. /* hw all off */
  1268. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
  1269. }
  1270. static void btc8192e2ant_init_coex_dm(struct btc_coexist *btcoexist)
  1271. {
  1272. /* force to reset coex mechanism */
  1273. btc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);
  1274. btc8192e2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6);
  1275. btc8192e2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0);
  1276. btc8192e2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
  1277. btc8192e2ant_switch_ss_type(btcoexist, FORCE_EXEC, 2);
  1278. btc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
  1279. btc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
  1280. }
  1281. static void btc8192e2ant_action_bt_inquiry(struct btc_coexist *btcoexist)
  1282. {
  1283. bool low_pwr_disable = true;
  1284. btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
  1285. &low_pwr_disable);
  1286. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  1287. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
  1288. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
  1289. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  1290. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1291. btc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
  1292. btc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
  1293. }
  1294. static bool btc8192e2ant_is_common_action(struct btc_coexist *btcoexist)
  1295. {
  1296. struct rtl_priv *rtlpriv = btcoexist->adapter;
  1297. struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
  1298. bool common = false, wifi_connected = false, wifi_busy = false;
  1299. bool bt_hs_on = false, low_pwr_disable = false;
  1300. btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
  1301. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
  1302. &wifi_connected);
  1303. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
  1304. if (bt_link_info->sco_exist || bt_link_info->hid_exist)
  1305. btc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 0, 0, 0);
  1306. else
  1307. btc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
  1308. if (!wifi_connected) {
  1309. low_pwr_disable = false;
  1310. btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
  1311. &low_pwr_disable);
  1312. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1313. "[BTCoex], Wifi non-connected idle!!\n");
  1314. if ((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
  1315. coex_dm->bt_status) ||
  1316. (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE ==
  1317. coex_dm->bt_status)) {
  1318. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 2);
  1319. btc8192e2ant_coex_table_with_type(btcoexist,
  1320. NORMAL_EXEC, 1);
  1321. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
  1322. } else {
  1323. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  1324. btc8192e2ant_coex_table_with_type(btcoexist,
  1325. NORMAL_EXEC, 0);
  1326. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
  1327. }
  1328. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  1329. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1330. btc8192e2ant_sw_mechanism1(btcoexist, false, false, false,
  1331. false);
  1332. btc8192e2ant_sw_mechanism2(btcoexist, false, false, false,
  1333. 0x18);
  1334. common = true;
  1335. } else {
  1336. if (BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
  1337. coex_dm->bt_status) {
  1338. low_pwr_disable = false;
  1339. btcoexist->btc_set(btcoexist,
  1340. BTC_SET_ACT_DISABLE_LOW_POWER,
  1341. &low_pwr_disable);
  1342. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1343. "Wifi connected + BT non connected-idle!!\n");
  1344. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 2);
  1345. btc8192e2ant_coex_table_with_type(btcoexist,
  1346. NORMAL_EXEC, 1);
  1347. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
  1348. btc8192e2ant_fw_dac_swing_lvl(btcoexist,
  1349. NORMAL_EXEC, 6);
  1350. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1351. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  1352. false, false);
  1353. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1354. false, 0x18);
  1355. common = true;
  1356. } else if (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE ==
  1357. coex_dm->bt_status) {
  1358. low_pwr_disable = true;
  1359. btcoexist->btc_set(btcoexist,
  1360. BTC_SET_ACT_DISABLE_LOW_POWER,
  1361. &low_pwr_disable);
  1362. if (bt_hs_on)
  1363. return false;
  1364. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1365. "Wifi connected + BT connected-idle!!\n");
  1366. btc8192e2ant_switch_ss_type(btcoexist,
  1367. NORMAL_EXEC, 2);
  1368. btc8192e2ant_coex_table_with_type(btcoexist,
  1369. NORMAL_EXEC, 1);
  1370. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1371. false, 0);
  1372. btc8192e2ant_fw_dac_swing_lvl(btcoexist,
  1373. NORMAL_EXEC, 6);
  1374. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1375. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  1376. false, false);
  1377. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1378. false, 0x18);
  1379. common = true;
  1380. } else {
  1381. low_pwr_disable = true;
  1382. btcoexist->btc_set(btcoexist,
  1383. BTC_SET_ACT_DISABLE_LOW_POWER,
  1384. &low_pwr_disable);
  1385. if (wifi_busy) {
  1386. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1387. "Wifi Connected-Busy + BT Busy!!\n");
  1388. common = false;
  1389. } else {
  1390. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1391. "Wifi Connected-Idle + BT Busy!!\n");
  1392. btc8192e2ant_switch_ss_type(btcoexist,
  1393. NORMAL_EXEC, 1);
  1394. btc8192e2ant_coex_table_with_type(btcoexist,
  1395. NORMAL_EXEC,
  1396. 2);
  1397. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1398. true, 21);
  1399. btc8192e2ant_fw_dac_swing_lvl(btcoexist,
  1400. NORMAL_EXEC, 6);
  1401. btc8192e2ant_dec_bt_pwr(btcoexist,
  1402. NORMAL_EXEC, 0);
  1403. btc8192e2ant_sw_mechanism1(btcoexist, false,
  1404. false, false, false);
  1405. btc8192e2ant_sw_mechanism2(btcoexist, false,
  1406. false, false, 0x18);
  1407. common = true;
  1408. }
  1409. }
  1410. }
  1411. return common;
  1412. }
  1413. static void btc8192e2ant_tdma_duration_adjust(struct btc_coexist *btcoexist,
  1414. bool sco_hid, bool tx_pause,
  1415. u8 max_interval)
  1416. {
  1417. struct rtl_priv *rtlpriv = btcoexist->adapter;
  1418. static int up, dn, m, n, wait_cnt;
  1419. /* 0: no change, +1: increase WiFi duration,
  1420. * -1: decrease WiFi duration
  1421. */
  1422. int result;
  1423. u8 retry_cnt = 0;
  1424. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1425. "[BTCoex], TdmaDurationAdjust()\n");
  1426. if (!coex_dm->auto_tdma_adjust) {
  1427. coex_dm->auto_tdma_adjust = true;
  1428. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1429. "[BTCoex], first run TdmaDurationAdjust()!!\n");
  1430. if (sco_hid) {
  1431. if (tx_pause) {
  1432. if (max_interval == 1) {
  1433. btc8192e2ant_ps_tdma(btcoexist,
  1434. NORMAL_EXEC,
  1435. true, 13);
  1436. coex_dm->tdma_adj_type = 13;
  1437. } else if (max_interval == 2) {
  1438. btc8192e2ant_ps_tdma(btcoexist,
  1439. NORMAL_EXEC,
  1440. true, 14);
  1441. coex_dm->tdma_adj_type = 14;
  1442. } else {
  1443. btc8192e2ant_ps_tdma(btcoexist,
  1444. NORMAL_EXEC,
  1445. true, 15);
  1446. coex_dm->tdma_adj_type = 15;
  1447. }
  1448. } else {
  1449. if (max_interval == 1) {
  1450. btc8192e2ant_ps_tdma(btcoexist,
  1451. NORMAL_EXEC,
  1452. true, 9);
  1453. coex_dm->tdma_adj_type = 9;
  1454. } else if (max_interval == 2) {
  1455. btc8192e2ant_ps_tdma(btcoexist,
  1456. NORMAL_EXEC,
  1457. true, 10);
  1458. coex_dm->tdma_adj_type = 10;
  1459. } else {
  1460. btc8192e2ant_ps_tdma(btcoexist,
  1461. NORMAL_EXEC,
  1462. true, 11);
  1463. coex_dm->tdma_adj_type = 11;
  1464. }
  1465. }
  1466. } else {
  1467. if (tx_pause) {
  1468. if (max_interval == 1) {
  1469. btc8192e2ant_ps_tdma(btcoexist,
  1470. NORMAL_EXEC,
  1471. true, 5);
  1472. coex_dm->tdma_adj_type = 5;
  1473. } else if (max_interval == 2) {
  1474. btc8192e2ant_ps_tdma(btcoexist,
  1475. NORMAL_EXEC,
  1476. true, 6);
  1477. coex_dm->tdma_adj_type = 6;
  1478. } else {
  1479. btc8192e2ant_ps_tdma(btcoexist,
  1480. NORMAL_EXEC,
  1481. true, 7);
  1482. coex_dm->tdma_adj_type = 7;
  1483. }
  1484. } else {
  1485. if (max_interval == 1) {
  1486. btc8192e2ant_ps_tdma(btcoexist,
  1487. NORMAL_EXEC,
  1488. true, 1);
  1489. coex_dm->tdma_adj_type = 1;
  1490. } else if (max_interval == 2) {
  1491. btc8192e2ant_ps_tdma(btcoexist,
  1492. NORMAL_EXEC,
  1493. true, 2);
  1494. coex_dm->tdma_adj_type = 2;
  1495. } else {
  1496. btc8192e2ant_ps_tdma(btcoexist,
  1497. NORMAL_EXEC,
  1498. true, 3);
  1499. coex_dm->tdma_adj_type = 3;
  1500. }
  1501. }
  1502. }
  1503. up = 0;
  1504. dn = 0;
  1505. m = 1;
  1506. n = 3;
  1507. result = 0;
  1508. wait_cnt = 0;
  1509. } else {
  1510. /* accquire the BT TRx retry count from BT_Info byte2 */
  1511. retry_cnt = coex_sta->bt_retry_cnt;
  1512. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1513. "[BTCoex], retry_cnt = %d\n", retry_cnt);
  1514. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1515. "[BTCoex], up=%d, dn=%d, m=%d, n=%d, wait_cnt=%d\n",
  1516. up, dn, m, n, wait_cnt);
  1517. result = 0;
  1518. wait_cnt++;
  1519. /* no retry in the last 2-second duration */
  1520. if (retry_cnt == 0) {
  1521. up++;
  1522. dn--;
  1523. if (dn <= 0)
  1524. dn = 0;
  1525. if (up >= n) {
  1526. wait_cnt = 0;
  1527. n = 3;
  1528. up = 0;
  1529. dn = 0;
  1530. result = 1;
  1531. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1532. "[BTCoex]Increase wifi duration!!\n");
  1533. }
  1534. } else if (retry_cnt <= 3) {
  1535. up--;
  1536. dn++;
  1537. if (up <= 0)
  1538. up = 0;
  1539. if (dn == 2) {
  1540. if (wait_cnt <= 2)
  1541. m++;
  1542. else
  1543. m = 1;
  1544. if (m >= 20)
  1545. m = 20;
  1546. n = 3 * m;
  1547. up = 0;
  1548. dn = 0;
  1549. wait_cnt = 0;
  1550. result = -1;
  1551. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1552. "Reduce wifi duration for retry<3\n");
  1553. }
  1554. } else {
  1555. if (wait_cnt == 1)
  1556. m++;
  1557. else
  1558. m = 1;
  1559. if (m >= 20)
  1560. m = 20;
  1561. n = 3*m;
  1562. up = 0;
  1563. dn = 0;
  1564. wait_cnt = 0;
  1565. result = -1;
  1566. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1567. "Decrease wifi duration for retryCounter>3!!\n");
  1568. }
  1569. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1570. "[BTCoex], max Interval = %d\n", max_interval);
  1571. }
  1572. /* if current PsTdma not match with
  1573. * the recorded one (when scan, dhcp...),
  1574. * then we have to adjust it back to the previous record one.
  1575. */
  1576. if (coex_dm->cur_ps_tdma != coex_dm->tdma_adj_type) {
  1577. bool scan = false, link = false, roam = false;
  1578. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1579. "[BTCoex], PsTdma type mismatch!!!, ");
  1580. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1581. "curPsTdma=%d, recordPsTdma=%d\n",
  1582. coex_dm->cur_ps_tdma, coex_dm->tdma_adj_type);
  1583. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
  1584. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
  1585. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
  1586. if (!scan && !link && !roam)
  1587. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1588. true, coex_dm->tdma_adj_type);
  1589. else
  1590. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1591. "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n");
  1592. }
  1593. }
  1594. /* SCO only or SCO+PAN(HS) */
  1595. static void btc8192e2ant_action_sco(struct btc_coexist *btcoexist)
  1596. {
  1597. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
  1598. u32 wifi_bw;
  1599. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  1600. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  1601. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  1602. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  1603. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
  1604. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  1605. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  1606. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  1607. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1608. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
  1609. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  1610. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  1611. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  1612. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
  1613. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1614. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1615. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  1616. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
  1617. }
  1618. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  1619. /* sw mechanism */
  1620. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  1621. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1622. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1623. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  1624. false, false);
  1625. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1626. false, 0x6);
  1627. } else {
  1628. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  1629. false, false);
  1630. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1631. false, 0x6);
  1632. }
  1633. } else {
  1634. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1635. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1636. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  1637. false, false);
  1638. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1639. false, 0x6);
  1640. } else {
  1641. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  1642. false, false);
  1643. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1644. false, 0x6);
  1645. }
  1646. }
  1647. }
  1648. static void btc8192e2ant_action_sco_pan(struct btc_coexist *btcoexist)
  1649. {
  1650. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
  1651. u32 wifi_bw;
  1652. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  1653. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  1654. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  1655. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  1656. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
  1657. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  1658. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  1659. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  1660. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1661. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
  1662. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  1663. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  1664. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  1665. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
  1666. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1667. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1668. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  1669. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
  1670. }
  1671. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  1672. /* sw mechanism */
  1673. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  1674. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1675. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1676. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  1677. false, false);
  1678. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1679. false, 0x6);
  1680. } else {
  1681. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  1682. false, false);
  1683. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1684. false, 0x6);
  1685. }
  1686. } else {
  1687. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1688. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1689. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  1690. false, false);
  1691. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1692. false, 0x6);
  1693. } else {
  1694. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  1695. false, false);
  1696. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1697. false, 0x6);
  1698. }
  1699. }
  1700. }
  1701. static void btc8192e2ant_action_hid(struct btc_coexist *btcoexist)
  1702. {
  1703. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
  1704. u32 wifi_bw;
  1705. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  1706. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  1707. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  1708. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  1709. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  1710. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  1711. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
  1712. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  1713. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  1714. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1715. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
  1716. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  1717. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  1718. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  1719. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
  1720. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1721. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1722. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  1723. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
  1724. }
  1725. /* sw mechanism */
  1726. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  1727. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1728. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1729. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  1730. false, false);
  1731. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1732. false, 0x18);
  1733. } else {
  1734. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  1735. false, false);
  1736. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1737. false, 0x18);
  1738. }
  1739. } else {
  1740. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1741. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1742. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  1743. false, false);
  1744. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1745. false, 0x18);
  1746. } else {
  1747. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  1748. false, false);
  1749. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1750. false, 0x18);
  1751. }
  1752. }
  1753. }
  1754. /* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
  1755. static void btc8192e2ant_action_a2dp(struct btc_coexist *btcoexist)
  1756. {
  1757. struct rtl_priv *rtlpriv = btcoexist->adapter;
  1758. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
  1759. u32 wifi_bw;
  1760. bool long_dist = false;
  1761. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  1762. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  1763. if ((bt_rssi_state == BTC_RSSI_STATE_LOW ||
  1764. bt_rssi_state == BTC_RSSI_STATE_STAY_LOW) &&
  1765. (wifi_rssi_state == BTC_RSSI_STATE_LOW ||
  1766. wifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  1767. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1768. "[BTCoex], A2dp, wifi/bt rssi both LOW!!\n");
  1769. long_dist = true;
  1770. }
  1771. if (long_dist) {
  1772. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 2);
  1773. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true,
  1774. 0x4);
  1775. } else {
  1776. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  1777. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
  1778. 0x8);
  1779. }
  1780. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  1781. if (long_dist)
  1782. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
  1783. else
  1784. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
  1785. if (long_dist) {
  1786. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 17);
  1787. coex_dm->auto_tdma_adjust = false;
  1788. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1789. } else {
  1790. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  1791. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  1792. btc8192e2ant_tdma_duration_adjust(btcoexist, false,
  1793. true, 1);
  1794. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1795. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  1796. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  1797. btc8192e2ant_tdma_duration_adjust(btcoexist, false,
  1798. false, 1);
  1799. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  1800. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1801. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1802. btc8192e2ant_tdma_duration_adjust(btcoexist, false,
  1803. false, 1);
  1804. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  1805. }
  1806. }
  1807. /* sw mechanism */
  1808. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  1809. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  1810. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1811. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1812. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  1813. false, false);
  1814. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1815. false, 0x18);
  1816. } else {
  1817. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  1818. false, false);
  1819. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1820. false, 0x18);
  1821. }
  1822. } else {
  1823. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1824. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1825. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  1826. false, false);
  1827. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1828. false, 0x18);
  1829. } else {
  1830. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  1831. false, false);
  1832. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1833. false, 0x18);
  1834. }
  1835. }
  1836. }
  1837. static void btc8192e2ant_action_a2dp_pan_hs(struct btc_coexist *btcoexist)
  1838. {
  1839. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
  1840. u32 wifi_bw;
  1841. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  1842. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  1843. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  1844. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  1845. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  1846. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
  1847. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  1848. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  1849. btc8192e2ant_tdma_duration_adjust(btcoexist, false, true, 2);
  1850. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1851. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  1852. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  1853. btc8192e2ant_tdma_duration_adjust(btcoexist, false, false, 2);
  1854. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  1855. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1856. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1857. btc8192e2ant_tdma_duration_adjust(btcoexist, false, false, 2);
  1858. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  1859. }
  1860. /* sw mechanism */
  1861. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  1862. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  1863. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1864. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1865. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  1866. false, false);
  1867. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1868. true, 0x6);
  1869. } else {
  1870. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  1871. false, false);
  1872. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1873. true, 0x6);
  1874. }
  1875. } else {
  1876. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1877. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1878. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  1879. false, false);
  1880. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1881. true, 0x6);
  1882. } else {
  1883. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  1884. false, false);
  1885. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1886. true, 0x6);
  1887. }
  1888. }
  1889. }
  1890. static void btc8192e2ant_action_pan_edr(struct btc_coexist *btcoexist)
  1891. {
  1892. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
  1893. u32 wifi_bw;
  1894. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  1895. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  1896. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  1897. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  1898. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  1899. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
  1900. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  1901. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  1902. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1903. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
  1904. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  1905. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  1906. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  1907. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
  1908. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1909. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1910. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  1911. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
  1912. }
  1913. /* sw mechanism */
  1914. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  1915. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  1916. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1917. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1918. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  1919. false, false);
  1920. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1921. false, 0x18);
  1922. } else {
  1923. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  1924. false, false);
  1925. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1926. false, 0x18);
  1927. }
  1928. } else {
  1929. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1930. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1931. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  1932. false, false);
  1933. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1934. false, 0x18);
  1935. } else {
  1936. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  1937. false, false);
  1938. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1939. false, 0x18);
  1940. }
  1941. }
  1942. }
  1943. /* PAN(HS) only */
  1944. static void btc8192e2ant_action_pan_hs(struct btc_coexist *btcoexist)
  1945. {
  1946. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
  1947. u32 wifi_bw;
  1948. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  1949. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  1950. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  1951. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  1952. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  1953. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
  1954. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  1955. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  1956. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1957. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  1958. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  1959. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  1960. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1961. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1962. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  1963. }
  1964. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
  1965. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  1966. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  1967. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1968. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1969. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  1970. false, false);
  1971. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1972. false, 0x18);
  1973. } else {
  1974. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  1975. false, false);
  1976. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1977. false, 0x18);
  1978. }
  1979. } else {
  1980. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1981. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1982. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  1983. false, false);
  1984. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1985. false, 0x18);
  1986. } else {
  1987. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  1988. false, false);
  1989. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1990. false, 0x18);
  1991. }
  1992. }
  1993. }
  1994. /* PAN(EDR)+A2DP */
  1995. static void btc8192e2ant_action_pan_edr_a2dp(struct btc_coexist *btcoexist)
  1996. {
  1997. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
  1998. u32 wifi_bw;
  1999. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  2000. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  2001. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  2002. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  2003. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  2004. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
  2005. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2006. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  2007. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  2008. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  2009. btc8192e2ant_tdma_duration_adjust(btcoexist, false, true, 3);
  2010. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  2011. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  2012. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  2013. btc8192e2ant_tdma_duration_adjust(btcoexist, false, false, 3);
  2014. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2015. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2016. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  2017. btc8192e2ant_tdma_duration_adjust(btcoexist, false, false, 3);
  2018. }
  2019. /* sw mechanism */
  2020. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  2021. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2022. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2023. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  2024. false, false);
  2025. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  2026. false, 0x18);
  2027. } else {
  2028. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  2029. false, false);
  2030. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  2031. false, 0x18);
  2032. }
  2033. } else {
  2034. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2035. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2036. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  2037. false, false);
  2038. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  2039. false, 0x18);
  2040. } else {
  2041. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  2042. false, false);
  2043. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  2044. false, 0x18);
  2045. }
  2046. }
  2047. }
  2048. static void btc8192e2ant_action_pan_edr_hid(struct btc_coexist *btcoexist)
  2049. {
  2050. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
  2051. u32 wifi_bw;
  2052. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  2053. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  2054. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2055. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  2056. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  2057. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  2058. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
  2059. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  2060. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  2061. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  2062. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
  2063. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  2064. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  2065. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  2066. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
  2067. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2068. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2069. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  2070. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  2071. true, 10);
  2072. }
  2073. /* sw mechanism */
  2074. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  2075. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2076. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2077. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  2078. false, false);
  2079. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  2080. false, 0x18);
  2081. } else {
  2082. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  2083. false, false);
  2084. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  2085. false, 0x18);
  2086. }
  2087. } else {
  2088. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2089. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2090. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  2091. false, false);
  2092. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  2093. false, 0x18);
  2094. } else {
  2095. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  2096. false, false);
  2097. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  2098. false, 0x18);
  2099. }
  2100. }
  2101. }
  2102. /* HID+A2DP+PAN(EDR) */
  2103. static void btc8192e2ant_action_hid_a2dp_pan_edr(struct btc_coexist *btcoexist)
  2104. {
  2105. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
  2106. u32 wifi_bw;
  2107. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  2108. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  2109. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  2110. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  2111. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  2112. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2113. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
  2114. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  2115. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  2116. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  2117. btc8192e2ant_tdma_duration_adjust(btcoexist, true, true, 3);
  2118. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  2119. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  2120. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  2121. btc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 3);
  2122. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2123. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2124. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  2125. btc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 3);
  2126. }
  2127. /* sw mechanism */
  2128. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  2129. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2130. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2131. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  2132. false, false);
  2133. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  2134. false, 0x18);
  2135. } else {
  2136. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  2137. false, false);
  2138. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  2139. false, 0x18);
  2140. }
  2141. } else {
  2142. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2143. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2144. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  2145. false, false);
  2146. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  2147. false, 0x18);
  2148. } else {
  2149. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  2150. false, false);
  2151. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  2152. false, 0x18);
  2153. }
  2154. }
  2155. }
  2156. static void btc8192e2ant_action_hid_a2dp(struct btc_coexist *btcoexist)
  2157. {
  2158. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
  2159. u32 wifi_bw;
  2160. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  2161. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  2162. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  2163. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  2164. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2165. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
  2166. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  2167. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  2168. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  2169. btc8192e2ant_tdma_duration_adjust(btcoexist, true, true, 2);
  2170. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  2171. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  2172. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  2173. btc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 2);
  2174. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2175. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2176. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  2177. btc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 2);
  2178. }
  2179. /* sw mechanism */
  2180. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  2181. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2182. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2183. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  2184. false, false);
  2185. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  2186. false, 0x18);
  2187. } else {
  2188. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  2189. false, false);
  2190. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  2191. false, 0x18);
  2192. }
  2193. } else {
  2194. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2195. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2196. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  2197. false, false);
  2198. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  2199. false, 0x18);
  2200. } else {
  2201. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  2202. false, false);
  2203. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  2204. false, 0x18);
  2205. }
  2206. }
  2207. }
  2208. static void btc8192e2ant_run_coexist_mechanism(struct btc_coexist *btcoexist)
  2209. {
  2210. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2211. u8 algorithm = 0;
  2212. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2213. "[BTCoex], RunCoexistMechanism()===>\n");
  2214. if (btcoexist->manual_control) {
  2215. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2216. "[BTCoex], return for Manual CTRL <===\n");
  2217. return;
  2218. }
  2219. if (coex_sta->under_ips) {
  2220. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2221. "[BTCoex], wifi is under IPS !!!\n");
  2222. return;
  2223. }
  2224. algorithm = btc8192e2ant_action_algorithm(btcoexist);
  2225. if (coex_sta->c2h_bt_inquiry_page &&
  2226. (BT_8192E_2ANT_COEX_ALGO_PANHS != algorithm)) {
  2227. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2228. "[BTCoex], BT is under inquiry/page scan !!\n");
  2229. btc8192e2ant_action_bt_inquiry(btcoexist);
  2230. return;
  2231. }
  2232. coex_dm->cur_algorithm = algorithm;
  2233. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2234. "[BTCoex], Algorithm = %d\n", coex_dm->cur_algorithm);
  2235. if (btc8192e2ant_is_common_action(btcoexist)) {
  2236. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2237. "[BTCoex], Action 2-Ant common\n");
  2238. coex_dm->auto_tdma_adjust = false;
  2239. } else {
  2240. if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) {
  2241. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2242. "[BTCoex] preAlgorithm=%d, curAlgorithm=%d\n",
  2243. coex_dm->pre_algorithm,
  2244. coex_dm->cur_algorithm);
  2245. coex_dm->auto_tdma_adjust = false;
  2246. }
  2247. switch (coex_dm->cur_algorithm) {
  2248. case BT_8192E_2ANT_COEX_ALGO_SCO:
  2249. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2250. "Action 2-Ant, algorithm = SCO\n");
  2251. btc8192e2ant_action_sco(btcoexist);
  2252. break;
  2253. case BT_8192E_2ANT_COEX_ALGO_SCO_PAN:
  2254. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2255. "Action 2-Ant, algorithm = SCO+PAN(EDR)\n");
  2256. btc8192e2ant_action_sco_pan(btcoexist);
  2257. break;
  2258. case BT_8192E_2ANT_COEX_ALGO_HID:
  2259. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2260. "Action 2-Ant, algorithm = HID\n");
  2261. btc8192e2ant_action_hid(btcoexist);
  2262. break;
  2263. case BT_8192E_2ANT_COEX_ALGO_A2DP:
  2264. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2265. "Action 2-Ant, algorithm = A2DP\n");
  2266. btc8192e2ant_action_a2dp(btcoexist);
  2267. break;
  2268. case BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS:
  2269. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2270. "Action 2-Ant, algorithm = A2DP+PAN(HS)\n");
  2271. btc8192e2ant_action_a2dp_pan_hs(btcoexist);
  2272. break;
  2273. case BT_8192E_2ANT_COEX_ALGO_PANEDR:
  2274. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2275. "Action 2-Ant, algorithm = PAN(EDR)\n");
  2276. btc8192e2ant_action_pan_edr(btcoexist);
  2277. break;
  2278. case BT_8192E_2ANT_COEX_ALGO_PANHS:
  2279. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2280. "Action 2-Ant, algorithm = HS mode\n");
  2281. btc8192e2ant_action_pan_hs(btcoexist);
  2282. break;
  2283. case BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP:
  2284. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2285. "Action 2-Ant, algorithm = PAN+A2DP\n");
  2286. btc8192e2ant_action_pan_edr_a2dp(btcoexist);
  2287. break;
  2288. case BT_8192E_2ANT_COEX_ALGO_PANEDR_HID:
  2289. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2290. "Action 2-Ant, algorithm = PAN(EDR)+HID\n");
  2291. btc8192e2ant_action_pan_edr_hid(btcoexist);
  2292. break;
  2293. case BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
  2294. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2295. "Action 2-Ant, algorithm = HID+A2DP+PAN\n");
  2296. btc8192e2ant_action_hid_a2dp_pan_edr(btcoexist);
  2297. break;
  2298. case BT_8192E_2ANT_COEX_ALGO_HID_A2DP:
  2299. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2300. "Action 2-Ant, algorithm = HID+A2DP\n");
  2301. btc8192e2ant_action_hid_a2dp(btcoexist);
  2302. break;
  2303. default:
  2304. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2305. "Action 2-Ant, algorithm = unknown!!\n");
  2306. /* btc8192e2ant_coex_all_off(btcoexist); */
  2307. break;
  2308. }
  2309. coex_dm->pre_algorithm = coex_dm->cur_algorithm;
  2310. }
  2311. }
  2312. static void btc8192e2ant_init_hwconfig(struct btc_coexist *btcoexist,
  2313. bool backup)
  2314. {
  2315. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2316. u16 u16tmp = 0;
  2317. u8 u8tmp = 0;
  2318. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2319. "[BTCoex], 2Ant Init HW Config!!\n");
  2320. if (backup) {
  2321. /* backup rf 0x1e value */
  2322. coex_dm->bt_rf0x1e_backup =
  2323. btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A,
  2324. 0x1e, 0xfffff);
  2325. coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
  2326. 0x430);
  2327. coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
  2328. 0x434);
  2329. coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
  2330. btcoexist,
  2331. 0x42a);
  2332. coex_dm->backup_ampdu_maxtime = btcoexist->btc_read_1byte(
  2333. btcoexist,
  2334. 0x456);
  2335. }
  2336. /* antenna sw ctrl to bt */
  2337. btcoexist->btc_write_1byte(btcoexist, 0x4f, 0x6);
  2338. btcoexist->btc_write_1byte(btcoexist, 0x944, 0x24);
  2339. btcoexist->btc_write_4byte(btcoexist, 0x930, 0x700700);
  2340. btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20);
  2341. if (btcoexist->chip_interface == BTC_INTF_USB)
  2342. btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004);
  2343. else
  2344. btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004);
  2345. btc8192e2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
  2346. /* antenna switch control parameter */
  2347. btcoexist->btc_write_4byte(btcoexist, 0x858, 0x55555555);
  2348. /* coex parameters */
  2349. btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3);
  2350. /* 0x790[5:0] = 0x5 */
  2351. u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
  2352. u8tmp &= 0xc0;
  2353. u8tmp |= 0x5;
  2354. btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
  2355. /* enable counter statistics */
  2356. btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
  2357. /* enable PTA */
  2358. btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20);
  2359. /* enable mailbox interface */
  2360. u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x40);
  2361. u16tmp |= BIT9;
  2362. btcoexist->btc_write_2byte(btcoexist, 0x40, u16tmp);
  2363. /* enable PTA I2C mailbox */
  2364. u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x101);
  2365. u8tmp |= BIT4;
  2366. btcoexist->btc_write_1byte(btcoexist, 0x101, u8tmp);
  2367. /* enable bt clock when wifi is disabled. */
  2368. u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x93);
  2369. u8tmp |= BIT0;
  2370. btcoexist->btc_write_1byte(btcoexist, 0x93, u8tmp);
  2371. /* enable bt clock when suspend. */
  2372. u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7);
  2373. u8tmp |= BIT0;
  2374. btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp);
  2375. }
  2376. /************************************************************
  2377. * extern function start with ex_btc8192e2ant_
  2378. ************************************************************/
  2379. void ex_btc8192e2ant_init_hwconfig(struct btc_coexist *btcoexist)
  2380. {
  2381. btc8192e2ant_init_hwconfig(btcoexist, true);
  2382. }
  2383. void ex_btc8192e2ant_init_coex_dm(struct btc_coexist *btcoexist)
  2384. {
  2385. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2386. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2387. "[BTCoex], Coex Mechanism Init!!\n");
  2388. btc8192e2ant_init_coex_dm(btcoexist);
  2389. }
  2390. void ex_btc8192e2ant_display_coex_info(struct btc_coexist *btcoexist,
  2391. struct seq_file *m)
  2392. {
  2393. struct btc_board_info *board_info = &btcoexist->board_info;
  2394. struct btc_stack_info *stack_info = &btcoexist->stack_info;
  2395. u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
  2396. u16 u16tmp[4];
  2397. u32 u32tmp[4];
  2398. bool roam = false, scan = false, link = false, wifi_under_5g = false;
  2399. bool bt_hs_on = false, wifi_busy = false;
  2400. int wifi_rssi = 0, bt_hs_rssi = 0;
  2401. u32 wifi_bw, wifi_traffic_dir;
  2402. u8 wifi_dot11_chnl, wifi_hs_chnl;
  2403. u32 fw_ver = 0, bt_patch_ver = 0;
  2404. seq_puts(m, "\n ============[BT Coexist info]============");
  2405. if (btcoexist->manual_control) {
  2406. seq_puts(m, "\n ===========[Under Manual Control]===========");
  2407. seq_puts(m, "\n ==========================================");
  2408. }
  2409. seq_printf(m, "\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:",
  2410. board_info->pg_ant_num, board_info->btdm_ant_num);
  2411. seq_printf(m, "\n %-35s = %s / %d", "BT stack/ hci ext ver",
  2412. ((stack_info->profile_notified) ? "Yes" : "No"),
  2413. stack_info->hci_version);
  2414. btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
  2415. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
  2416. seq_printf(m, "\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)",
  2417. "CoexVer/ FwVer/ PatchVer",
  2418. glcoex_ver_date_8192e_2ant, glcoex_ver_8192e_2ant,
  2419. fw_ver, bt_patch_ver, bt_patch_ver);
  2420. btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
  2421. btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_DOT11_CHNL,
  2422. &wifi_dot11_chnl);
  2423. btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_HS_CHNL, &wifi_hs_chnl);
  2424. seq_printf(m, "\n %-35s = %d / %d(%d)",
  2425. "Dot11 channel / HsMode(HsChnl)",
  2426. wifi_dot11_chnl, bt_hs_on, wifi_hs_chnl);
  2427. seq_printf(m, "\n %-35s = %3ph ",
  2428. "H2C Wifi inform bt chnl Info", coex_dm->wifi_chnl_info);
  2429. btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
  2430. btcoexist->btc_get(btcoexist, BTC_GET_S4_HS_RSSI, &bt_hs_rssi);
  2431. seq_printf(m, "\n %-35s = %d/ %d",
  2432. "Wifi rssi/ HS rssi", wifi_rssi, bt_hs_rssi);
  2433. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
  2434. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
  2435. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
  2436. seq_printf(m, "\n %-35s = %d/ %d/ %d ",
  2437. "Wifi link/ roam/ scan", link, roam, scan);
  2438. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
  2439. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2440. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
  2441. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION,
  2442. &wifi_traffic_dir);
  2443. seq_printf(m, "\n %-35s = %s / %s/ %s ",
  2444. "Wifi status", (wifi_under_5g ? "5G" : "2.4G"),
  2445. ((BTC_WIFI_BW_LEGACY == wifi_bw) ? "Legacy" :
  2446. (((BTC_WIFI_BW_HT40 == wifi_bw) ? "HT40" : "HT20"))),
  2447. ((!wifi_busy) ? "idle" :
  2448. ((BTC_WIFI_TRAFFIC_TX == wifi_traffic_dir) ?
  2449. "uplink" : "downlink")));
  2450. seq_printf(m, "\n %-35s = [%s/ %d/ %d] ",
  2451. "BT [status/ rssi/ retryCnt]",
  2452. ((btcoexist->bt_info.bt_disabled) ? ("disabled") :
  2453. ((coex_sta->c2h_bt_inquiry_page) ?
  2454. ("inquiry/page scan") :
  2455. ((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
  2456. coex_dm->bt_status) ? "non-connected idle" :
  2457. ((BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE ==
  2458. coex_dm->bt_status) ? "connected-idle" : "busy")))),
  2459. coex_sta->bt_rssi, coex_sta->bt_retry_cnt);
  2460. seq_printf(m, "\n %-35s = %d / %d / %d / %d",
  2461. "SCO/HID/PAN/A2DP", stack_info->sco_exist,
  2462. stack_info->hid_exist, stack_info->pan_exist,
  2463. stack_info->a2dp_exist);
  2464. btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO, m);
  2465. bt_info_ext = coex_sta->bt_info_ext;
  2466. seq_printf(m, "\n %-35s = %s",
  2467. "BT Info A2DP rate",
  2468. (bt_info_ext&BIT0) ? "Basic rate" : "EDR rate");
  2469. for (i = 0; i < BT_INFO_SRC_8192E_2ANT_MAX; i++) {
  2470. if (coex_sta->bt_info_c2h_cnt[i]) {
  2471. seq_printf(m, "\n %-35s = %7ph(%d)",
  2472. glbt_info_src_8192e_2ant[i],
  2473. coex_sta->bt_info_c2h[i],
  2474. coex_sta->bt_info_c2h_cnt[i]);
  2475. }
  2476. }
  2477. seq_printf(m, "\n %-35s = %s/%s",
  2478. "PS state, IPS/LPS",
  2479. ((coex_sta->under_ips ? "IPS ON" : "IPS OFF")),
  2480. ((coex_sta->under_lps ? "LPS ON" : "LPS OFF")));
  2481. btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_FW_PWR_MODE_CMD, m);
  2482. seq_printf(m, "\n %-35s = 0x%x ", "SS Type",
  2483. coex_dm->cur_ss_type);
  2484. /* Sw mechanism */
  2485. seq_printf(m, "\n %-35s",
  2486. "============[Sw mechanism]============");
  2487. seq_printf(m, "\n %-35s = %d/ %d/ %d ",
  2488. "SM1[ShRf/ LpRA/ LimDig]", coex_dm->cur_rf_rx_lpf_shrink,
  2489. coex_dm->cur_low_penalty_ra, coex_dm->limited_dig);
  2490. seq_printf(m, "\n %-35s = %d/ %d/ %d(0x%x) ",
  2491. "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]",
  2492. coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off,
  2493. coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl);
  2494. seq_printf(m, "\n %-35s = 0x%x ", "Rate Mask",
  2495. btcoexist->bt_info.ra_mask);
  2496. /* Fw mechanism */
  2497. seq_printf(m, "\n %-35s",
  2498. "============[Fw mechanism]============");
  2499. ps_tdma_case = coex_dm->cur_ps_tdma;
  2500. seq_printf(m,
  2501. "\n %-35s = %5ph case-%d (auto:%d)",
  2502. "PS TDMA", coex_dm->ps_tdma_para,
  2503. ps_tdma_case, coex_dm->auto_tdma_adjust);
  2504. seq_printf(m, "\n %-35s = %d/ %d ",
  2505. "DecBtPwr/ IgnWlanAct",
  2506. coex_dm->cur_dec_bt_pwr, coex_dm->cur_ignore_wlan_act);
  2507. /* Hw setting */
  2508. seq_printf(m, "\n %-35s",
  2509. "============[Hw setting]============");
  2510. seq_printf(m, "\n %-35s = 0x%x",
  2511. "RF-A, 0x1e initVal", coex_dm->bt_rf0x1e_backup);
  2512. seq_printf(m, "\n %-35s = 0x%x/0x%x/0x%x/0x%x",
  2513. "backup ARFR1/ARFR2/RL/AMaxTime", coex_dm->backup_arfr_cnt1,
  2514. coex_dm->backup_arfr_cnt2, coex_dm->backup_retry_limit,
  2515. coex_dm->backup_ampdu_maxtime);
  2516. u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
  2517. u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
  2518. u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
  2519. u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
  2520. seq_printf(m, "\n %-35s = 0x%x/0x%x/0x%x/0x%x",
  2521. "0x430/0x434/0x42a/0x456",
  2522. u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
  2523. u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc04);
  2524. u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xd04);
  2525. u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x90c);
  2526. seq_printf(m, "\n %-35s = 0x%x/ 0x%x/ 0x%x",
  2527. "0xc04/ 0xd04/ 0x90c", u32tmp[0], u32tmp[1], u32tmp[2]);
  2528. u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
  2529. seq_printf(m, "\n %-35s = 0x%x", "0x778", u8tmp[0]);
  2530. u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x92c);
  2531. u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x930);
  2532. seq_printf(m, "\n %-35s = 0x%x/ 0x%x",
  2533. "0x92c/ 0x930", (u8tmp[0]), u32tmp[0]);
  2534. u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40);
  2535. u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x4f);
  2536. seq_printf(m, "\n %-35s = 0x%x/ 0x%x",
  2537. "0x40/ 0x4f", u8tmp[0], u8tmp[1]);
  2538. u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
  2539. u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
  2540. seq_printf(m, "\n %-35s = 0x%x/ 0x%x",
  2541. "0x550(bcn ctrl)/0x522", u32tmp[0], u8tmp[0]);
  2542. u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
  2543. seq_printf(m, "\n %-35s = 0x%x", "0xc50(dig)",
  2544. u32tmp[0]);
  2545. u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
  2546. u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
  2547. u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
  2548. u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
  2549. seq_printf(m,
  2550. "\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
  2551. "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)",
  2552. u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]);
  2553. seq_printf(m, "\n %-35s = %d/ %d",
  2554. "0x770(hp rx[31:16]/tx[15:0])",
  2555. coex_sta->high_priority_rx, coex_sta->high_priority_tx);
  2556. seq_printf(m, "\n %-35s = %d/ %d",
  2557. "0x774(lp rx[31:16]/tx[15:0])",
  2558. coex_sta->low_priority_rx, coex_sta->low_priority_tx);
  2559. if (btcoexist->auto_report_2ant)
  2560. btc8192e2ant_monitor_bt_ctr(btcoexist);
  2561. btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS, m);
  2562. }
  2563. void ex_btc8192e2ant_ips_notify(struct btc_coexist *btcoexist, u8 type)
  2564. {
  2565. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2566. if (BTC_IPS_ENTER == type) {
  2567. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2568. "[BTCoex], IPS ENTER notify\n");
  2569. coex_sta->under_ips = true;
  2570. btc8192e2ant_coex_all_off(btcoexist);
  2571. } else if (BTC_IPS_LEAVE == type) {
  2572. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2573. "[BTCoex], IPS LEAVE notify\n");
  2574. coex_sta->under_ips = false;
  2575. }
  2576. }
  2577. void ex_btc8192e2ant_lps_notify(struct btc_coexist *btcoexist, u8 type)
  2578. {
  2579. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2580. if (BTC_LPS_ENABLE == type) {
  2581. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2582. "[BTCoex], LPS ENABLE notify\n");
  2583. coex_sta->under_lps = true;
  2584. } else if (BTC_LPS_DISABLE == type) {
  2585. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2586. "[BTCoex], LPS DISABLE notify\n");
  2587. coex_sta->under_lps = false;
  2588. }
  2589. }
  2590. void ex_btc8192e2ant_scan_notify(struct btc_coexist *btcoexist, u8 type)
  2591. {
  2592. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2593. if (BTC_SCAN_START == type)
  2594. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2595. "[BTCoex], SCAN START notify\n");
  2596. else if (BTC_SCAN_FINISH == type)
  2597. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2598. "[BTCoex], SCAN FINISH notify\n");
  2599. }
  2600. void ex_btc8192e2ant_connect_notify(struct btc_coexist *btcoexist, u8 type)
  2601. {
  2602. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2603. if (BTC_ASSOCIATE_START == type)
  2604. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2605. "[BTCoex], CONNECT START notify\n");
  2606. else if (BTC_ASSOCIATE_FINISH == type)
  2607. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2608. "[BTCoex], CONNECT FINISH notify\n");
  2609. }
  2610. void ex_btc8192e2ant_media_status_notify(struct btc_coexist *btcoexist,
  2611. u8 type)
  2612. {
  2613. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2614. u8 h2c_parameter[3] = {0};
  2615. u32 wifi_bw;
  2616. u8 wifi_center_chnl;
  2617. if (btcoexist->manual_control ||
  2618. btcoexist->stop_coex_dm ||
  2619. btcoexist->bt_info.bt_disabled)
  2620. return;
  2621. if (BTC_MEDIA_CONNECT == type)
  2622. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2623. "[BTCoex], MEDIA connect notify\n");
  2624. else
  2625. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2626. "[BTCoex], MEDIA disconnect notify\n");
  2627. /* only 2.4G we need to inform bt the chnl mask */
  2628. btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
  2629. &wifi_center_chnl);
  2630. if ((BTC_MEDIA_CONNECT == type) &&
  2631. (wifi_center_chnl <= 14)) {
  2632. h2c_parameter[0] = 0x1;
  2633. h2c_parameter[1] = wifi_center_chnl;
  2634. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2635. if (BTC_WIFI_BW_HT40 == wifi_bw)
  2636. h2c_parameter[2] = 0x30;
  2637. else
  2638. h2c_parameter[2] = 0x20;
  2639. }
  2640. coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
  2641. coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
  2642. coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
  2643. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2644. "[BTCoex], FW write 0x66 = 0x%x\n",
  2645. h2c_parameter[0] << 16 | h2c_parameter[1] << 8 |
  2646. h2c_parameter[2]);
  2647. btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
  2648. }
  2649. void ex_btc8192e2ant_special_packet_notify(struct btc_coexist *btcoexist,
  2650. u8 type)
  2651. {
  2652. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2653. if (type == BTC_PACKET_DHCP)
  2654. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2655. "[BTCoex], DHCP Packet notify\n");
  2656. }
  2657. void ex_btc8192e2ant_bt_info_notify(struct btc_coexist *btcoexist,
  2658. u8 *tmp_buf, u8 length)
  2659. {
  2660. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2661. u8 bt_info = 0;
  2662. u8 i, rsp_source = 0;
  2663. bool bt_busy = false, limited_dig = false;
  2664. bool wifi_connected = false;
  2665. coex_sta->c2h_bt_info_req_sent = false;
  2666. rsp_source = tmp_buf[0] & 0xf;
  2667. if (rsp_source >= BT_INFO_SRC_8192E_2ANT_MAX)
  2668. rsp_source = BT_INFO_SRC_8192E_2ANT_WIFI_FW;
  2669. coex_sta->bt_info_c2h_cnt[rsp_source]++;
  2670. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2671. "[BTCoex], Bt info[%d], length=%d, hex data = [",
  2672. rsp_source, length);
  2673. for (i = 0; i < length; i++) {
  2674. coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
  2675. if (i == 1)
  2676. bt_info = tmp_buf[i];
  2677. if (i == length-1)
  2678. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2679. "0x%02x]\n", tmp_buf[i]);
  2680. else
  2681. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2682. "0x%02x, ", tmp_buf[i]);
  2683. }
  2684. if (BT_INFO_SRC_8192E_2ANT_WIFI_FW != rsp_source) {
  2685. /* [3:0] */
  2686. coex_sta->bt_retry_cnt =
  2687. coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
  2688. coex_sta->bt_rssi =
  2689. coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
  2690. coex_sta->bt_info_ext =
  2691. coex_sta->bt_info_c2h[rsp_source][4];
  2692. /* Here we need to resend some wifi info to BT
  2693. * because bt is reset and loss of the info.
  2694. */
  2695. if ((coex_sta->bt_info_ext & BIT1)) {
  2696. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2697. "bit1, send wifi BW&Chnl to BT!!\n");
  2698. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
  2699. &wifi_connected);
  2700. if (wifi_connected)
  2701. ex_btc8192e2ant_media_status_notify(
  2702. btcoexist,
  2703. BTC_MEDIA_CONNECT);
  2704. else
  2705. ex_btc8192e2ant_media_status_notify(
  2706. btcoexist,
  2707. BTC_MEDIA_DISCONNECT);
  2708. }
  2709. if ((coex_sta->bt_info_ext & BIT3)) {
  2710. if (!btcoexist->manual_control &&
  2711. !btcoexist->stop_coex_dm) {
  2712. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2713. "bit3, BT NOT ignore Wlan active!\n");
  2714. btc8192e2ant_ignore_wlan_act(btcoexist,
  2715. FORCE_EXEC,
  2716. false);
  2717. }
  2718. } else {
  2719. /* BT already NOT ignore Wlan active,
  2720. * do nothing here.
  2721. */
  2722. }
  2723. if (!btcoexist->auto_report_2ant) {
  2724. if (!(coex_sta->bt_info_ext & BIT4))
  2725. btc8192e2ant_bt_auto_report(btcoexist,
  2726. FORCE_EXEC,
  2727. true);
  2728. }
  2729. }
  2730. /* check BIT2 first ==> check if bt is under inquiry or page scan */
  2731. if (bt_info & BT_INFO_8192E_2ANT_B_INQ_PAGE)
  2732. coex_sta->c2h_bt_inquiry_page = true;
  2733. else
  2734. coex_sta->c2h_bt_inquiry_page = false;
  2735. /* set link exist status */
  2736. if (!(bt_info&BT_INFO_8192E_2ANT_B_CONNECTION)) {
  2737. coex_sta->bt_link_exist = false;
  2738. coex_sta->pan_exist = false;
  2739. coex_sta->a2dp_exist = false;
  2740. coex_sta->hid_exist = false;
  2741. coex_sta->sco_exist = false;
  2742. } else {/* connection exists */
  2743. coex_sta->bt_link_exist = true;
  2744. if (bt_info & BT_INFO_8192E_2ANT_B_FTP)
  2745. coex_sta->pan_exist = true;
  2746. else
  2747. coex_sta->pan_exist = false;
  2748. if (bt_info & BT_INFO_8192E_2ANT_B_A2DP)
  2749. coex_sta->a2dp_exist = true;
  2750. else
  2751. coex_sta->a2dp_exist = false;
  2752. if (bt_info & BT_INFO_8192E_2ANT_B_HID)
  2753. coex_sta->hid_exist = true;
  2754. else
  2755. coex_sta->hid_exist = false;
  2756. if (bt_info & BT_INFO_8192E_2ANT_B_SCO_ESCO)
  2757. coex_sta->sco_exist = true;
  2758. else
  2759. coex_sta->sco_exist = false;
  2760. }
  2761. btc8192e2ant_update_bt_link_info(btcoexist);
  2762. if (!(bt_info & BT_INFO_8192E_2ANT_B_CONNECTION)) {
  2763. coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE;
  2764. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2765. "[BTCoex], BT Non-Connected idle!!!\n");
  2766. } else if (bt_info == BT_INFO_8192E_2ANT_B_CONNECTION) {
  2767. coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE;
  2768. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2769. "[BTCoex], bt_infoNotify(), BT Connected-idle!!!\n");
  2770. } else if ((bt_info & BT_INFO_8192E_2ANT_B_SCO_ESCO) ||
  2771. (bt_info & BT_INFO_8192E_2ANT_B_SCO_BUSY)) {
  2772. coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_SCO_BUSY;
  2773. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2774. "[BTCoex], bt_infoNotify(), BT SCO busy!!!\n");
  2775. } else if (bt_info & BT_INFO_8192E_2ANT_B_ACL_BUSY) {
  2776. coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_ACL_BUSY;
  2777. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2778. "[BTCoex], bt_infoNotify(), BT ACL busy!!!\n");
  2779. } else {
  2780. coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_MAX;
  2781. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2782. "[BTCoex]bt_infoNotify(), BT Non-Defined state!!!\n");
  2783. }
  2784. if ((BT_8192E_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
  2785. (BT_8192E_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
  2786. (BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) {
  2787. bt_busy = true;
  2788. limited_dig = true;
  2789. } else {
  2790. bt_busy = false;
  2791. limited_dig = false;
  2792. }
  2793. btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
  2794. coex_dm->limited_dig = limited_dig;
  2795. btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig);
  2796. btc8192e2ant_run_coexist_mechanism(btcoexist);
  2797. }
  2798. void ex_btc8192e2ant_halt_notify(struct btc_coexist *btcoexist)
  2799. {
  2800. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2801. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, "[BTCoex], Halt notify\n");
  2802. btc8192e2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
  2803. ex_btc8192e2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
  2804. }
  2805. void ex_btc8192e2ant_periodical(struct btc_coexist *btcoexist)
  2806. {
  2807. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2808. static u8 dis_ver_info_cnt;
  2809. u32 fw_ver = 0, bt_patch_ver = 0;
  2810. struct btc_board_info *board_info = &btcoexist->board_info;
  2811. struct btc_stack_info *stack_info = &btcoexist->stack_info;
  2812. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2813. "=======================Periodical=======================\n");
  2814. if (dis_ver_info_cnt <= 5) {
  2815. dis_ver_info_cnt += 1;
  2816. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2817. "************************************************\n");
  2818. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2819. "Ant PG Num/ Ant Mech/ Ant Pos = %d/ %d/ %d\n",
  2820. board_info->pg_ant_num, board_info->btdm_ant_num,
  2821. board_info->btdm_ant_pos);
  2822. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2823. "BT stack/ hci ext ver = %s / %d\n",
  2824. ((stack_info->profile_notified) ? "Yes" : "No"),
  2825. stack_info->hci_version);
  2826. btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER,
  2827. &bt_patch_ver);
  2828. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
  2829. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2830. "CoexVer/ FwVer/ PatchVer = %d_%x/ 0x%x/ 0x%x(%d)\n",
  2831. glcoex_ver_date_8192e_2ant, glcoex_ver_8192e_2ant,
  2832. fw_ver, bt_patch_ver, bt_patch_ver);
  2833. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2834. "************************************************\n");
  2835. }
  2836. if (!btcoexist->auto_report_2ant) {
  2837. btc8192e2ant_query_bt_info(btcoexist);
  2838. btc8192e2ant_monitor_bt_ctr(btcoexist);
  2839. btc8192e2ant_monitor_bt_enable_disable(btcoexist);
  2840. } else {
  2841. if (btc8192e2ant_is_wifi_status_changed(btcoexist) ||
  2842. coex_dm->auto_tdma_adjust)
  2843. btc8192e2ant_run_coexist_mechanism(btcoexist);
  2844. }
  2845. }