rts5249.c 21 KB

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  1. /* Driver for Realtek PCI-Express card reader
  2. *
  3. * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2, or (at your option) any
  8. * later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along
  16. * with this program; if not, see <http://www.gnu.org/licenses/>.
  17. *
  18. * Author:
  19. * Wei WANG <wei_wang@realsil.com.cn>
  20. */
  21. #include <linux/module.h>
  22. #include <linux/delay.h>
  23. #include <linux/rtsx_pci.h>
  24. #include "rtsx_pcr.h"
  25. static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
  26. {
  27. u8 val;
  28. rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  29. return val & 0x0F;
  30. }
  31. static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  32. {
  33. u8 driving_3v3[4][3] = {
  34. {0x11, 0x11, 0x18},
  35. {0x55, 0x55, 0x5C},
  36. {0xFF, 0xFF, 0xFF},
  37. {0x96, 0x96, 0x96},
  38. };
  39. u8 driving_1v8[4][3] = {
  40. {0xC4, 0xC4, 0xC4},
  41. {0x3C, 0x3C, 0x3C},
  42. {0xFE, 0xFE, 0xFE},
  43. {0xB3, 0xB3, 0xB3},
  44. };
  45. u8 (*driving)[3], drive_sel;
  46. if (voltage == OUTPUT_3V3) {
  47. driving = driving_3v3;
  48. drive_sel = pcr->sd30_drive_sel_3v3;
  49. } else {
  50. driving = driving_1v8;
  51. drive_sel = pcr->sd30_drive_sel_1v8;
  52. }
  53. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
  54. 0xFF, driving[drive_sel][0]);
  55. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
  56. 0xFF, driving[drive_sel][1]);
  57. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
  58. 0xFF, driving[drive_sel][2]);
  59. }
  60. static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
  61. {
  62. u32 reg;
  63. rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
  64. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  65. if (!rtsx_vendor_setting_valid(reg)) {
  66. pcr_dbg(pcr, "skip fetch vendor setting\n");
  67. return;
  68. }
  69. pcr->aspm_en = rtsx_reg_to_aspm(reg);
  70. pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  71. pcr->card_drive_sel &= 0x3F;
  72. pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  73. rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
  74. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  75. pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  76. if (rtsx_reg_check_reverse_socket(reg))
  77. pcr->flags |= PCR_REVERSE_SOCKET;
  78. }
  79. static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
  80. {
  81. /* Set relink_time to 0 */
  82. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
  83. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
  84. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
  85. if (pm_state == HOST_ENTER_S3)
  86. rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
  87. D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
  88. rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
  89. }
  90. static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
  91. {
  92. struct rtsx_cr_option *option = &(pcr->option);
  93. u32 lval;
  94. if (CHK_PCI_PID(pcr, PID_524A))
  95. rtsx_pci_read_config_dword(pcr,
  96. PCR_ASPM_SETTING_REG1, &lval);
  97. else
  98. rtsx_pci_read_config_dword(pcr,
  99. PCR_ASPM_SETTING_REG2, &lval);
  100. if (lval & ASPM_L1_1_EN_MASK)
  101. rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
  102. if (lval & ASPM_L1_2_EN_MASK)
  103. rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
  104. if (lval & PM_L1_1_EN_MASK)
  105. rtsx_set_dev_flag(pcr, PM_L1_1_EN);
  106. if (lval & PM_L1_2_EN_MASK)
  107. rtsx_set_dev_flag(pcr, PM_L1_2_EN);
  108. if (option->ltr_en) {
  109. u16 val;
  110. pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
  111. if (val & PCI_EXP_DEVCTL2_LTR_EN) {
  112. option->ltr_enabled = true;
  113. option->ltr_active = true;
  114. rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
  115. } else {
  116. option->ltr_enabled = false;
  117. }
  118. }
  119. }
  120. static int rts5249_init_from_hw(struct rtsx_pcr *pcr)
  121. {
  122. struct rtsx_cr_option *option = &(pcr->option);
  123. if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
  124. | PM_L1_1_EN | PM_L1_2_EN))
  125. option->force_clkreq_0 = false;
  126. else
  127. option->force_clkreq_0 = true;
  128. return 0;
  129. }
  130. static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
  131. {
  132. struct rtsx_cr_option *option = &(pcr->option);
  133. rts5249_init_from_cfg(pcr);
  134. rts5249_init_from_hw(pcr);
  135. rtsx_pci_init_cmd(pcr);
  136. /* Rest L1SUB Config */
  137. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
  138. /* Configure GPIO as output */
  139. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
  140. /* Reset ASPM state to default value */
  141. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
  142. /* Switch LDO3318 source from DV33 to card_3v3 */
  143. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
  144. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
  145. /* LED shine disabled, set initial shine cycle period */
  146. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
  147. /* Configure driving */
  148. rts5249_fill_driving(pcr, OUTPUT_3V3);
  149. if (pcr->flags & PCR_REVERSE_SOCKET)
  150. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
  151. else
  152. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
  153. /*
  154. * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
  155. * to drive low, and we forcibly request clock.
  156. */
  157. if (option->force_clkreq_0)
  158. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
  159. FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
  160. else
  161. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
  162. FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
  163. return rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
  164. }
  165. static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
  166. {
  167. int err;
  168. err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
  169. if (err < 0)
  170. return err;
  171. err = rtsx_pci_write_phy_register(pcr, PHY_REV,
  172. PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED |
  173. PHY_REV_P1_EN | PHY_REV_RXIDLE_EN |
  174. PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST |
  175. PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD |
  176. PHY_REV_STOP_CLKWR);
  177. if (err < 0)
  178. return err;
  179. msleep(1);
  180. err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
  181. PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
  182. PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);
  183. if (err < 0)
  184. return err;
  185. err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
  186. PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
  187. PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
  188. PHY_PCR_RSSI_EN | PHY_PCR_RX10K);
  189. if (err < 0)
  190. return err;
  191. err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
  192. PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR |
  193. PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 |
  194. PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE);
  195. if (err < 0)
  196. return err;
  197. err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,
  198. PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF |
  199. PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA |
  200. PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER |
  201. PHY_FLD4_BER_CHK_EN);
  202. if (err < 0)
  203. return err;
  204. err = rtsx_pci_write_phy_register(pcr, PHY_RDR,
  205. PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD);
  206. if (err < 0)
  207. return err;
  208. err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,
  209. PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE);
  210. if (err < 0)
  211. return err;
  212. err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,
  213. PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 |
  214. PHY_FLD3_RXDELINK);
  215. if (err < 0)
  216. return err;
  217. return rtsx_pci_write_phy_register(pcr, PHY_TUNE,
  218. PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 |
  219. PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 |
  220. PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12);
  221. }
  222. static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)
  223. {
  224. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
  225. }
  226. static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)
  227. {
  228. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
  229. }
  230. static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
  231. {
  232. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
  233. }
  234. static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
  235. {
  236. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
  237. }
  238. static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)
  239. {
  240. int err;
  241. rtsx_pci_init_cmd(pcr);
  242. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  243. SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
  244. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  245. LDO3318_PWR_MASK, 0x02);
  246. err = rtsx_pci_send_cmd(pcr, 100);
  247. if (err < 0)
  248. return err;
  249. msleep(5);
  250. rtsx_pci_init_cmd(pcr);
  251. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  252. SD_POWER_MASK, SD_VCC_POWER_ON);
  253. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  254. LDO3318_PWR_MASK, 0x06);
  255. return rtsx_pci_send_cmd(pcr, 100);
  256. }
  257. static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)
  258. {
  259. rtsx_pci_init_cmd(pcr);
  260. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  261. SD_POWER_MASK, SD_POWER_OFF);
  262. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  263. LDO3318_PWR_MASK, 0x00);
  264. return rtsx_pci_send_cmd(pcr, 100);
  265. }
  266. static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  267. {
  268. int err;
  269. u16 append;
  270. switch (voltage) {
  271. case OUTPUT_3V3:
  272. err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
  273. PHY_TUNE_VOLTAGE_3V3);
  274. if (err < 0)
  275. return err;
  276. break;
  277. case OUTPUT_1V8:
  278. append = PHY_TUNE_D18_1V8;
  279. if (CHK_PCI_PID(pcr, 0x5249)) {
  280. err = rtsx_pci_update_phy(pcr, PHY_BACR,
  281. PHY_BACR_BASIC_MASK, 0);
  282. if (err < 0)
  283. return err;
  284. append = PHY_TUNE_D18_1V7;
  285. }
  286. err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
  287. append);
  288. if (err < 0)
  289. return err;
  290. break;
  291. default:
  292. pcr_dbg(pcr, "unknown output voltage %d\n", voltage);
  293. return -EINVAL;
  294. }
  295. /* set pad drive */
  296. rtsx_pci_init_cmd(pcr);
  297. rts5249_fill_driving(pcr, voltage);
  298. return rtsx_pci_send_cmd(pcr, 100);
  299. }
  300. static void rts5249_set_aspm(struct rtsx_pcr *pcr, bool enable)
  301. {
  302. struct rtsx_cr_option *option = &pcr->option;
  303. u8 val = 0;
  304. if (pcr->aspm_enabled == enable)
  305. return;
  306. if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) {
  307. if (enable)
  308. val = pcr->aspm_en;
  309. rtsx_pci_update_cfg_byte(pcr,
  310. pcr->pcie_cap + PCI_EXP_LNKCTL,
  311. ASPM_MASK_NEG, val);
  312. } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) {
  313. u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0;
  314. if (!enable)
  315. val = FORCE_ASPM_CTL0;
  316. rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
  317. }
  318. pcr->aspm_enabled = enable;
  319. }
  320. static const struct pcr_ops rts5249_pcr_ops = {
  321. .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
  322. .extra_init_hw = rts5249_extra_init_hw,
  323. .optimize_phy = rts5249_optimize_phy,
  324. .turn_on_led = rtsx_base_turn_on_led,
  325. .turn_off_led = rtsx_base_turn_off_led,
  326. .enable_auto_blink = rtsx_base_enable_auto_blink,
  327. .disable_auto_blink = rtsx_base_disable_auto_blink,
  328. .card_power_on = rtsx_base_card_power_on,
  329. .card_power_off = rtsx_base_card_power_off,
  330. .switch_output_voltage = rtsx_base_switch_output_voltage,
  331. .force_power_down = rtsx_base_force_power_down,
  332. .set_aspm = rts5249_set_aspm,
  333. };
  334. /* SD Pull Control Enable:
  335. * SD_DAT[3:0] ==> pull up
  336. * SD_CD ==> pull up
  337. * SD_WP ==> pull up
  338. * SD_CMD ==> pull up
  339. * SD_CLK ==> pull down
  340. */
  341. static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
  342. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
  343. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  344. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
  345. RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
  346. 0,
  347. };
  348. /* SD Pull Control Disable:
  349. * SD_DAT[3:0] ==> pull down
  350. * SD_CD ==> pull up
  351. * SD_WP ==> pull down
  352. * SD_CMD ==> pull down
  353. * SD_CLK ==> pull down
  354. */
  355. static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
  356. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
  357. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  358. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
  359. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
  360. 0,
  361. };
  362. /* MS Pull Control Enable:
  363. * MS CD ==> pull up
  364. * others ==> pull down
  365. */
  366. static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
  367. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
  368. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  369. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  370. 0,
  371. };
  372. /* MS Pull Control Disable:
  373. * MS CD ==> pull up
  374. * others ==> pull down
  375. */
  376. static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
  377. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
  378. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  379. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  380. 0,
  381. };
  382. void rts5249_init_params(struct rtsx_pcr *pcr)
  383. {
  384. struct rtsx_cr_option *option = &(pcr->option);
  385. pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
  386. pcr->num_slots = 2;
  387. pcr->ops = &rts5249_pcr_ops;
  388. pcr->flags = 0;
  389. pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
  390. pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
  391. pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
  392. pcr->aspm_en = ASPM_L1_EN;
  393. pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
  394. pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
  395. pcr->ic_version = rts5249_get_ic_version(pcr);
  396. pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
  397. pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
  398. pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
  399. pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
  400. pcr->reg_pm_ctrl3 = PM_CTRL3;
  401. option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
  402. | LTR_L1SS_PWR_GATE_EN);
  403. option->ltr_en = true;
  404. /* Init latency of active, idle, L1OFF to 60us, 300us, 3ms */
  405. option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
  406. option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
  407. option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
  408. option->dev_aspm_mode = DEV_ASPM_DYNAMIC;
  409. option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
  410. option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF;
  411. option->ltr_l1off_snooze_sspwrgate =
  412. LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF;
  413. }
  414. static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
  415. {
  416. addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
  417. return __rtsx_pci_write_phy_register(pcr, addr, val);
  418. }
  419. static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)
  420. {
  421. addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
  422. return __rtsx_pci_read_phy_register(pcr, addr, val);
  423. }
  424. static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
  425. {
  426. int err;
  427. err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
  428. D3_DELINK_MODE_EN, 0x00);
  429. if (err < 0)
  430. return err;
  431. rtsx_pci_write_phy_register(pcr, PHY_PCR,
  432. PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
  433. PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN);
  434. rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
  435. PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
  436. if (is_version(pcr, 0x524A, IC_VER_A)) {
  437. rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
  438. PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
  439. rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
  440. PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 |
  441. PHY_SSCCR2_TIME2_WIDTH);
  442. rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
  443. PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST |
  444. PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV);
  445. rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
  446. PHY_ANA1D_DEBUG_ADDR);
  447. rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
  448. PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 |
  449. PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST |
  450. PHY_DIG1E_RCLK_TX_EN_KEEP |
  451. PHY_DIG1E_RCLK_TX_TERM_KEEP |
  452. PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP |
  453. PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP |
  454. PHY_DIG1E_RX_EN_KEEP);
  455. }
  456. rtsx_pci_write_phy_register(pcr, PHY_ANA08,
  457. PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN |
  458. PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI);
  459. return 0;
  460. }
  461. static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)
  462. {
  463. rts5249_extra_init_hw(pcr);
  464. rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
  465. FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN);
  466. rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
  467. rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,
  468. LDO_VCC_LMT_EN);
  469. rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
  470. if (is_version(pcr, 0x524A, IC_VER_A)) {
  471. rtsx_pci_write_register(pcr, LDO_DV18_CFG,
  472. LDO_DV18_SR_MASK, LDO_DV18_SR_DF);
  473. rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
  474. LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2);
  475. rtsx_pci_write_register(pcr, LDO_VIO_CFG,
  476. LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2);
  477. rtsx_pci_write_register(pcr, LDO_VIO_CFG,
  478. LDO_VIO_SR_MASK, LDO_VIO_SR_DF);
  479. rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
  480. LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF);
  481. rtsx_pci_write_register(pcr, SD40_LDO_CTL1,
  482. SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7);
  483. }
  484. return 0;
  485. }
  486. static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
  487. {
  488. struct rtsx_cr_option *option = &(pcr->option);
  489. u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
  490. int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST);
  491. int aspm_L1_1, aspm_L1_2;
  492. u8 val = 0;
  493. aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
  494. aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
  495. if (active) {
  496. /* Run, latency: 60us */
  497. if (aspm_L1_1)
  498. val = option->ltr_l1off_snooze_sspwrgate;
  499. } else {
  500. /* L1off, latency: 300us */
  501. if (aspm_L1_2)
  502. val = option->ltr_l1off_sspwrgate;
  503. }
  504. if (aspm_L1_1 || aspm_L1_2) {
  505. if (rtsx_check_dev_flag(pcr,
  506. LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) {
  507. if (card_exist)
  508. val &= ~L1OFF_MBIAS2_EN_5250;
  509. else
  510. val |= L1OFF_MBIAS2_EN_5250;
  511. }
  512. }
  513. rtsx_set_l1off_sub(pcr, val);
  514. }
  515. static const struct pcr_ops rts524a_pcr_ops = {
  516. .write_phy = rts524a_write_phy,
  517. .read_phy = rts524a_read_phy,
  518. .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
  519. .extra_init_hw = rts524a_extra_init_hw,
  520. .optimize_phy = rts524a_optimize_phy,
  521. .turn_on_led = rtsx_base_turn_on_led,
  522. .turn_off_led = rtsx_base_turn_off_led,
  523. .enable_auto_blink = rtsx_base_enable_auto_blink,
  524. .disable_auto_blink = rtsx_base_disable_auto_blink,
  525. .card_power_on = rtsx_base_card_power_on,
  526. .card_power_off = rtsx_base_card_power_off,
  527. .switch_output_voltage = rtsx_base_switch_output_voltage,
  528. .force_power_down = rtsx_base_force_power_down,
  529. .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
  530. .set_aspm = rts5249_set_aspm,
  531. };
  532. void rts524a_init_params(struct rtsx_pcr *pcr)
  533. {
  534. rts5249_init_params(pcr);
  535. pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
  536. pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
  537. pcr->option.ltr_l1off_snooze_sspwrgate =
  538. LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
  539. pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
  540. pcr->ops = &rts524a_pcr_ops;
  541. }
  542. static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card)
  543. {
  544. rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
  545. LDO_VCC_TUNE_MASK, LDO_VCC_3V3);
  546. return rtsx_base_card_power_on(pcr, card);
  547. }
  548. static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  549. {
  550. switch (voltage) {
  551. case OUTPUT_3V3:
  552. rtsx_pci_write_register(pcr, LDO_CONFIG2,
  553. LDO_D3318_MASK, LDO_D3318_33V);
  554. rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
  555. break;
  556. case OUTPUT_1V8:
  557. rtsx_pci_write_register(pcr, LDO_CONFIG2,
  558. LDO_D3318_MASK, LDO_D3318_18V);
  559. rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
  560. SD_IO_USING_1V8);
  561. break;
  562. default:
  563. return -EINVAL;
  564. }
  565. rtsx_pci_init_cmd(pcr);
  566. rts5249_fill_driving(pcr, voltage);
  567. return rtsx_pci_send_cmd(pcr, 100);
  568. }
  569. static int rts525a_optimize_phy(struct rtsx_pcr *pcr)
  570. {
  571. int err;
  572. err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
  573. D3_DELINK_MODE_EN, 0x00);
  574. if (err < 0)
  575. return err;
  576. rtsx_pci_write_phy_register(pcr, _PHY_FLD0,
  577. _PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN |
  578. _PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT |
  579. _PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN);
  580. rtsx_pci_write_phy_register(pcr, _PHY_ANA03,
  581. _PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN |
  582. _PHY_CMU_DEBUG_EN);
  583. if (is_version(pcr, 0x525A, IC_VER_A))
  584. rtsx_pci_write_phy_register(pcr, _PHY_REV0,
  585. _PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD |
  586. _PHY_REV0_CDR_RX_IDLE_BYPASS);
  587. return 0;
  588. }
  589. static int rts525a_extra_init_hw(struct rtsx_pcr *pcr)
  590. {
  591. rts5249_extra_init_hw(pcr);
  592. rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
  593. if (is_version(pcr, 0x525A, IC_VER_A)) {
  594. rtsx_pci_write_register(pcr, L1SUB_CONFIG2,
  595. L1SUB_AUTO_CFG, L1SUB_AUTO_CFG);
  596. rtsx_pci_write_register(pcr, RREF_CFG,
  597. RREF_VBGSEL_MASK, RREF_VBGSEL_1V25);
  598. rtsx_pci_write_register(pcr, LDO_VIO_CFG,
  599. LDO_VIO_TUNE_MASK, LDO_VIO_1V7);
  600. rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
  601. LDO_D12_TUNE_MASK, LDO_D12_TUNE_DF);
  602. rtsx_pci_write_register(pcr, LDO_AV12S_CFG,
  603. LDO_AV12S_TUNE_MASK, LDO_AV12S_TUNE_DF);
  604. rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
  605. LDO_VCC_LMTVTH_MASK, LDO_VCC_LMTVTH_2A);
  606. rtsx_pci_write_register(pcr, OOBS_CONFIG,
  607. OOBS_AUTOK_DIS | OOBS_VAL_MASK, 0x89);
  608. }
  609. return 0;
  610. }
  611. static const struct pcr_ops rts525a_pcr_ops = {
  612. .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
  613. .extra_init_hw = rts525a_extra_init_hw,
  614. .optimize_phy = rts525a_optimize_phy,
  615. .turn_on_led = rtsx_base_turn_on_led,
  616. .turn_off_led = rtsx_base_turn_off_led,
  617. .enable_auto_blink = rtsx_base_enable_auto_blink,
  618. .disable_auto_blink = rtsx_base_disable_auto_blink,
  619. .card_power_on = rts525a_card_power_on,
  620. .card_power_off = rtsx_base_card_power_off,
  621. .switch_output_voltage = rts525a_switch_output_voltage,
  622. .force_power_down = rtsx_base_force_power_down,
  623. .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
  624. .set_aspm = rts5249_set_aspm,
  625. };
  626. void rts525a_init_params(struct rtsx_pcr *pcr)
  627. {
  628. rts5249_init_params(pcr);
  629. pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11);
  630. pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
  631. pcr->option.ltr_l1off_snooze_sspwrgate =
  632. LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
  633. pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
  634. pcr->ops = &rts525a_pcr_ops;
  635. }