platsmp.c 2.6 KB

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  1. /*
  2. * Copyright (C) 2002 ARM Ltd.
  3. * Copyright (C) 2008 STMicroelctronics.
  4. * Copyright (C) 2009 ST-Ericsson.
  5. * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
  6. *
  7. * This file is based on arm realview platform
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/init.h>
  14. #include <linux/errno.h>
  15. #include <linux/delay.h>
  16. #include <linux/device.h>
  17. #include <linux/smp.h>
  18. #include <linux/io.h>
  19. #include <linux/of.h>
  20. #include <linux/of_address.h>
  21. #include <asm/cacheflush.h>
  22. #include <asm/smp_plat.h>
  23. #include <asm/smp_scu.h>
  24. #include "db8500-regs.h"
  25. /* Magic triggers in backup RAM */
  26. #define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
  27. #define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
  28. static void __iomem *backupram;
  29. static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
  30. {
  31. struct device_node *np;
  32. static void __iomem *scu_base;
  33. unsigned int ncores;
  34. int i;
  35. np = of_find_compatible_node(NULL, NULL, "ste,dbx500-backupram");
  36. if (!np) {
  37. pr_err("No backupram base address\n");
  38. return;
  39. }
  40. backupram = of_iomap(np, 0);
  41. of_node_put(np);
  42. if (!backupram) {
  43. pr_err("No backupram remap\n");
  44. return;
  45. }
  46. np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
  47. if (!np) {
  48. pr_err("No SCU base address\n");
  49. return;
  50. }
  51. scu_base = of_iomap(np, 0);
  52. of_node_put(np);
  53. if (!scu_base) {
  54. pr_err("No SCU remap\n");
  55. return;
  56. }
  57. scu_enable(scu_base);
  58. ncores = scu_get_core_count(scu_base);
  59. for (i = 0; i < ncores; i++)
  60. set_cpu_possible(i, true);
  61. iounmap(scu_base);
  62. }
  63. static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
  64. {
  65. /*
  66. * write the address of secondary startup into the backup ram register
  67. * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
  68. * backup ram register at offset 0x1FF0, which is what boot rom code
  69. * is waiting for. This will wake up the secondary core from WFE.
  70. */
  71. writel(__pa_symbol(secondary_startup),
  72. backupram + UX500_CPU1_JUMPADDR_OFFSET);
  73. writel(0xA1FEED01,
  74. backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
  75. /* make sure write buffer is drained */
  76. mb();
  77. arch_send_wakeup_ipi_mask(cpumask_of(cpu));
  78. return 0;
  79. }
  80. #ifdef CONFIG_HOTPLUG_CPU
  81. void ux500_cpu_die(unsigned int cpu)
  82. {
  83. wfi();
  84. }
  85. #endif
  86. static const struct smp_operations ux500_smp_ops __initconst = {
  87. .smp_prepare_cpus = ux500_smp_prepare_cpus,
  88. .smp_boot_secondary = ux500_boot_secondary,
  89. #ifdef CONFIG_HOTPLUG_CPU
  90. .cpu_die = ux500_cpu_die,
  91. #endif
  92. };
  93. CPU_METHOD_OF_DECLARE(ux500_smp, "ste,dbx500-smp", &ux500_smp_ops);