mtu3_plat.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2016 MediaTek Inc.
  4. *
  5. * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/dma-mapping.h>
  9. #include <linux/iopoll.h>
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/of_address.h>
  13. #include <linux/of_irq.h>
  14. #include <linux/platform_device.h>
  15. #include "mtu3.h"
  16. #include "mtu3_dr.h"
  17. /* u2-port0 should be powered on and enabled; */
  18. int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks)
  19. {
  20. void __iomem *ibase = ssusb->ippc_base;
  21. u32 value, check_val;
  22. int ret;
  23. check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE |
  24. SSUSB_REF_RST_B_STS;
  25. ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
  26. (check_val == (value & check_val)), 100, 20000);
  27. if (ret) {
  28. dev_err(ssusb->dev, "clks of sts1 are not stable!\n");
  29. return ret;
  30. }
  31. ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value,
  32. (value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000);
  33. if (ret) {
  34. dev_err(ssusb->dev, "mac2 clock is not stable\n");
  35. return ret;
  36. }
  37. return 0;
  38. }
  39. static int ssusb_phy_init(struct ssusb_mtk *ssusb)
  40. {
  41. int i;
  42. int ret;
  43. for (i = 0; i < ssusb->num_phys; i++) {
  44. ret = phy_init(ssusb->phys[i]);
  45. if (ret)
  46. goto exit_phy;
  47. }
  48. return 0;
  49. exit_phy:
  50. for (; i > 0; i--)
  51. phy_exit(ssusb->phys[i - 1]);
  52. return ret;
  53. }
  54. static int ssusb_phy_exit(struct ssusb_mtk *ssusb)
  55. {
  56. int i;
  57. for (i = 0; i < ssusb->num_phys; i++)
  58. phy_exit(ssusb->phys[i]);
  59. return 0;
  60. }
  61. static int ssusb_phy_power_on(struct ssusb_mtk *ssusb)
  62. {
  63. int i;
  64. int ret;
  65. for (i = 0; i < ssusb->num_phys; i++) {
  66. ret = phy_power_on(ssusb->phys[i]);
  67. if (ret)
  68. goto power_off_phy;
  69. }
  70. return 0;
  71. power_off_phy:
  72. for (; i > 0; i--)
  73. phy_power_off(ssusb->phys[i - 1]);
  74. return ret;
  75. }
  76. static void ssusb_phy_power_off(struct ssusb_mtk *ssusb)
  77. {
  78. unsigned int i;
  79. for (i = 0; i < ssusb->num_phys; i++)
  80. phy_power_off(ssusb->phys[i]);
  81. }
  82. static int ssusb_clks_enable(struct ssusb_mtk *ssusb)
  83. {
  84. int ret;
  85. ret = clk_prepare_enable(ssusb->sys_clk);
  86. if (ret) {
  87. dev_err(ssusb->dev, "failed to enable sys_clk\n");
  88. goto sys_clk_err;
  89. }
  90. ret = clk_prepare_enable(ssusb->ref_clk);
  91. if (ret) {
  92. dev_err(ssusb->dev, "failed to enable ref_clk\n");
  93. goto ref_clk_err;
  94. }
  95. ret = clk_prepare_enable(ssusb->mcu_clk);
  96. if (ret) {
  97. dev_err(ssusb->dev, "failed to enable mcu_clk\n");
  98. goto mcu_clk_err;
  99. }
  100. ret = clk_prepare_enable(ssusb->dma_clk);
  101. if (ret) {
  102. dev_err(ssusb->dev, "failed to enable dma_clk\n");
  103. goto dma_clk_err;
  104. }
  105. return 0;
  106. dma_clk_err:
  107. clk_disable_unprepare(ssusb->mcu_clk);
  108. mcu_clk_err:
  109. clk_disable_unprepare(ssusb->ref_clk);
  110. ref_clk_err:
  111. clk_disable_unprepare(ssusb->sys_clk);
  112. sys_clk_err:
  113. return ret;
  114. }
  115. static void ssusb_clks_disable(struct ssusb_mtk *ssusb)
  116. {
  117. clk_disable_unprepare(ssusb->dma_clk);
  118. clk_disable_unprepare(ssusb->mcu_clk);
  119. clk_disable_unprepare(ssusb->ref_clk);
  120. clk_disable_unprepare(ssusb->sys_clk);
  121. }
  122. static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
  123. {
  124. int ret = 0;
  125. ret = regulator_enable(ssusb->vusb33);
  126. if (ret) {
  127. dev_err(ssusb->dev, "failed to enable vusb33\n");
  128. goto vusb33_err;
  129. }
  130. ret = ssusb_clks_enable(ssusb);
  131. if (ret)
  132. goto clks_err;
  133. ret = ssusb_phy_init(ssusb);
  134. if (ret) {
  135. dev_err(ssusb->dev, "failed to init phy\n");
  136. goto phy_init_err;
  137. }
  138. ret = ssusb_phy_power_on(ssusb);
  139. if (ret) {
  140. dev_err(ssusb->dev, "failed to power on phy\n");
  141. goto phy_err;
  142. }
  143. return 0;
  144. phy_err:
  145. ssusb_phy_exit(ssusb);
  146. phy_init_err:
  147. ssusb_clks_disable(ssusb);
  148. clks_err:
  149. regulator_disable(ssusb->vusb33);
  150. vusb33_err:
  151. return ret;
  152. }
  153. static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
  154. {
  155. ssusb_clks_disable(ssusb);
  156. regulator_disable(ssusb->vusb33);
  157. ssusb_phy_power_off(ssusb);
  158. ssusb_phy_exit(ssusb);
  159. }
  160. static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb)
  161. {
  162. /* reset whole ip (xhci & u3d) */
  163. mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
  164. udelay(1);
  165. mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
  166. }
  167. /* ignore the error if the clock does not exist */
  168. static struct clk *get_optional_clk(struct device *dev, const char *id)
  169. {
  170. struct clk *opt_clk;
  171. opt_clk = devm_clk_get(dev, id);
  172. /* ignore error number except EPROBE_DEFER */
  173. if (IS_ERR(opt_clk) && (PTR_ERR(opt_clk) != -EPROBE_DEFER))
  174. opt_clk = NULL;
  175. return opt_clk;
  176. }
  177. static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
  178. {
  179. struct device_node *node = pdev->dev.of_node;
  180. struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
  181. struct device *dev = &pdev->dev;
  182. struct regulator *vbus;
  183. struct resource *res;
  184. int i;
  185. int ret;
  186. ssusb->vusb33 = devm_regulator_get(&pdev->dev, "vusb33");
  187. if (IS_ERR(ssusb->vusb33)) {
  188. dev_err(dev, "failed to get vusb33\n");
  189. return PTR_ERR(ssusb->vusb33);
  190. }
  191. ssusb->sys_clk = devm_clk_get(dev, "sys_ck");
  192. if (IS_ERR(ssusb->sys_clk)) {
  193. dev_err(dev, "failed to get sys clock\n");
  194. return PTR_ERR(ssusb->sys_clk);
  195. }
  196. ssusb->ref_clk = get_optional_clk(dev, "ref_ck");
  197. if (IS_ERR(ssusb->ref_clk))
  198. return PTR_ERR(ssusb->ref_clk);
  199. ssusb->mcu_clk = get_optional_clk(dev, "mcu_ck");
  200. if (IS_ERR(ssusb->mcu_clk))
  201. return PTR_ERR(ssusb->mcu_clk);
  202. ssusb->dma_clk = get_optional_clk(dev, "dma_ck");
  203. if (IS_ERR(ssusb->dma_clk))
  204. return PTR_ERR(ssusb->dma_clk);
  205. ssusb->num_phys = of_count_phandle_with_args(node,
  206. "phys", "#phy-cells");
  207. if (ssusb->num_phys > 0) {
  208. ssusb->phys = devm_kcalloc(dev, ssusb->num_phys,
  209. sizeof(*ssusb->phys), GFP_KERNEL);
  210. if (!ssusb->phys)
  211. return -ENOMEM;
  212. } else {
  213. ssusb->num_phys = 0;
  214. }
  215. for (i = 0; i < ssusb->num_phys; i++) {
  216. ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i);
  217. if (IS_ERR(ssusb->phys[i])) {
  218. dev_err(dev, "failed to get phy-%d\n", i);
  219. return PTR_ERR(ssusb->phys[i]);
  220. }
  221. }
  222. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
  223. ssusb->ippc_base = devm_ioremap_resource(dev, res);
  224. if (IS_ERR(ssusb->ippc_base))
  225. return PTR_ERR(ssusb->ippc_base);
  226. ssusb->dr_mode = usb_get_dr_mode(dev);
  227. if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN)
  228. ssusb->dr_mode = USB_DR_MODE_OTG;
  229. if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL)
  230. return 0;
  231. /* if host role is supported */
  232. ret = ssusb_wakeup_of_property_parse(ssusb, node);
  233. if (ret) {
  234. dev_err(dev, "failed to parse uwk property\n");
  235. return ret;
  236. }
  237. /* optional property, ignore the error if it does not exist */
  238. of_property_read_u32(node, "mediatek,u3p-dis-msk",
  239. &ssusb->u3p_dis_msk);
  240. vbus = devm_regulator_get(&pdev->dev, "vbus");
  241. if (IS_ERR(vbus)) {
  242. dev_err(dev, "failed to get vbus\n");
  243. return PTR_ERR(vbus);
  244. }
  245. otg_sx->vbus = vbus;
  246. if (ssusb->dr_mode == USB_DR_MODE_HOST)
  247. return 0;
  248. /* if dual-role mode is supported */
  249. otg_sx->is_u3_drd = of_property_read_bool(node, "mediatek,usb3-drd");
  250. otg_sx->manual_drd_enabled =
  251. of_property_read_bool(node, "enable-manual-drd");
  252. if (of_property_read_bool(node, "extcon")) {
  253. otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0);
  254. if (IS_ERR(otg_sx->edev)) {
  255. dev_err(ssusb->dev, "couldn't get extcon device\n");
  256. return PTR_ERR(otg_sx->edev);
  257. }
  258. }
  259. dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk: %x, drd: %s\n",
  260. ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk,
  261. otg_sx->manual_drd_enabled ? "manual" : "auto");
  262. return 0;
  263. }
  264. static int mtu3_probe(struct platform_device *pdev)
  265. {
  266. struct device_node *node = pdev->dev.of_node;
  267. struct device *dev = &pdev->dev;
  268. struct ssusb_mtk *ssusb;
  269. int ret = -ENOMEM;
  270. /* all elements are set to ZERO as default value */
  271. ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL);
  272. if (!ssusb)
  273. return -ENOMEM;
  274. ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
  275. if (ret) {
  276. dev_err(dev, "No suitable DMA config available\n");
  277. return -ENOTSUPP;
  278. }
  279. platform_set_drvdata(pdev, ssusb);
  280. ssusb->dev = dev;
  281. ret = get_ssusb_rscs(pdev, ssusb);
  282. if (ret)
  283. return ret;
  284. /* enable power domain */
  285. pm_runtime_enable(dev);
  286. pm_runtime_get_sync(dev);
  287. device_enable_async_suspend(dev);
  288. ret = ssusb_rscs_init(ssusb);
  289. if (ret)
  290. goto comm_init_err;
  291. ssusb_ip_sw_reset(ssusb);
  292. if (IS_ENABLED(CONFIG_USB_MTU3_HOST))
  293. ssusb->dr_mode = USB_DR_MODE_HOST;
  294. else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET))
  295. ssusb->dr_mode = USB_DR_MODE_PERIPHERAL;
  296. /* default as host */
  297. ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL);
  298. switch (ssusb->dr_mode) {
  299. case USB_DR_MODE_PERIPHERAL:
  300. ret = ssusb_gadget_init(ssusb);
  301. if (ret) {
  302. dev_err(dev, "failed to initialize gadget\n");
  303. goto comm_exit;
  304. }
  305. break;
  306. case USB_DR_MODE_HOST:
  307. ret = ssusb_host_init(ssusb, node);
  308. if (ret) {
  309. dev_err(dev, "failed to initialize host\n");
  310. goto comm_exit;
  311. }
  312. break;
  313. case USB_DR_MODE_OTG:
  314. ret = ssusb_gadget_init(ssusb);
  315. if (ret) {
  316. dev_err(dev, "failed to initialize gadget\n");
  317. goto comm_exit;
  318. }
  319. ret = ssusb_host_init(ssusb, node);
  320. if (ret) {
  321. dev_err(dev, "failed to initialize host\n");
  322. goto gadget_exit;
  323. }
  324. ssusb_otg_switch_init(ssusb);
  325. break;
  326. default:
  327. dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode);
  328. ret = -EINVAL;
  329. goto comm_exit;
  330. }
  331. return 0;
  332. gadget_exit:
  333. ssusb_gadget_exit(ssusb);
  334. comm_exit:
  335. ssusb_rscs_exit(ssusb);
  336. comm_init_err:
  337. pm_runtime_put_sync(dev);
  338. pm_runtime_disable(dev);
  339. return ret;
  340. }
  341. static int mtu3_remove(struct platform_device *pdev)
  342. {
  343. struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
  344. switch (ssusb->dr_mode) {
  345. case USB_DR_MODE_PERIPHERAL:
  346. ssusb_gadget_exit(ssusb);
  347. break;
  348. case USB_DR_MODE_HOST:
  349. ssusb_host_exit(ssusb);
  350. break;
  351. case USB_DR_MODE_OTG:
  352. ssusb_otg_switch_exit(ssusb);
  353. ssusb_gadget_exit(ssusb);
  354. ssusb_host_exit(ssusb);
  355. break;
  356. default:
  357. return -EINVAL;
  358. }
  359. ssusb_rscs_exit(ssusb);
  360. pm_runtime_put_sync(&pdev->dev);
  361. pm_runtime_disable(&pdev->dev);
  362. return 0;
  363. }
  364. /*
  365. * when support dual-role mode, we reject suspend when
  366. * it works as device mode;
  367. */
  368. static int __maybe_unused mtu3_suspend(struct device *dev)
  369. {
  370. struct ssusb_mtk *ssusb = dev_get_drvdata(dev);
  371. dev_dbg(dev, "%s\n", __func__);
  372. /* REVISIT: disconnect it for only device mode? */
  373. if (!ssusb->is_host)
  374. return 0;
  375. ssusb_host_disable(ssusb, true);
  376. ssusb_phy_power_off(ssusb);
  377. ssusb_clks_disable(ssusb);
  378. ssusb_wakeup_set(ssusb, true);
  379. return 0;
  380. }
  381. static int __maybe_unused mtu3_resume(struct device *dev)
  382. {
  383. struct ssusb_mtk *ssusb = dev_get_drvdata(dev);
  384. int ret;
  385. dev_dbg(dev, "%s\n", __func__);
  386. if (!ssusb->is_host)
  387. return 0;
  388. ssusb_wakeup_set(ssusb, false);
  389. ret = ssusb_clks_enable(ssusb);
  390. if (ret)
  391. goto clks_err;
  392. ret = ssusb_phy_power_on(ssusb);
  393. if (ret)
  394. goto phy_err;
  395. ssusb_host_enable(ssusb);
  396. return 0;
  397. phy_err:
  398. ssusb_clks_disable(ssusb);
  399. clks_err:
  400. return ret;
  401. }
  402. static const struct dev_pm_ops mtu3_pm_ops = {
  403. SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume)
  404. };
  405. #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL)
  406. #ifdef CONFIG_OF
  407. static const struct of_device_id mtu3_of_match[] = {
  408. {.compatible = "mediatek,mt8173-mtu3",},
  409. {.compatible = "mediatek,mtu3",},
  410. {},
  411. };
  412. MODULE_DEVICE_TABLE(of, mtu3_of_match);
  413. #endif
  414. static struct platform_driver mtu3_driver = {
  415. .probe = mtu3_probe,
  416. .remove = mtu3_remove,
  417. .driver = {
  418. .name = MTU3_DRIVER_NAME,
  419. .pm = DEV_PM_OPS,
  420. .of_match_table = of_match_ptr(mtu3_of_match),
  421. },
  422. };
  423. module_platform_driver(mtu3_driver);
  424. MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
  425. MODULE_LICENSE("GPL v2");
  426. MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver");