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linux-phytium
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drivers
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spi
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spi-fsl-spi.h

spi-fsl-spi.h 2.0 KB
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  1. /*
    2. 

  2.  * Freescale SPI controller driver.
    3. 

  3.  *
    4. 

  4.  * Maintainer: Kumar Gala
    5. 

  5.  *
    6. 

  6.  * Copyright (C) 2006 Polycom, Inc.
    7. 

  7.  * Copyright 2010 Freescale Semiconductor, Inc.
    8. 

  8.  *
    9. 

  9.  * CPM SPI and QE buffer descriptors mode support:
    10. 

  10.  * Copyright (c) 2009  MontaVista Software, Inc.
    11. 

  11.  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
    12. 

  12.  *
    13. 

  13.  * GRLIB support:
    14. 

  14.  * Copyright (c) 2012 Aeroflex Gaisler AB.
    15. 

  15.  * Author: Andreas Larsson <andreas@gaisler.com>
    16. 

  16.  *
    17. 

  17.  * This program is free software; you can redistribute  it and/or modify it
    18. 

  18.  * under  the terms of  the GNU General  Public License as published by the
    19. 

  19.  * Free Software Foundation;  either version 2 of the  License, or (at your
    20. 

  20.  * option) any later version.
    21. 

  21.  */
    22. 

  22. 

  23. #ifndef __SPI_FSL_SPI_H__
    24. 

  24. #define __SPI_FSL_SPI_H__
    25. 

  25. 

  26. /* SPI Controller registers */
    27. 

  27. struct fsl_spi_reg {
    28. 

  28. 	__be32 cap; /* TYPE_GRLIB specific */
    29. 

  29. 	u8 res1[0x1C];
    30. 

  30. 	__be32 mode;
    31. 

  31. 	__be32 event;
    32. 

  32. 	__be32 mask;
    33. 

  33. 	__be32 command;
    34. 

  34. 	__be32 transmit;
    35. 

  35. 	__be32 receive;
    36. 

  36. 	__be32 slvsel; /* TYPE_GRLIB specific */
    37. 

  37. };
    38. 

  38. 

  39. /* SPI Controller mode register definitions */
    40. 

  40. #define	SPMODE_LOOP		(1 << 30)
    41. 

  41. #define	SPMODE_CI_INACTIVEHIGH	(1 << 29)
    42. 

  42. #define	SPMODE_CP_BEGIN_EDGECLK	(1 << 28)
    43. 

  43. #define	SPMODE_DIV16		(1 << 27)
    44. 

  44. #define	SPMODE_REV		(1 << 26)
    45. 

  45. #define	SPMODE_MS		(1 << 25)
    46. 

  46. #define	SPMODE_ENABLE		(1 << 24)
    47. 

  47. #define	SPMODE_LEN(x)		((x) << 20)
    48. 

  48. #define	SPMODE_PM(x)		((x) << 16)
    49. 

  49. #define	SPMODE_OP		(1 << 14)
    50. 

  50. #define	SPMODE_CG(x)		((x) << 7)
    51. 

  51. 

  52. /* TYPE_GRLIB SPI Controller capability register definitions */
    53. 

  53. #define SPCAP_SSEN(x)		(((x) >> 16) & 0x1)
    54. 

  54. #define SPCAP_SSSZ(x)		(((x) >> 24) & 0xff)
    55. 

  55. #define SPCAP_MAXWLEN(x)	(((x) >> 20) & 0xf)
    56. 

  56. 

  57. /*
    58. 

  58.  * Default for SPI Mode:
    59. 

  59.  *	SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
    60. 

  60.  */
    61. 

  61. #define	SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
    62. 

  62. 			 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
    63. 

  63. 

  64. /* SPIE register values */
    65. 

  65. #define	SPIE_NE		0x00000200	/* Not empty */
    66. 

  66. #define	SPIE_NF		0x00000100	/* Not full */
    67. 

  67. 

  68. /* SPIM register values */
    69. 

  69. #define	SPIM_NE		0x00000200	/* Not empty */
    70. 

  70. #define	SPIM_NF		0x00000100	/* Not full */
    71. 

  71. 

  72. #endif /* __SPI_FSL_SPI_H__ */
    73. 

  73.