bnx2fc_hwi.c 62 KB

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  1. /* bnx2fc_hwi.c: QLogic Linux FCoE offload driver.
  2. * This file contains the code that low level functions that interact
  3. * with 57712 FCoE firmware.
  4. *
  5. * Copyright (c) 2008-2013 Broadcom Corporation
  6. * Copyright (c) 2014-2016 QLogic Corporation
  7. * Copyright (c) 2016-2017 Cavium Inc.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation.
  12. *
  13. * Written by: Bhanu Prakash Gollapudi (bprakash@broadcom.com)
  14. */
  15. #include "bnx2fc.h"
  16. DECLARE_PER_CPU(struct bnx2fc_percpu_s, bnx2fc_percpu);
  17. static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
  18. struct fcoe_kcqe *new_cqe_kcqe);
  19. static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
  20. struct fcoe_kcqe *ofld_kcqe);
  21. static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
  22. struct fcoe_kcqe *ofld_kcqe);
  23. static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code);
  24. static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
  25. struct fcoe_kcqe *destroy_kcqe);
  26. int bnx2fc_send_stat_req(struct bnx2fc_hba *hba)
  27. {
  28. struct fcoe_kwqe_stat stat_req;
  29. struct kwqe *kwqe_arr[2];
  30. int num_kwqes = 1;
  31. int rc = 0;
  32. memset(&stat_req, 0x00, sizeof(struct fcoe_kwqe_stat));
  33. stat_req.hdr.op_code = FCOE_KWQE_OPCODE_STAT;
  34. stat_req.hdr.flags =
  35. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  36. stat_req.stat_params_addr_lo = (u32) hba->stats_buf_dma;
  37. stat_req.stat_params_addr_hi = (u32) ((u64)hba->stats_buf_dma >> 32);
  38. kwqe_arr[0] = (struct kwqe *) &stat_req;
  39. if (hba->cnic && hba->cnic->submit_kwqes)
  40. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  41. return rc;
  42. }
  43. /**
  44. * bnx2fc_send_fw_fcoe_init_msg - initiates initial handshake with FCoE f/w
  45. *
  46. * @hba: adapter structure pointer
  47. *
  48. * Send down FCoE firmware init KWQEs which initiates the initial handshake
  49. * with the f/w.
  50. *
  51. */
  52. int bnx2fc_send_fw_fcoe_init_msg(struct bnx2fc_hba *hba)
  53. {
  54. struct fcoe_kwqe_init1 fcoe_init1;
  55. struct fcoe_kwqe_init2 fcoe_init2;
  56. struct fcoe_kwqe_init3 fcoe_init3;
  57. struct kwqe *kwqe_arr[3];
  58. int num_kwqes = 3;
  59. int rc = 0;
  60. if (!hba->cnic) {
  61. printk(KERN_ERR PFX "hba->cnic NULL during fcoe fw init\n");
  62. return -ENODEV;
  63. }
  64. /* fill init1 KWQE */
  65. memset(&fcoe_init1, 0x00, sizeof(struct fcoe_kwqe_init1));
  66. fcoe_init1.hdr.op_code = FCOE_KWQE_OPCODE_INIT1;
  67. fcoe_init1.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  68. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  69. fcoe_init1.num_tasks = hba->max_tasks;
  70. fcoe_init1.sq_num_wqes = BNX2FC_SQ_WQES_MAX;
  71. fcoe_init1.rq_num_wqes = BNX2FC_RQ_WQES_MAX;
  72. fcoe_init1.rq_buffer_log_size = BNX2FC_RQ_BUF_LOG_SZ;
  73. fcoe_init1.cq_num_wqes = BNX2FC_CQ_WQES_MAX;
  74. fcoe_init1.dummy_buffer_addr_lo = (u32) hba->dummy_buf_dma;
  75. fcoe_init1.dummy_buffer_addr_hi = (u32) ((u64)hba->dummy_buf_dma >> 32);
  76. fcoe_init1.task_list_pbl_addr_lo = (u32) hba->task_ctx_bd_dma;
  77. fcoe_init1.task_list_pbl_addr_hi =
  78. (u32) ((u64) hba->task_ctx_bd_dma >> 32);
  79. fcoe_init1.mtu = BNX2FC_MINI_JUMBO_MTU;
  80. fcoe_init1.flags = (PAGE_SHIFT <<
  81. FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT);
  82. fcoe_init1.num_sessions_log = BNX2FC_NUM_MAX_SESS_LOG;
  83. /* fill init2 KWQE */
  84. memset(&fcoe_init2, 0x00, sizeof(struct fcoe_kwqe_init2));
  85. fcoe_init2.hdr.op_code = FCOE_KWQE_OPCODE_INIT2;
  86. fcoe_init2.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  87. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  88. fcoe_init2.hsi_major_version = FCOE_HSI_MAJOR_VERSION;
  89. fcoe_init2.hsi_minor_version = FCOE_HSI_MINOR_VERSION;
  90. fcoe_init2.hash_tbl_pbl_addr_lo = (u32) hba->hash_tbl_pbl_dma;
  91. fcoe_init2.hash_tbl_pbl_addr_hi = (u32)
  92. ((u64) hba->hash_tbl_pbl_dma >> 32);
  93. fcoe_init2.t2_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_dma;
  94. fcoe_init2.t2_hash_tbl_addr_hi = (u32)
  95. ((u64) hba->t2_hash_tbl_dma >> 32);
  96. fcoe_init2.t2_ptr_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_ptr_dma;
  97. fcoe_init2.t2_ptr_hash_tbl_addr_hi = (u32)
  98. ((u64) hba->t2_hash_tbl_ptr_dma >> 32);
  99. fcoe_init2.free_list_count = BNX2FC_NUM_MAX_SESS;
  100. /* fill init3 KWQE */
  101. memset(&fcoe_init3, 0x00, sizeof(struct fcoe_kwqe_init3));
  102. fcoe_init3.hdr.op_code = FCOE_KWQE_OPCODE_INIT3;
  103. fcoe_init3.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  104. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  105. fcoe_init3.error_bit_map_lo = 0xffffffff;
  106. fcoe_init3.error_bit_map_hi = 0xffffffff;
  107. /*
  108. * enable both cached connection and cached tasks
  109. * 0 = none, 1 = cached connection, 2 = cached tasks, 3 = both
  110. */
  111. fcoe_init3.perf_config = 3;
  112. kwqe_arr[0] = (struct kwqe *) &fcoe_init1;
  113. kwqe_arr[1] = (struct kwqe *) &fcoe_init2;
  114. kwqe_arr[2] = (struct kwqe *) &fcoe_init3;
  115. if (hba->cnic && hba->cnic->submit_kwqes)
  116. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  117. return rc;
  118. }
  119. int bnx2fc_send_fw_fcoe_destroy_msg(struct bnx2fc_hba *hba)
  120. {
  121. struct fcoe_kwqe_destroy fcoe_destroy;
  122. struct kwqe *kwqe_arr[2];
  123. int num_kwqes = 1;
  124. int rc = -1;
  125. /* fill destroy KWQE */
  126. memset(&fcoe_destroy, 0x00, sizeof(struct fcoe_kwqe_destroy));
  127. fcoe_destroy.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY;
  128. fcoe_destroy.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  129. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  130. kwqe_arr[0] = (struct kwqe *) &fcoe_destroy;
  131. if (hba->cnic && hba->cnic->submit_kwqes)
  132. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  133. return rc;
  134. }
  135. /**
  136. * bnx2fc_send_session_ofld_req - initiates FCoE Session offload process
  137. *
  138. * @port: port structure pointer
  139. * @tgt: bnx2fc_rport structure pointer
  140. */
  141. int bnx2fc_send_session_ofld_req(struct fcoe_port *port,
  142. struct bnx2fc_rport *tgt)
  143. {
  144. struct fc_lport *lport = port->lport;
  145. struct bnx2fc_interface *interface = port->priv;
  146. struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface);
  147. struct bnx2fc_hba *hba = interface->hba;
  148. struct kwqe *kwqe_arr[4];
  149. struct fcoe_kwqe_conn_offload1 ofld_req1;
  150. struct fcoe_kwqe_conn_offload2 ofld_req2;
  151. struct fcoe_kwqe_conn_offload3 ofld_req3;
  152. struct fcoe_kwqe_conn_offload4 ofld_req4;
  153. struct fc_rport_priv *rdata = tgt->rdata;
  154. struct fc_rport *rport = tgt->rport;
  155. int num_kwqes = 4;
  156. u32 port_id;
  157. int rc = 0;
  158. u16 conn_id;
  159. /* Initialize offload request 1 structure */
  160. memset(&ofld_req1, 0x00, sizeof(struct fcoe_kwqe_conn_offload1));
  161. ofld_req1.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN1;
  162. ofld_req1.hdr.flags =
  163. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  164. conn_id = (u16)tgt->fcoe_conn_id;
  165. ofld_req1.fcoe_conn_id = conn_id;
  166. ofld_req1.sq_addr_lo = (u32) tgt->sq_dma;
  167. ofld_req1.sq_addr_hi = (u32)((u64) tgt->sq_dma >> 32);
  168. ofld_req1.rq_pbl_addr_lo = (u32) tgt->rq_pbl_dma;
  169. ofld_req1.rq_pbl_addr_hi = (u32)((u64) tgt->rq_pbl_dma >> 32);
  170. ofld_req1.rq_first_pbe_addr_lo = (u32) tgt->rq_dma;
  171. ofld_req1.rq_first_pbe_addr_hi =
  172. (u32)((u64) tgt->rq_dma >> 32);
  173. ofld_req1.rq_prod = 0x8000;
  174. /* Initialize offload request 2 structure */
  175. memset(&ofld_req2, 0x00, sizeof(struct fcoe_kwqe_conn_offload2));
  176. ofld_req2.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN2;
  177. ofld_req2.hdr.flags =
  178. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  179. ofld_req2.tx_max_fc_pay_len = rdata->maxframe_size;
  180. ofld_req2.cq_addr_lo = (u32) tgt->cq_dma;
  181. ofld_req2.cq_addr_hi = (u32)((u64)tgt->cq_dma >> 32);
  182. ofld_req2.xferq_addr_lo = (u32) tgt->xferq_dma;
  183. ofld_req2.xferq_addr_hi = (u32)((u64)tgt->xferq_dma >> 32);
  184. ofld_req2.conn_db_addr_lo = (u32)tgt->conn_db_dma;
  185. ofld_req2.conn_db_addr_hi = (u32)((u64)tgt->conn_db_dma >> 32);
  186. /* Initialize offload request 3 structure */
  187. memset(&ofld_req3, 0x00, sizeof(struct fcoe_kwqe_conn_offload3));
  188. ofld_req3.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN3;
  189. ofld_req3.hdr.flags =
  190. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  191. ofld_req3.vlan_tag = interface->vlan_id <<
  192. FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT;
  193. ofld_req3.vlan_tag |= 3 << FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT;
  194. port_id = fc_host_port_id(lport->host);
  195. if (port_id == 0) {
  196. BNX2FC_HBA_DBG(lport, "ofld_req: port_id = 0, link down?\n");
  197. return -EINVAL;
  198. }
  199. /*
  200. * Store s_id of the initiator for further reference. This will
  201. * be used during disable/destroy during linkdown processing as
  202. * when the lport is reset, the port_id also is reset to 0
  203. */
  204. tgt->sid = port_id;
  205. ofld_req3.s_id[0] = (port_id & 0x000000FF);
  206. ofld_req3.s_id[1] = (port_id & 0x0000FF00) >> 8;
  207. ofld_req3.s_id[2] = (port_id & 0x00FF0000) >> 16;
  208. port_id = rport->port_id;
  209. ofld_req3.d_id[0] = (port_id & 0x000000FF);
  210. ofld_req3.d_id[1] = (port_id & 0x0000FF00) >> 8;
  211. ofld_req3.d_id[2] = (port_id & 0x00FF0000) >> 16;
  212. ofld_req3.tx_total_conc_seqs = rdata->max_seq;
  213. ofld_req3.tx_max_conc_seqs_c3 = rdata->max_seq;
  214. ofld_req3.rx_max_fc_pay_len = lport->mfs;
  215. ofld_req3.rx_total_conc_seqs = BNX2FC_MAX_SEQS;
  216. ofld_req3.rx_max_conc_seqs_c3 = BNX2FC_MAX_SEQS;
  217. ofld_req3.rx_open_seqs_exch_c3 = 1;
  218. ofld_req3.confq_first_pbe_addr_lo = tgt->confq_dma;
  219. ofld_req3.confq_first_pbe_addr_hi = (u32)((u64) tgt->confq_dma >> 32);
  220. /* set mul_n_port_ids supported flag to 0, until it is supported */
  221. ofld_req3.flags = 0;
  222. /*
  223. ofld_req3.flags |= (((lport->send_sp_features & FC_SP_FT_MNA) ? 1:0) <<
  224. FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT);
  225. */
  226. /* Info from PLOGI response */
  227. ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_EDTR) ? 1 : 0) <<
  228. FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT);
  229. ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_SEQC) ? 1 : 0) <<
  230. FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT);
  231. /*
  232. * Info from PRLI response, this info is used for sequence level error
  233. * recovery support
  234. */
  235. if (tgt->dev_type == TYPE_TAPE) {
  236. ofld_req3.flags |= 1 <<
  237. FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT;
  238. ofld_req3.flags |= (((rdata->flags & FC_RP_FLAGS_REC_SUPPORTED)
  239. ? 1 : 0) <<
  240. FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT);
  241. }
  242. /* vlan flag */
  243. ofld_req3.flags |= (interface->vlan_enabled <<
  244. FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT);
  245. /* C2_VALID and ACK flags are not set as they are not supported */
  246. /* Initialize offload request 4 structure */
  247. memset(&ofld_req4, 0x00, sizeof(struct fcoe_kwqe_conn_offload4));
  248. ofld_req4.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN4;
  249. ofld_req4.hdr.flags =
  250. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  251. ofld_req4.e_d_tov_timer_val = lport->e_d_tov / 20;
  252. ofld_req4.src_mac_addr_lo[0] = port->data_src_addr[5];
  253. /* local mac */
  254. ofld_req4.src_mac_addr_lo[1] = port->data_src_addr[4];
  255. ofld_req4.src_mac_addr_mid[0] = port->data_src_addr[3];
  256. ofld_req4.src_mac_addr_mid[1] = port->data_src_addr[2];
  257. ofld_req4.src_mac_addr_hi[0] = port->data_src_addr[1];
  258. ofld_req4.src_mac_addr_hi[1] = port->data_src_addr[0];
  259. ofld_req4.dst_mac_addr_lo[0] = ctlr->dest_addr[5];
  260. /* fcf mac */
  261. ofld_req4.dst_mac_addr_lo[1] = ctlr->dest_addr[4];
  262. ofld_req4.dst_mac_addr_mid[0] = ctlr->dest_addr[3];
  263. ofld_req4.dst_mac_addr_mid[1] = ctlr->dest_addr[2];
  264. ofld_req4.dst_mac_addr_hi[0] = ctlr->dest_addr[1];
  265. ofld_req4.dst_mac_addr_hi[1] = ctlr->dest_addr[0];
  266. ofld_req4.lcq_addr_lo = (u32) tgt->lcq_dma;
  267. ofld_req4.lcq_addr_hi = (u32)((u64) tgt->lcq_dma >> 32);
  268. ofld_req4.confq_pbl_base_addr_lo = (u32) tgt->confq_pbl_dma;
  269. ofld_req4.confq_pbl_base_addr_hi =
  270. (u32)((u64) tgt->confq_pbl_dma >> 32);
  271. kwqe_arr[0] = (struct kwqe *) &ofld_req1;
  272. kwqe_arr[1] = (struct kwqe *) &ofld_req2;
  273. kwqe_arr[2] = (struct kwqe *) &ofld_req3;
  274. kwqe_arr[3] = (struct kwqe *) &ofld_req4;
  275. if (hba->cnic && hba->cnic->submit_kwqes)
  276. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  277. return rc;
  278. }
  279. /**
  280. * bnx2fc_send_session_enable_req - initiates FCoE Session enablement
  281. *
  282. * @port: port structure pointer
  283. * @tgt: bnx2fc_rport structure pointer
  284. */
  285. int bnx2fc_send_session_enable_req(struct fcoe_port *port,
  286. struct bnx2fc_rport *tgt)
  287. {
  288. struct kwqe *kwqe_arr[2];
  289. struct bnx2fc_interface *interface = port->priv;
  290. struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface);
  291. struct bnx2fc_hba *hba = interface->hba;
  292. struct fcoe_kwqe_conn_enable_disable enbl_req;
  293. struct fc_lport *lport = port->lport;
  294. struct fc_rport *rport = tgt->rport;
  295. int num_kwqes = 1;
  296. int rc = 0;
  297. u32 port_id;
  298. memset(&enbl_req, 0x00,
  299. sizeof(struct fcoe_kwqe_conn_enable_disable));
  300. enbl_req.hdr.op_code = FCOE_KWQE_OPCODE_ENABLE_CONN;
  301. enbl_req.hdr.flags =
  302. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  303. enbl_req.src_mac_addr_lo[0] = port->data_src_addr[5];
  304. /* local mac */
  305. enbl_req.src_mac_addr_lo[1] = port->data_src_addr[4];
  306. enbl_req.src_mac_addr_mid[0] = port->data_src_addr[3];
  307. enbl_req.src_mac_addr_mid[1] = port->data_src_addr[2];
  308. enbl_req.src_mac_addr_hi[0] = port->data_src_addr[1];
  309. enbl_req.src_mac_addr_hi[1] = port->data_src_addr[0];
  310. memcpy(tgt->src_addr, port->data_src_addr, ETH_ALEN);
  311. enbl_req.dst_mac_addr_lo[0] = ctlr->dest_addr[5];
  312. enbl_req.dst_mac_addr_lo[1] = ctlr->dest_addr[4];
  313. enbl_req.dst_mac_addr_mid[0] = ctlr->dest_addr[3];
  314. enbl_req.dst_mac_addr_mid[1] = ctlr->dest_addr[2];
  315. enbl_req.dst_mac_addr_hi[0] = ctlr->dest_addr[1];
  316. enbl_req.dst_mac_addr_hi[1] = ctlr->dest_addr[0];
  317. port_id = fc_host_port_id(lport->host);
  318. if (port_id != tgt->sid) {
  319. printk(KERN_ERR PFX "WARN: enable_req port_id = 0x%x,"
  320. "sid = 0x%x\n", port_id, tgt->sid);
  321. port_id = tgt->sid;
  322. }
  323. enbl_req.s_id[0] = (port_id & 0x000000FF);
  324. enbl_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
  325. enbl_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
  326. port_id = rport->port_id;
  327. enbl_req.d_id[0] = (port_id & 0x000000FF);
  328. enbl_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
  329. enbl_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
  330. enbl_req.vlan_tag = interface->vlan_id <<
  331. FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
  332. enbl_req.vlan_tag |= 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
  333. enbl_req.vlan_flag = interface->vlan_enabled;
  334. enbl_req.context_id = tgt->context_id;
  335. enbl_req.conn_id = tgt->fcoe_conn_id;
  336. kwqe_arr[0] = (struct kwqe *) &enbl_req;
  337. if (hba->cnic && hba->cnic->submit_kwqes)
  338. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  339. return rc;
  340. }
  341. /**
  342. * bnx2fc_send_session_disable_req - initiates FCoE Session disable
  343. *
  344. * @port: port structure pointer
  345. * @tgt: bnx2fc_rport structure pointer
  346. */
  347. int bnx2fc_send_session_disable_req(struct fcoe_port *port,
  348. struct bnx2fc_rport *tgt)
  349. {
  350. struct bnx2fc_interface *interface = port->priv;
  351. struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface);
  352. struct bnx2fc_hba *hba = interface->hba;
  353. struct fcoe_kwqe_conn_enable_disable disable_req;
  354. struct kwqe *kwqe_arr[2];
  355. struct fc_rport *rport = tgt->rport;
  356. int num_kwqes = 1;
  357. int rc = 0;
  358. u32 port_id;
  359. memset(&disable_req, 0x00,
  360. sizeof(struct fcoe_kwqe_conn_enable_disable));
  361. disable_req.hdr.op_code = FCOE_KWQE_OPCODE_DISABLE_CONN;
  362. disable_req.hdr.flags =
  363. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  364. disable_req.src_mac_addr_lo[0] = tgt->src_addr[5];
  365. disable_req.src_mac_addr_lo[1] = tgt->src_addr[4];
  366. disable_req.src_mac_addr_mid[0] = tgt->src_addr[3];
  367. disable_req.src_mac_addr_mid[1] = tgt->src_addr[2];
  368. disable_req.src_mac_addr_hi[0] = tgt->src_addr[1];
  369. disable_req.src_mac_addr_hi[1] = tgt->src_addr[0];
  370. disable_req.dst_mac_addr_lo[0] = ctlr->dest_addr[5];
  371. disable_req.dst_mac_addr_lo[1] = ctlr->dest_addr[4];
  372. disable_req.dst_mac_addr_mid[0] = ctlr->dest_addr[3];
  373. disable_req.dst_mac_addr_mid[1] = ctlr->dest_addr[2];
  374. disable_req.dst_mac_addr_hi[0] = ctlr->dest_addr[1];
  375. disable_req.dst_mac_addr_hi[1] = ctlr->dest_addr[0];
  376. port_id = tgt->sid;
  377. disable_req.s_id[0] = (port_id & 0x000000FF);
  378. disable_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
  379. disable_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
  380. port_id = rport->port_id;
  381. disable_req.d_id[0] = (port_id & 0x000000FF);
  382. disable_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
  383. disable_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
  384. disable_req.context_id = tgt->context_id;
  385. disable_req.conn_id = tgt->fcoe_conn_id;
  386. disable_req.vlan_tag = interface->vlan_id <<
  387. FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
  388. disable_req.vlan_tag |=
  389. 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
  390. disable_req.vlan_flag = interface->vlan_enabled;
  391. kwqe_arr[0] = (struct kwqe *) &disable_req;
  392. if (hba->cnic && hba->cnic->submit_kwqes)
  393. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  394. return rc;
  395. }
  396. /**
  397. * bnx2fc_send_session_destroy_req - initiates FCoE Session destroy
  398. *
  399. * @port: port structure pointer
  400. * @tgt: bnx2fc_rport structure pointer
  401. */
  402. int bnx2fc_send_session_destroy_req(struct bnx2fc_hba *hba,
  403. struct bnx2fc_rport *tgt)
  404. {
  405. struct fcoe_kwqe_conn_destroy destroy_req;
  406. struct kwqe *kwqe_arr[2];
  407. int num_kwqes = 1;
  408. int rc = 0;
  409. memset(&destroy_req, 0x00, sizeof(struct fcoe_kwqe_conn_destroy));
  410. destroy_req.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY_CONN;
  411. destroy_req.hdr.flags =
  412. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  413. destroy_req.context_id = tgt->context_id;
  414. destroy_req.conn_id = tgt->fcoe_conn_id;
  415. kwqe_arr[0] = (struct kwqe *) &destroy_req;
  416. if (hba->cnic && hba->cnic->submit_kwqes)
  417. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  418. return rc;
  419. }
  420. static bool is_valid_lport(struct bnx2fc_hba *hba, struct fc_lport *lport)
  421. {
  422. struct bnx2fc_lport *blport;
  423. spin_lock_bh(&hba->hba_lock);
  424. list_for_each_entry(blport, &hba->vports, list) {
  425. if (blport->lport == lport) {
  426. spin_unlock_bh(&hba->hba_lock);
  427. return true;
  428. }
  429. }
  430. spin_unlock_bh(&hba->hba_lock);
  431. return false;
  432. }
  433. static void bnx2fc_unsol_els_work(struct work_struct *work)
  434. {
  435. struct bnx2fc_unsol_els *unsol_els;
  436. struct fc_lport *lport;
  437. struct bnx2fc_hba *hba;
  438. struct fc_frame *fp;
  439. unsol_els = container_of(work, struct bnx2fc_unsol_els, unsol_els_work);
  440. lport = unsol_els->lport;
  441. fp = unsol_els->fp;
  442. hba = unsol_els->hba;
  443. if (is_valid_lport(hba, lport))
  444. fc_exch_recv(lport, fp);
  445. kfree(unsol_els);
  446. }
  447. void bnx2fc_process_l2_frame_compl(struct bnx2fc_rport *tgt,
  448. unsigned char *buf,
  449. u32 frame_len, u16 l2_oxid)
  450. {
  451. struct fcoe_port *port = tgt->port;
  452. struct fc_lport *lport = port->lport;
  453. struct bnx2fc_interface *interface = port->priv;
  454. struct bnx2fc_unsol_els *unsol_els;
  455. struct fc_frame_header *fh;
  456. struct fc_frame *fp;
  457. struct sk_buff *skb;
  458. u32 payload_len;
  459. u32 crc;
  460. u8 op;
  461. unsol_els = kzalloc(sizeof(*unsol_els), GFP_ATOMIC);
  462. if (!unsol_els) {
  463. BNX2FC_TGT_DBG(tgt, "Unable to allocate unsol_work\n");
  464. return;
  465. }
  466. BNX2FC_TGT_DBG(tgt, "l2_frame_compl l2_oxid = 0x%x, frame_len = %d\n",
  467. l2_oxid, frame_len);
  468. payload_len = frame_len - sizeof(struct fc_frame_header);
  469. fp = fc_frame_alloc(lport, payload_len);
  470. if (!fp) {
  471. printk(KERN_ERR PFX "fc_frame_alloc failure\n");
  472. kfree(unsol_els);
  473. return;
  474. }
  475. fh = (struct fc_frame_header *) fc_frame_header_get(fp);
  476. /* Copy FC Frame header and payload into the frame */
  477. memcpy(fh, buf, frame_len);
  478. if (l2_oxid != FC_XID_UNKNOWN)
  479. fh->fh_ox_id = htons(l2_oxid);
  480. skb = fp_skb(fp);
  481. if ((fh->fh_r_ctl == FC_RCTL_ELS_REQ) ||
  482. (fh->fh_r_ctl == FC_RCTL_ELS_REP)) {
  483. if (fh->fh_type == FC_TYPE_ELS) {
  484. op = fc_frame_payload_op(fp);
  485. if ((op == ELS_TEST) || (op == ELS_ESTC) ||
  486. (op == ELS_FAN) || (op == ELS_CSU)) {
  487. /*
  488. * No need to reply for these
  489. * ELS requests
  490. */
  491. printk(KERN_ERR PFX "dropping ELS 0x%x\n", op);
  492. kfree_skb(skb);
  493. kfree(unsol_els);
  494. return;
  495. }
  496. }
  497. crc = fcoe_fc_crc(fp);
  498. fc_frame_init(fp);
  499. fr_dev(fp) = lport;
  500. fr_sof(fp) = FC_SOF_I3;
  501. fr_eof(fp) = FC_EOF_T;
  502. fr_crc(fp) = cpu_to_le32(~crc);
  503. unsol_els->lport = lport;
  504. unsol_els->hba = interface->hba;
  505. unsol_els->fp = fp;
  506. INIT_WORK(&unsol_els->unsol_els_work, bnx2fc_unsol_els_work);
  507. queue_work(bnx2fc_wq, &unsol_els->unsol_els_work);
  508. } else {
  509. BNX2FC_HBA_DBG(lport, "fh_r_ctl = 0x%x\n", fh->fh_r_ctl);
  510. kfree_skb(skb);
  511. kfree(unsol_els);
  512. }
  513. }
  514. static void bnx2fc_process_unsol_compl(struct bnx2fc_rport *tgt, u16 wqe)
  515. {
  516. u8 num_rq;
  517. struct fcoe_err_report_entry *err_entry;
  518. unsigned char *rq_data;
  519. unsigned char *buf = NULL, *buf1;
  520. int i;
  521. u16 xid;
  522. u32 frame_len, len;
  523. struct bnx2fc_cmd *io_req = NULL;
  524. struct fcoe_task_ctx_entry *task, *task_page;
  525. struct bnx2fc_interface *interface = tgt->port->priv;
  526. struct bnx2fc_hba *hba = interface->hba;
  527. int task_idx, index;
  528. int rc = 0;
  529. u64 err_warn_bit_map;
  530. u8 err_warn = 0xff;
  531. BNX2FC_TGT_DBG(tgt, "Entered UNSOL COMPLETION wqe = 0x%x\n", wqe);
  532. switch (wqe & FCOE_UNSOLICITED_CQE_SUBTYPE) {
  533. case FCOE_UNSOLICITED_FRAME_CQE_TYPE:
  534. frame_len = (wqe & FCOE_UNSOLICITED_CQE_PKT_LEN) >>
  535. FCOE_UNSOLICITED_CQE_PKT_LEN_SHIFT;
  536. num_rq = (frame_len + BNX2FC_RQ_BUF_SZ - 1) / BNX2FC_RQ_BUF_SZ;
  537. spin_lock_bh(&tgt->tgt_lock);
  538. rq_data = (unsigned char *)bnx2fc_get_next_rqe(tgt, num_rq);
  539. spin_unlock_bh(&tgt->tgt_lock);
  540. if (rq_data) {
  541. buf = rq_data;
  542. } else {
  543. buf1 = buf = kmalloc((num_rq * BNX2FC_RQ_BUF_SZ),
  544. GFP_ATOMIC);
  545. if (!buf1) {
  546. BNX2FC_TGT_DBG(tgt, "Memory alloc failure\n");
  547. break;
  548. }
  549. for (i = 0; i < num_rq; i++) {
  550. spin_lock_bh(&tgt->tgt_lock);
  551. rq_data = (unsigned char *)
  552. bnx2fc_get_next_rqe(tgt, 1);
  553. spin_unlock_bh(&tgt->tgt_lock);
  554. len = BNX2FC_RQ_BUF_SZ;
  555. memcpy(buf1, rq_data, len);
  556. buf1 += len;
  557. }
  558. }
  559. bnx2fc_process_l2_frame_compl(tgt, buf, frame_len,
  560. FC_XID_UNKNOWN);
  561. if (buf != rq_data)
  562. kfree(buf);
  563. spin_lock_bh(&tgt->tgt_lock);
  564. bnx2fc_return_rqe(tgt, num_rq);
  565. spin_unlock_bh(&tgt->tgt_lock);
  566. break;
  567. case FCOE_ERROR_DETECTION_CQE_TYPE:
  568. /*
  569. * In case of error reporting CQE a single RQ entry
  570. * is consumed.
  571. */
  572. spin_lock_bh(&tgt->tgt_lock);
  573. num_rq = 1;
  574. err_entry = (struct fcoe_err_report_entry *)
  575. bnx2fc_get_next_rqe(tgt, 1);
  576. xid = err_entry->fc_hdr.ox_id;
  577. BNX2FC_TGT_DBG(tgt, "Unsol Error Frame OX_ID = 0x%x\n", xid);
  578. BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x\n",
  579. err_entry->data.err_warn_bitmap_hi,
  580. err_entry->data.err_warn_bitmap_lo);
  581. BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x\n",
  582. err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
  583. if (xid > hba->max_xid) {
  584. BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n",
  585. xid);
  586. goto ret_err_rqe;
  587. }
  588. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  589. index = xid % BNX2FC_TASKS_PER_PAGE;
  590. task_page = (struct fcoe_task_ctx_entry *)
  591. hba->task_ctx[task_idx];
  592. task = &(task_page[index]);
  593. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  594. if (!io_req)
  595. goto ret_err_rqe;
  596. if (io_req->cmd_type != BNX2FC_SCSI_CMD) {
  597. printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n");
  598. goto ret_err_rqe;
  599. }
  600. if (test_and_clear_bit(BNX2FC_FLAG_IO_CLEANUP,
  601. &io_req->req_flags)) {
  602. BNX2FC_IO_DBG(io_req, "unsol_err: cleanup in "
  603. "progress.. ignore unsol err\n");
  604. goto ret_err_rqe;
  605. }
  606. err_warn_bit_map = (u64)
  607. ((u64)err_entry->data.err_warn_bitmap_hi << 32) |
  608. (u64)err_entry->data.err_warn_bitmap_lo;
  609. for (i = 0; i < BNX2FC_NUM_ERR_BITS; i++) {
  610. if (err_warn_bit_map & (u64)((u64)1 << i)) {
  611. err_warn = i;
  612. break;
  613. }
  614. }
  615. /*
  616. * If ABTS is already in progress, and FW error is
  617. * received after that, do not cancel the timeout_work
  618. * and let the error recovery continue by explicitly
  619. * logging out the target, when the ABTS eventually
  620. * times out.
  621. */
  622. if (test_bit(BNX2FC_FLAG_ISSUE_ABTS, &io_req->req_flags)) {
  623. printk(KERN_ERR PFX "err_warn: io_req (0x%x) already "
  624. "in ABTS processing\n", xid);
  625. goto ret_err_rqe;
  626. }
  627. BNX2FC_TGT_DBG(tgt, "err = 0x%x\n", err_warn);
  628. if (tgt->dev_type != TYPE_TAPE)
  629. goto skip_rec;
  630. switch (err_warn) {
  631. case FCOE_ERROR_CODE_REC_TOV_TIMER_EXPIRATION:
  632. case FCOE_ERROR_CODE_DATA_OOO_RO:
  633. case FCOE_ERROR_CODE_COMMON_INCORRECT_SEQ_CNT:
  634. case FCOE_ERROR_CODE_DATA_SOFI3_SEQ_ACTIVE_SET:
  635. case FCOE_ERROR_CODE_FCP_RSP_OPENED_SEQ:
  636. case FCOE_ERROR_CODE_DATA_SOFN_SEQ_ACTIVE_RESET:
  637. BNX2FC_TGT_DBG(tgt, "REC TOV popped for xid - 0x%x\n",
  638. xid);
  639. memcpy(&io_req->err_entry, err_entry,
  640. sizeof(struct fcoe_err_report_entry));
  641. if (!test_bit(BNX2FC_FLAG_SRR_SENT,
  642. &io_req->req_flags)) {
  643. spin_unlock_bh(&tgt->tgt_lock);
  644. rc = bnx2fc_send_rec(io_req);
  645. spin_lock_bh(&tgt->tgt_lock);
  646. if (rc)
  647. goto skip_rec;
  648. } else
  649. printk(KERN_ERR PFX "SRR in progress\n");
  650. goto ret_err_rqe;
  651. break;
  652. default:
  653. break;
  654. }
  655. skip_rec:
  656. set_bit(BNX2FC_FLAG_ISSUE_ABTS, &io_req->req_flags);
  657. /*
  658. * Cancel the timeout_work, as we received IO
  659. * completion with FW error.
  660. */
  661. if (cancel_delayed_work(&io_req->timeout_work))
  662. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  663. rc = bnx2fc_initiate_abts(io_req);
  664. if (rc != SUCCESS) {
  665. printk(KERN_ERR PFX "err_warn: initiate_abts "
  666. "failed xid = 0x%x. issue cleanup\n",
  667. io_req->xid);
  668. bnx2fc_initiate_cleanup(io_req);
  669. }
  670. ret_err_rqe:
  671. bnx2fc_return_rqe(tgt, 1);
  672. spin_unlock_bh(&tgt->tgt_lock);
  673. break;
  674. case FCOE_WARNING_DETECTION_CQE_TYPE:
  675. /*
  676. *In case of warning reporting CQE a single RQ entry
  677. * is consumes.
  678. */
  679. spin_lock_bh(&tgt->tgt_lock);
  680. num_rq = 1;
  681. err_entry = (struct fcoe_err_report_entry *)
  682. bnx2fc_get_next_rqe(tgt, 1);
  683. xid = cpu_to_be16(err_entry->fc_hdr.ox_id);
  684. BNX2FC_TGT_DBG(tgt, "Unsol Warning Frame OX_ID = 0x%x\n", xid);
  685. BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x",
  686. err_entry->data.err_warn_bitmap_hi,
  687. err_entry->data.err_warn_bitmap_lo);
  688. BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x",
  689. err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
  690. if (xid > hba->max_xid) {
  691. BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n", xid);
  692. goto ret_warn_rqe;
  693. }
  694. err_warn_bit_map = (u64)
  695. ((u64)err_entry->data.err_warn_bitmap_hi << 32) |
  696. (u64)err_entry->data.err_warn_bitmap_lo;
  697. for (i = 0; i < BNX2FC_NUM_ERR_BITS; i++) {
  698. if (err_warn_bit_map & ((u64)1 << i)) {
  699. err_warn = i;
  700. break;
  701. }
  702. }
  703. BNX2FC_TGT_DBG(tgt, "warn = 0x%x\n", err_warn);
  704. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  705. index = xid % BNX2FC_TASKS_PER_PAGE;
  706. task_page = (struct fcoe_task_ctx_entry *)
  707. interface->hba->task_ctx[task_idx];
  708. task = &(task_page[index]);
  709. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  710. if (!io_req)
  711. goto ret_warn_rqe;
  712. if (io_req->cmd_type != BNX2FC_SCSI_CMD) {
  713. printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n");
  714. goto ret_warn_rqe;
  715. }
  716. memcpy(&io_req->err_entry, err_entry,
  717. sizeof(struct fcoe_err_report_entry));
  718. if (err_warn == FCOE_ERROR_CODE_REC_TOV_TIMER_EXPIRATION)
  719. /* REC_TOV is not a warning code */
  720. BUG_ON(1);
  721. else
  722. BNX2FC_TGT_DBG(tgt, "Unsolicited warning\n");
  723. ret_warn_rqe:
  724. bnx2fc_return_rqe(tgt, 1);
  725. spin_unlock_bh(&tgt->tgt_lock);
  726. break;
  727. default:
  728. printk(KERN_ERR PFX "Unsol Compl: Invalid CQE Subtype\n");
  729. break;
  730. }
  731. }
  732. void bnx2fc_process_cq_compl(struct bnx2fc_rport *tgt, u16 wqe)
  733. {
  734. struct fcoe_task_ctx_entry *task;
  735. struct fcoe_task_ctx_entry *task_page;
  736. struct fcoe_port *port = tgt->port;
  737. struct bnx2fc_interface *interface = port->priv;
  738. struct bnx2fc_hba *hba = interface->hba;
  739. struct bnx2fc_cmd *io_req;
  740. int task_idx, index;
  741. u16 xid;
  742. u8 cmd_type;
  743. u8 rx_state = 0;
  744. u8 num_rq;
  745. spin_lock_bh(&tgt->tgt_lock);
  746. xid = wqe & FCOE_PEND_WQ_CQE_TASK_ID;
  747. if (xid >= hba->max_tasks) {
  748. printk(KERN_ERR PFX "ERROR:xid out of range\n");
  749. spin_unlock_bh(&tgt->tgt_lock);
  750. return;
  751. }
  752. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  753. index = xid % BNX2FC_TASKS_PER_PAGE;
  754. task_page = (struct fcoe_task_ctx_entry *)hba->task_ctx[task_idx];
  755. task = &(task_page[index]);
  756. num_rq = ((task->rxwr_txrd.var_ctx.rx_flags &
  757. FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE) >>
  758. FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT);
  759. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  760. if (io_req == NULL) {
  761. printk(KERN_ERR PFX "ERROR? cq_compl - io_req is NULL\n");
  762. spin_unlock_bh(&tgt->tgt_lock);
  763. return;
  764. }
  765. /* Timestamp IO completion time */
  766. cmd_type = io_req->cmd_type;
  767. rx_state = ((task->rxwr_txrd.var_ctx.rx_flags &
  768. FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE) >>
  769. FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT);
  770. /* Process other IO completion types */
  771. switch (cmd_type) {
  772. case BNX2FC_SCSI_CMD:
  773. if (rx_state == FCOE_TASK_RX_STATE_COMPLETED) {
  774. bnx2fc_process_scsi_cmd_compl(io_req, task, num_rq);
  775. spin_unlock_bh(&tgt->tgt_lock);
  776. return;
  777. }
  778. if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
  779. bnx2fc_process_abts_compl(io_req, task, num_rq);
  780. else if (rx_state ==
  781. FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
  782. bnx2fc_process_cleanup_compl(io_req, task, num_rq);
  783. else
  784. printk(KERN_ERR PFX "Invalid rx state - %d\n",
  785. rx_state);
  786. break;
  787. case BNX2FC_TASK_MGMT_CMD:
  788. BNX2FC_IO_DBG(io_req, "Processing TM complete\n");
  789. bnx2fc_process_tm_compl(io_req, task, num_rq);
  790. break;
  791. case BNX2FC_ABTS:
  792. /*
  793. * ABTS request received by firmware. ABTS response
  794. * will be delivered to the task belonging to the IO
  795. * that was aborted
  796. */
  797. BNX2FC_IO_DBG(io_req, "cq_compl- ABTS sent out by fw\n");
  798. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  799. break;
  800. case BNX2FC_ELS:
  801. if (rx_state == FCOE_TASK_RX_STATE_COMPLETED)
  802. bnx2fc_process_els_compl(io_req, task, num_rq);
  803. else if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
  804. bnx2fc_process_abts_compl(io_req, task, num_rq);
  805. else if (rx_state ==
  806. FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
  807. bnx2fc_process_cleanup_compl(io_req, task, num_rq);
  808. else
  809. printk(KERN_ERR PFX "Invalid rx state = %d\n",
  810. rx_state);
  811. break;
  812. case BNX2FC_CLEANUP:
  813. BNX2FC_IO_DBG(io_req, "cq_compl- cleanup resp rcvd\n");
  814. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  815. break;
  816. case BNX2FC_SEQ_CLEANUP:
  817. BNX2FC_IO_DBG(io_req, "cq_compl(0x%x) - seq cleanup resp\n",
  818. io_req->xid);
  819. bnx2fc_process_seq_cleanup_compl(io_req, task, rx_state);
  820. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  821. break;
  822. default:
  823. printk(KERN_ERR PFX "Invalid cmd_type %d\n", cmd_type);
  824. break;
  825. }
  826. spin_unlock_bh(&tgt->tgt_lock);
  827. }
  828. void bnx2fc_arm_cq(struct bnx2fc_rport *tgt)
  829. {
  830. struct b577xx_fcoe_rx_doorbell *rx_db = &tgt->rx_db;
  831. u32 msg;
  832. wmb();
  833. rx_db->doorbell_cq_cons = tgt->cq_cons_idx | (tgt->cq_curr_toggle_bit <<
  834. FCOE_CQE_TOGGLE_BIT_SHIFT);
  835. msg = *((u32 *)rx_db);
  836. writel(cpu_to_le32(msg), tgt->ctx_base);
  837. mmiowb();
  838. }
  839. static struct bnx2fc_work *bnx2fc_alloc_work(struct bnx2fc_rport *tgt, u16 wqe)
  840. {
  841. struct bnx2fc_work *work;
  842. work = kzalloc(sizeof(struct bnx2fc_work), GFP_ATOMIC);
  843. if (!work)
  844. return NULL;
  845. INIT_LIST_HEAD(&work->list);
  846. work->tgt = tgt;
  847. work->wqe = wqe;
  848. return work;
  849. }
  850. /* Pending work request completion */
  851. static void bnx2fc_pending_work(struct bnx2fc_rport *tgt, unsigned int wqe)
  852. {
  853. unsigned int cpu = wqe % num_possible_cpus();
  854. struct bnx2fc_percpu_s *fps;
  855. struct bnx2fc_work *work;
  856. fps = &per_cpu(bnx2fc_percpu, cpu);
  857. spin_lock_bh(&fps->fp_work_lock);
  858. if (fps->iothread) {
  859. work = bnx2fc_alloc_work(tgt, wqe);
  860. if (work) {
  861. list_add_tail(&work->list, &fps->work_list);
  862. wake_up_process(fps->iothread);
  863. spin_unlock_bh(&fps->fp_work_lock);
  864. return;
  865. }
  866. }
  867. spin_unlock_bh(&fps->fp_work_lock);
  868. bnx2fc_process_cq_compl(tgt, wqe);
  869. }
  870. int bnx2fc_process_new_cqes(struct bnx2fc_rport *tgt)
  871. {
  872. struct fcoe_cqe *cq;
  873. u32 cq_cons;
  874. struct fcoe_cqe *cqe;
  875. u32 num_free_sqes = 0;
  876. u32 num_cqes = 0;
  877. u16 wqe;
  878. /*
  879. * cq_lock is a low contention lock used to protect
  880. * the CQ data structure from being freed up during
  881. * the upload operation
  882. */
  883. spin_lock_bh(&tgt->cq_lock);
  884. if (!tgt->cq) {
  885. printk(KERN_ERR PFX "process_new_cqes: cq is NULL\n");
  886. spin_unlock_bh(&tgt->cq_lock);
  887. return 0;
  888. }
  889. cq = tgt->cq;
  890. cq_cons = tgt->cq_cons_idx;
  891. cqe = &cq[cq_cons];
  892. while (((wqe = cqe->wqe) & FCOE_CQE_TOGGLE_BIT) ==
  893. (tgt->cq_curr_toggle_bit <<
  894. FCOE_CQE_TOGGLE_BIT_SHIFT)) {
  895. /* new entry on the cq */
  896. if (wqe & FCOE_CQE_CQE_TYPE) {
  897. /* Unsolicited event notification */
  898. bnx2fc_process_unsol_compl(tgt, wqe);
  899. } else {
  900. bnx2fc_pending_work(tgt, wqe);
  901. num_free_sqes++;
  902. }
  903. cqe++;
  904. tgt->cq_cons_idx++;
  905. num_cqes++;
  906. if (tgt->cq_cons_idx == BNX2FC_CQ_WQES_MAX) {
  907. tgt->cq_cons_idx = 0;
  908. cqe = cq;
  909. tgt->cq_curr_toggle_bit =
  910. 1 - tgt->cq_curr_toggle_bit;
  911. }
  912. }
  913. if (num_cqes) {
  914. /* Arm CQ only if doorbell is mapped */
  915. if (tgt->ctx_base)
  916. bnx2fc_arm_cq(tgt);
  917. atomic_add(num_free_sqes, &tgt->free_sqes);
  918. }
  919. spin_unlock_bh(&tgt->cq_lock);
  920. return 0;
  921. }
  922. /**
  923. * bnx2fc_fastpath_notification - process global event queue (KCQ)
  924. *
  925. * @hba: adapter structure pointer
  926. * @new_cqe_kcqe: pointer to newly DMA'd KCQ entry
  927. *
  928. * Fast path event notification handler
  929. */
  930. static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
  931. struct fcoe_kcqe *new_cqe_kcqe)
  932. {
  933. u32 conn_id = new_cqe_kcqe->fcoe_conn_id;
  934. struct bnx2fc_rport *tgt = hba->tgt_ofld_list[conn_id];
  935. if (!tgt) {
  936. printk(KERN_ERR PFX "conn_id 0x%x not valid\n", conn_id);
  937. return;
  938. }
  939. bnx2fc_process_new_cqes(tgt);
  940. }
  941. /**
  942. * bnx2fc_process_ofld_cmpl - process FCoE session offload completion
  943. *
  944. * @hba: adapter structure pointer
  945. * @ofld_kcqe: connection offload kcqe pointer
  946. *
  947. * handle session offload completion, enable the session if offload is
  948. * successful.
  949. */
  950. static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
  951. struct fcoe_kcqe *ofld_kcqe)
  952. {
  953. struct bnx2fc_rport *tgt;
  954. struct fcoe_port *port;
  955. struct bnx2fc_interface *interface;
  956. u32 conn_id;
  957. u32 context_id;
  958. conn_id = ofld_kcqe->fcoe_conn_id;
  959. context_id = ofld_kcqe->fcoe_conn_context_id;
  960. tgt = hba->tgt_ofld_list[conn_id];
  961. if (!tgt) {
  962. printk(KERN_ALERT PFX "ERROR:ofld_cmpl: No pending ofld req\n");
  963. return;
  964. }
  965. BNX2FC_TGT_DBG(tgt, "Entered ofld compl - context_id = 0x%x\n",
  966. ofld_kcqe->fcoe_conn_context_id);
  967. port = tgt->port;
  968. interface = tgt->port->priv;
  969. if (hba != interface->hba) {
  970. printk(KERN_ERR PFX "ERROR:ofld_cmpl: HBA mis-match\n");
  971. goto ofld_cmpl_err;
  972. }
  973. /*
  974. * cnic has allocated a context_id for this session; use this
  975. * while enabling the session.
  976. */
  977. tgt->context_id = context_id;
  978. if (ofld_kcqe->completion_status) {
  979. if (ofld_kcqe->completion_status ==
  980. FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE) {
  981. printk(KERN_ERR PFX "unable to allocate FCoE context "
  982. "resources\n");
  983. set_bit(BNX2FC_FLAG_CTX_ALLOC_FAILURE, &tgt->flags);
  984. }
  985. } else {
  986. /* FW offload request successfully completed */
  987. set_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
  988. }
  989. ofld_cmpl_err:
  990. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  991. wake_up_interruptible(&tgt->ofld_wait);
  992. }
  993. /**
  994. * bnx2fc_process_enable_conn_cmpl - process FCoE session enable completion
  995. *
  996. * @hba: adapter structure pointer
  997. * @ofld_kcqe: connection offload kcqe pointer
  998. *
  999. * handle session enable completion, mark the rport as ready
  1000. */
  1001. static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
  1002. struct fcoe_kcqe *ofld_kcqe)
  1003. {
  1004. struct bnx2fc_rport *tgt;
  1005. struct bnx2fc_interface *interface;
  1006. u32 conn_id;
  1007. u32 context_id;
  1008. context_id = ofld_kcqe->fcoe_conn_context_id;
  1009. conn_id = ofld_kcqe->fcoe_conn_id;
  1010. tgt = hba->tgt_ofld_list[conn_id];
  1011. if (!tgt) {
  1012. printk(KERN_ERR PFX "ERROR:enbl_cmpl: No pending ofld req\n");
  1013. return;
  1014. }
  1015. BNX2FC_TGT_DBG(tgt, "Enable compl - context_id = 0x%x\n",
  1016. ofld_kcqe->fcoe_conn_context_id);
  1017. /*
  1018. * context_id should be the same for this target during offload
  1019. * and enable
  1020. */
  1021. if (tgt->context_id != context_id) {
  1022. printk(KERN_ERR PFX "context id mis-match\n");
  1023. return;
  1024. }
  1025. interface = tgt->port->priv;
  1026. if (hba != interface->hba) {
  1027. printk(KERN_ERR PFX "bnx2fc-enbl_cmpl: HBA mis-match\n");
  1028. goto enbl_cmpl_err;
  1029. }
  1030. if (!ofld_kcqe->completion_status)
  1031. /* enable successful - rport ready for issuing IOs */
  1032. set_bit(BNX2FC_FLAG_ENABLED, &tgt->flags);
  1033. enbl_cmpl_err:
  1034. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  1035. wake_up_interruptible(&tgt->ofld_wait);
  1036. }
  1037. static void bnx2fc_process_conn_disable_cmpl(struct bnx2fc_hba *hba,
  1038. struct fcoe_kcqe *disable_kcqe)
  1039. {
  1040. struct bnx2fc_rport *tgt;
  1041. u32 conn_id;
  1042. conn_id = disable_kcqe->fcoe_conn_id;
  1043. tgt = hba->tgt_ofld_list[conn_id];
  1044. if (!tgt) {
  1045. printk(KERN_ERR PFX "ERROR: disable_cmpl: No disable req\n");
  1046. return;
  1047. }
  1048. BNX2FC_TGT_DBG(tgt, PFX "disable_cmpl: conn_id %d\n", conn_id);
  1049. if (disable_kcqe->completion_status) {
  1050. printk(KERN_ERR PFX "Disable failed with cmpl status %d\n",
  1051. disable_kcqe->completion_status);
  1052. set_bit(BNX2FC_FLAG_DISABLE_FAILED, &tgt->flags);
  1053. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  1054. wake_up_interruptible(&tgt->upld_wait);
  1055. } else {
  1056. /* disable successful */
  1057. BNX2FC_TGT_DBG(tgt, "disable successful\n");
  1058. clear_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
  1059. clear_bit(BNX2FC_FLAG_ENABLED, &tgt->flags);
  1060. set_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
  1061. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  1062. wake_up_interruptible(&tgt->upld_wait);
  1063. }
  1064. }
  1065. static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
  1066. struct fcoe_kcqe *destroy_kcqe)
  1067. {
  1068. struct bnx2fc_rport *tgt;
  1069. u32 conn_id;
  1070. conn_id = destroy_kcqe->fcoe_conn_id;
  1071. tgt = hba->tgt_ofld_list[conn_id];
  1072. if (!tgt) {
  1073. printk(KERN_ERR PFX "destroy_cmpl: No destroy req\n");
  1074. return;
  1075. }
  1076. BNX2FC_TGT_DBG(tgt, "destroy_cmpl: conn_id %d\n", conn_id);
  1077. if (destroy_kcqe->completion_status) {
  1078. printk(KERN_ERR PFX "Destroy conn failed, cmpl status %d\n",
  1079. destroy_kcqe->completion_status);
  1080. return;
  1081. } else {
  1082. /* destroy successful */
  1083. BNX2FC_TGT_DBG(tgt, "upload successful\n");
  1084. clear_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
  1085. set_bit(BNX2FC_FLAG_DESTROYED, &tgt->flags);
  1086. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  1087. wake_up_interruptible(&tgt->upld_wait);
  1088. }
  1089. }
  1090. static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code)
  1091. {
  1092. switch (err_code) {
  1093. case FCOE_KCQE_COMPLETION_STATUS_INVALID_OPCODE:
  1094. printk(KERN_ERR PFX "init_failure due to invalid opcode\n");
  1095. break;
  1096. case FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE:
  1097. printk(KERN_ERR PFX "init failed due to ctx alloc failure\n");
  1098. break;
  1099. case FCOE_KCQE_COMPLETION_STATUS_NIC_ERROR:
  1100. printk(KERN_ERR PFX "init_failure due to NIC error\n");
  1101. break;
  1102. case FCOE_KCQE_COMPLETION_STATUS_ERROR:
  1103. printk(KERN_ERR PFX "init failure due to compl status err\n");
  1104. break;
  1105. case FCOE_KCQE_COMPLETION_STATUS_WRONG_HSI_VERSION:
  1106. printk(KERN_ERR PFX "init failure due to HSI mismatch\n");
  1107. break;
  1108. default:
  1109. printk(KERN_ERR PFX "Unknown Error code %d\n", err_code);
  1110. }
  1111. }
  1112. /**
  1113. * bnx2fc_indicae_kcqe - process KCQE
  1114. *
  1115. * @hba: adapter structure pointer
  1116. * @kcqe: kcqe pointer
  1117. * @num_cqe: Number of completion queue elements
  1118. *
  1119. * Generic KCQ event handler
  1120. */
  1121. void bnx2fc_indicate_kcqe(void *context, struct kcqe *kcq[],
  1122. u32 num_cqe)
  1123. {
  1124. struct bnx2fc_hba *hba = (struct bnx2fc_hba *)context;
  1125. int i = 0;
  1126. struct fcoe_kcqe *kcqe = NULL;
  1127. while (i < num_cqe) {
  1128. kcqe = (struct fcoe_kcqe *) kcq[i++];
  1129. switch (kcqe->op_code) {
  1130. case FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION:
  1131. bnx2fc_fastpath_notification(hba, kcqe);
  1132. break;
  1133. case FCOE_KCQE_OPCODE_OFFLOAD_CONN:
  1134. bnx2fc_process_ofld_cmpl(hba, kcqe);
  1135. break;
  1136. case FCOE_KCQE_OPCODE_ENABLE_CONN:
  1137. bnx2fc_process_enable_conn_cmpl(hba, kcqe);
  1138. break;
  1139. case FCOE_KCQE_OPCODE_INIT_FUNC:
  1140. if (kcqe->completion_status !=
  1141. FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
  1142. bnx2fc_init_failure(hba,
  1143. kcqe->completion_status);
  1144. } else {
  1145. set_bit(ADAPTER_STATE_UP, &hba->adapter_state);
  1146. bnx2fc_get_link_state(hba);
  1147. printk(KERN_INFO PFX "[%.2x]: FCOE_INIT passed\n",
  1148. (u8)hba->pcidev->bus->number);
  1149. }
  1150. break;
  1151. case FCOE_KCQE_OPCODE_DESTROY_FUNC:
  1152. if (kcqe->completion_status !=
  1153. FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
  1154. printk(KERN_ERR PFX "DESTROY failed\n");
  1155. } else {
  1156. printk(KERN_ERR PFX "DESTROY success\n");
  1157. }
  1158. set_bit(BNX2FC_FLAG_DESTROY_CMPL, &hba->flags);
  1159. wake_up_interruptible(&hba->destroy_wait);
  1160. break;
  1161. case FCOE_KCQE_OPCODE_DISABLE_CONN:
  1162. bnx2fc_process_conn_disable_cmpl(hba, kcqe);
  1163. break;
  1164. case FCOE_KCQE_OPCODE_DESTROY_CONN:
  1165. bnx2fc_process_conn_destroy_cmpl(hba, kcqe);
  1166. break;
  1167. case FCOE_KCQE_OPCODE_STAT_FUNC:
  1168. if (kcqe->completion_status !=
  1169. FCOE_KCQE_COMPLETION_STATUS_SUCCESS)
  1170. printk(KERN_ERR PFX "STAT failed\n");
  1171. complete(&hba->stat_req_done);
  1172. break;
  1173. case FCOE_KCQE_OPCODE_FCOE_ERROR:
  1174. /* fall thru */
  1175. default:
  1176. printk(KERN_ERR PFX "unknown opcode 0x%x\n",
  1177. kcqe->op_code);
  1178. }
  1179. }
  1180. }
  1181. void bnx2fc_add_2_sq(struct bnx2fc_rport *tgt, u16 xid)
  1182. {
  1183. struct fcoe_sqe *sqe;
  1184. sqe = &tgt->sq[tgt->sq_prod_idx];
  1185. /* Fill SQ WQE */
  1186. sqe->wqe = xid << FCOE_SQE_TASK_ID_SHIFT;
  1187. sqe->wqe |= tgt->sq_curr_toggle_bit << FCOE_SQE_TOGGLE_BIT_SHIFT;
  1188. /* Advance SQ Prod Idx */
  1189. if (++tgt->sq_prod_idx == BNX2FC_SQ_WQES_MAX) {
  1190. tgt->sq_prod_idx = 0;
  1191. tgt->sq_curr_toggle_bit = 1 - tgt->sq_curr_toggle_bit;
  1192. }
  1193. }
  1194. void bnx2fc_ring_doorbell(struct bnx2fc_rport *tgt)
  1195. {
  1196. struct b577xx_doorbell_set_prod *sq_db = &tgt->sq_db;
  1197. u32 msg;
  1198. wmb();
  1199. sq_db->prod = tgt->sq_prod_idx |
  1200. (tgt->sq_curr_toggle_bit << 15);
  1201. msg = *((u32 *)sq_db);
  1202. writel(cpu_to_le32(msg), tgt->ctx_base);
  1203. mmiowb();
  1204. }
  1205. int bnx2fc_map_doorbell(struct bnx2fc_rport *tgt)
  1206. {
  1207. u32 context_id = tgt->context_id;
  1208. struct fcoe_port *port = tgt->port;
  1209. u32 reg_off;
  1210. resource_size_t reg_base;
  1211. struct bnx2fc_interface *interface = port->priv;
  1212. struct bnx2fc_hba *hba = interface->hba;
  1213. reg_base = pci_resource_start(hba->pcidev,
  1214. BNX2X_DOORBELL_PCI_BAR);
  1215. reg_off = (1 << BNX2X_DB_SHIFT) * (context_id & 0x1FFFF);
  1216. tgt->ctx_base = ioremap_nocache(reg_base + reg_off, 4);
  1217. if (!tgt->ctx_base)
  1218. return -ENOMEM;
  1219. return 0;
  1220. }
  1221. char *bnx2fc_get_next_rqe(struct bnx2fc_rport *tgt, u8 num_items)
  1222. {
  1223. char *buf = (char *)tgt->rq + (tgt->rq_cons_idx * BNX2FC_RQ_BUF_SZ);
  1224. if (tgt->rq_cons_idx + num_items > BNX2FC_RQ_WQES_MAX)
  1225. return NULL;
  1226. tgt->rq_cons_idx += num_items;
  1227. if (tgt->rq_cons_idx >= BNX2FC_RQ_WQES_MAX)
  1228. tgt->rq_cons_idx -= BNX2FC_RQ_WQES_MAX;
  1229. return buf;
  1230. }
  1231. void bnx2fc_return_rqe(struct bnx2fc_rport *tgt, u8 num_items)
  1232. {
  1233. /* return the rq buffer */
  1234. u32 next_prod_idx = tgt->rq_prod_idx + num_items;
  1235. if ((next_prod_idx & 0x7fff) == BNX2FC_RQ_WQES_MAX) {
  1236. /* Wrap around RQ */
  1237. next_prod_idx += 0x8000 - BNX2FC_RQ_WQES_MAX;
  1238. }
  1239. tgt->rq_prod_idx = next_prod_idx;
  1240. tgt->conn_db->rq_prod = tgt->rq_prod_idx;
  1241. }
  1242. void bnx2fc_init_seq_cleanup_task(struct bnx2fc_cmd *seq_clnp_req,
  1243. struct fcoe_task_ctx_entry *task,
  1244. struct bnx2fc_cmd *orig_io_req,
  1245. u32 offset)
  1246. {
  1247. struct scsi_cmnd *sc_cmd = orig_io_req->sc_cmd;
  1248. struct bnx2fc_rport *tgt = seq_clnp_req->tgt;
  1249. struct bnx2fc_interface *interface = tgt->port->priv;
  1250. struct fcoe_bd_ctx *bd = orig_io_req->bd_tbl->bd_tbl;
  1251. struct fcoe_task_ctx_entry *orig_task;
  1252. struct fcoe_task_ctx_entry *task_page;
  1253. struct fcoe_ext_mul_sges_ctx *sgl;
  1254. u8 task_type = FCOE_TASK_TYPE_SEQUENCE_CLEANUP;
  1255. u8 orig_task_type;
  1256. u16 orig_xid = orig_io_req->xid;
  1257. u32 context_id = tgt->context_id;
  1258. u64 phys_addr = (u64)orig_io_req->bd_tbl->bd_tbl_dma;
  1259. u32 orig_offset = offset;
  1260. int bd_count;
  1261. int orig_task_idx, index;
  1262. int i;
  1263. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1264. if (sc_cmd->sc_data_direction == DMA_TO_DEVICE)
  1265. orig_task_type = FCOE_TASK_TYPE_WRITE;
  1266. else
  1267. orig_task_type = FCOE_TASK_TYPE_READ;
  1268. /* Tx flags */
  1269. task->txwr_rxrd.const_ctx.tx_flags =
  1270. FCOE_TASK_TX_STATE_SEQUENCE_CLEANUP <<
  1271. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1272. /* init flags */
  1273. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1274. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1275. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1276. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1277. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1278. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1279. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1280. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1281. task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid;
  1282. task->txwr_rxrd.union_ctx.cleanup.ctx.rolled_tx_seq_cnt = 0;
  1283. task->txwr_rxrd.union_ctx.cleanup.ctx.rolled_tx_data_offset = offset;
  1284. bd_count = orig_io_req->bd_tbl->bd_valid;
  1285. /* obtain the appropriate bd entry from relative offset */
  1286. for (i = 0; i < bd_count; i++) {
  1287. if (offset < bd[i].buf_len)
  1288. break;
  1289. offset -= bd[i].buf_len;
  1290. }
  1291. phys_addr += (i * sizeof(struct fcoe_bd_ctx));
  1292. if (orig_task_type == FCOE_TASK_TYPE_WRITE) {
  1293. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
  1294. (u32)phys_addr;
  1295. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
  1296. (u32)((u64)phys_addr >> 32);
  1297. task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size =
  1298. bd_count;
  1299. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_off =
  1300. offset; /* adjusted offset */
  1301. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_idx = i;
  1302. } else {
  1303. orig_task_idx = orig_xid / BNX2FC_TASKS_PER_PAGE;
  1304. index = orig_xid % BNX2FC_TASKS_PER_PAGE;
  1305. task_page = (struct fcoe_task_ctx_entry *)
  1306. interface->hba->task_ctx[orig_task_idx];
  1307. orig_task = &(task_page[index]);
  1308. /* Multiple SGEs were used for this IO */
  1309. sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
  1310. sgl->mul_sgl.cur_sge_addr.lo = (u32)phys_addr;
  1311. sgl->mul_sgl.cur_sge_addr.hi = (u32)((u64)phys_addr >> 32);
  1312. sgl->mul_sgl.sgl_size = bd_count;
  1313. sgl->mul_sgl.cur_sge_off = offset; /*adjusted offset */
  1314. sgl->mul_sgl.cur_sge_idx = i;
  1315. memset(&task->rxwr_only.rx_seq_ctx, 0,
  1316. sizeof(struct fcoe_rx_seq_ctx));
  1317. task->rxwr_only.rx_seq_ctx.low_exp_ro = orig_offset;
  1318. task->rxwr_only.rx_seq_ctx.high_exp_ro = orig_offset;
  1319. }
  1320. }
  1321. void bnx2fc_init_cleanup_task(struct bnx2fc_cmd *io_req,
  1322. struct fcoe_task_ctx_entry *task,
  1323. u16 orig_xid)
  1324. {
  1325. u8 task_type = FCOE_TASK_TYPE_EXCHANGE_CLEANUP;
  1326. struct bnx2fc_rport *tgt = io_req->tgt;
  1327. u32 context_id = tgt->context_id;
  1328. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1329. /* Tx Write Rx Read */
  1330. /* init flags */
  1331. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1332. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1333. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1334. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1335. if (tgt->dev_type == TYPE_TAPE)
  1336. task->txwr_rxrd.const_ctx.init_flags |=
  1337. FCOE_TASK_DEV_TYPE_TAPE <<
  1338. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1339. else
  1340. task->txwr_rxrd.const_ctx.init_flags |=
  1341. FCOE_TASK_DEV_TYPE_DISK <<
  1342. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1343. task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid;
  1344. /* Tx flags */
  1345. task->txwr_rxrd.const_ctx.tx_flags =
  1346. FCOE_TASK_TX_STATE_EXCHANGE_CLEANUP <<
  1347. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1348. /* Rx Read Tx Write */
  1349. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1350. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1351. task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
  1352. FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
  1353. }
  1354. void bnx2fc_init_mp_task(struct bnx2fc_cmd *io_req,
  1355. struct fcoe_task_ctx_entry *task)
  1356. {
  1357. struct bnx2fc_mp_req *mp_req = &(io_req->mp_req);
  1358. struct bnx2fc_rport *tgt = io_req->tgt;
  1359. struct fc_frame_header *fc_hdr;
  1360. struct fcoe_ext_mul_sges_ctx *sgl;
  1361. u8 task_type = 0;
  1362. u64 *hdr;
  1363. u64 temp_hdr[3];
  1364. u32 context_id;
  1365. /* Obtain task_type */
  1366. if ((io_req->cmd_type == BNX2FC_TASK_MGMT_CMD) ||
  1367. (io_req->cmd_type == BNX2FC_ELS)) {
  1368. task_type = FCOE_TASK_TYPE_MIDPATH;
  1369. } else if (io_req->cmd_type == BNX2FC_ABTS) {
  1370. task_type = FCOE_TASK_TYPE_ABTS;
  1371. }
  1372. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1373. /* Setup the task from io_req for easy reference */
  1374. io_req->task = task;
  1375. BNX2FC_IO_DBG(io_req, "Init MP task for cmd_type = %d task_type = %d\n",
  1376. io_req->cmd_type, task_type);
  1377. /* Tx only */
  1378. if ((task_type == FCOE_TASK_TYPE_MIDPATH) ||
  1379. (task_type == FCOE_TASK_TYPE_UNSOLICITED)) {
  1380. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
  1381. (u32)mp_req->mp_req_bd_dma;
  1382. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
  1383. (u32)((u64)mp_req->mp_req_bd_dma >> 32);
  1384. task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size = 1;
  1385. }
  1386. /* Tx Write Rx Read */
  1387. /* init flags */
  1388. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1389. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1390. if (tgt->dev_type == TYPE_TAPE)
  1391. task->txwr_rxrd.const_ctx.init_flags |=
  1392. FCOE_TASK_DEV_TYPE_TAPE <<
  1393. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1394. else
  1395. task->txwr_rxrd.const_ctx.init_flags |=
  1396. FCOE_TASK_DEV_TYPE_DISK <<
  1397. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1398. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1399. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1400. /* tx flags */
  1401. task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_INIT <<
  1402. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1403. /* Rx Write Tx Read */
  1404. task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
  1405. /* rx flags */
  1406. task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
  1407. FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
  1408. context_id = tgt->context_id;
  1409. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1410. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1411. fc_hdr = &(mp_req->req_fc_hdr);
  1412. if (task_type == FCOE_TASK_TYPE_MIDPATH) {
  1413. fc_hdr->fh_ox_id = cpu_to_be16(io_req->xid);
  1414. fc_hdr->fh_rx_id = htons(0xffff);
  1415. task->rxwr_txrd.var_ctx.rx_id = 0xffff;
  1416. } else if (task_type == FCOE_TASK_TYPE_UNSOLICITED) {
  1417. fc_hdr->fh_rx_id = cpu_to_be16(io_req->xid);
  1418. }
  1419. /* Fill FC Header into middle path buffer */
  1420. hdr = (u64 *) &task->txwr_rxrd.union_ctx.tx_frame.fc_hdr;
  1421. memcpy(temp_hdr, fc_hdr, sizeof(temp_hdr));
  1422. hdr[0] = cpu_to_be64(temp_hdr[0]);
  1423. hdr[1] = cpu_to_be64(temp_hdr[1]);
  1424. hdr[2] = cpu_to_be64(temp_hdr[2]);
  1425. /* Rx Only */
  1426. if (task_type == FCOE_TASK_TYPE_MIDPATH) {
  1427. sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
  1428. sgl->mul_sgl.cur_sge_addr.lo = (u32)mp_req->mp_resp_bd_dma;
  1429. sgl->mul_sgl.cur_sge_addr.hi =
  1430. (u32)((u64)mp_req->mp_resp_bd_dma >> 32);
  1431. sgl->mul_sgl.sgl_size = 1;
  1432. }
  1433. }
  1434. void bnx2fc_init_task(struct bnx2fc_cmd *io_req,
  1435. struct fcoe_task_ctx_entry *task)
  1436. {
  1437. u8 task_type;
  1438. struct scsi_cmnd *sc_cmd = io_req->sc_cmd;
  1439. struct io_bdt *bd_tbl = io_req->bd_tbl;
  1440. struct bnx2fc_rport *tgt = io_req->tgt;
  1441. struct fcoe_cached_sge_ctx *cached_sge;
  1442. struct fcoe_ext_mul_sges_ctx *sgl;
  1443. int dev_type = tgt->dev_type;
  1444. u64 *fcp_cmnd;
  1445. u64 tmp_fcp_cmnd[4];
  1446. u32 context_id;
  1447. int cnt, i;
  1448. int bd_count;
  1449. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1450. /* Setup the task from io_req for easy reference */
  1451. io_req->task = task;
  1452. if (sc_cmd->sc_data_direction == DMA_TO_DEVICE)
  1453. task_type = FCOE_TASK_TYPE_WRITE;
  1454. else
  1455. task_type = FCOE_TASK_TYPE_READ;
  1456. /* Tx only */
  1457. bd_count = bd_tbl->bd_valid;
  1458. cached_sge = &task->rxwr_only.union_ctx.read_info.sgl_ctx.cached_sge;
  1459. if (task_type == FCOE_TASK_TYPE_WRITE) {
  1460. if ((dev_type == TYPE_DISK) && (bd_count == 1)) {
  1461. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1462. task->txwr_only.sgl_ctx.cached_sge.cur_buf_addr.lo =
  1463. cached_sge->cur_buf_addr.lo =
  1464. fcoe_bd_tbl->buf_addr_lo;
  1465. task->txwr_only.sgl_ctx.cached_sge.cur_buf_addr.hi =
  1466. cached_sge->cur_buf_addr.hi =
  1467. fcoe_bd_tbl->buf_addr_hi;
  1468. task->txwr_only.sgl_ctx.cached_sge.cur_buf_rem =
  1469. cached_sge->cur_buf_rem =
  1470. fcoe_bd_tbl->buf_len;
  1471. task->txwr_rxrd.const_ctx.init_flags |= 1 <<
  1472. FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
  1473. } else {
  1474. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
  1475. (u32)bd_tbl->bd_tbl_dma;
  1476. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
  1477. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1478. task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size =
  1479. bd_tbl->bd_valid;
  1480. }
  1481. }
  1482. /*Tx Write Rx Read */
  1483. /* Init state to NORMAL */
  1484. task->txwr_rxrd.const_ctx.init_flags |= task_type <<
  1485. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1486. if (dev_type == TYPE_TAPE) {
  1487. task->txwr_rxrd.const_ctx.init_flags |=
  1488. FCOE_TASK_DEV_TYPE_TAPE <<
  1489. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1490. io_req->rec_retry = 0;
  1491. io_req->rec_retry = 0;
  1492. } else
  1493. task->txwr_rxrd.const_ctx.init_flags |=
  1494. FCOE_TASK_DEV_TYPE_DISK <<
  1495. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1496. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1497. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1498. /* tx flags */
  1499. task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_NORMAL <<
  1500. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1501. /* Set initial seq counter */
  1502. task->txwr_rxrd.union_ctx.tx_seq.ctx.seq_cnt = 1;
  1503. /* Fill FCP_CMND IU */
  1504. fcp_cmnd = (u64 *)
  1505. task->txwr_rxrd.union_ctx.fcp_cmd.opaque;
  1506. bnx2fc_build_fcp_cmnd(io_req, (struct fcp_cmnd *)&tmp_fcp_cmnd);
  1507. /* swap fcp_cmnd */
  1508. cnt = sizeof(struct fcp_cmnd) / sizeof(u64);
  1509. for (i = 0; i < cnt; i++) {
  1510. *fcp_cmnd = cpu_to_be64(tmp_fcp_cmnd[i]);
  1511. fcp_cmnd++;
  1512. }
  1513. /* Rx Write Tx Read */
  1514. task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
  1515. context_id = tgt->context_id;
  1516. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1517. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1518. /* rx flags */
  1519. /* Set state to "waiting for the first packet" */
  1520. task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
  1521. FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
  1522. task->rxwr_txrd.var_ctx.rx_id = 0xffff;
  1523. /* Rx Only */
  1524. if (task_type != FCOE_TASK_TYPE_READ)
  1525. return;
  1526. sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
  1527. bd_count = bd_tbl->bd_valid;
  1528. if (dev_type == TYPE_DISK) {
  1529. if (bd_count == 1) {
  1530. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1531. cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
  1532. cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
  1533. cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
  1534. task->txwr_rxrd.const_ctx.init_flags |= 1 <<
  1535. FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
  1536. } else if (bd_count == 2) {
  1537. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1538. cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
  1539. cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
  1540. cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
  1541. fcoe_bd_tbl++;
  1542. cached_sge->second_buf_addr.lo =
  1543. fcoe_bd_tbl->buf_addr_lo;
  1544. cached_sge->second_buf_addr.hi =
  1545. fcoe_bd_tbl->buf_addr_hi;
  1546. cached_sge->second_buf_rem = fcoe_bd_tbl->buf_len;
  1547. task->txwr_rxrd.const_ctx.init_flags |= 1 <<
  1548. FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
  1549. } else {
  1550. sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma;
  1551. sgl->mul_sgl.cur_sge_addr.hi =
  1552. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1553. sgl->mul_sgl.sgl_size = bd_count;
  1554. }
  1555. } else {
  1556. sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma;
  1557. sgl->mul_sgl.cur_sge_addr.hi =
  1558. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1559. sgl->mul_sgl.sgl_size = bd_count;
  1560. }
  1561. }
  1562. /**
  1563. * bnx2fc_setup_task_ctx - allocate and map task context
  1564. *
  1565. * @hba: pointer to adapter structure
  1566. *
  1567. * allocate memory for task context, and associated BD table to be used
  1568. * by firmware
  1569. *
  1570. */
  1571. int bnx2fc_setup_task_ctx(struct bnx2fc_hba *hba)
  1572. {
  1573. int rc = 0;
  1574. struct regpair *task_ctx_bdt;
  1575. dma_addr_t addr;
  1576. int task_ctx_arr_sz;
  1577. int i;
  1578. /*
  1579. * Allocate task context bd table. A page size of bd table
  1580. * can map 256 buffers. Each buffer contains 32 task context
  1581. * entries. Hence the limit with one page is 8192 task context
  1582. * entries.
  1583. */
  1584. hba->task_ctx_bd_tbl = dma_zalloc_coherent(&hba->pcidev->dev,
  1585. PAGE_SIZE,
  1586. &hba->task_ctx_bd_dma,
  1587. GFP_KERNEL);
  1588. if (!hba->task_ctx_bd_tbl) {
  1589. printk(KERN_ERR PFX "unable to allocate task context BDT\n");
  1590. rc = -1;
  1591. goto out;
  1592. }
  1593. /*
  1594. * Allocate task_ctx which is an array of pointers pointing to
  1595. * a page containing 32 task contexts
  1596. */
  1597. task_ctx_arr_sz = (hba->max_tasks / BNX2FC_TASKS_PER_PAGE);
  1598. hba->task_ctx = kzalloc((task_ctx_arr_sz * sizeof(void *)),
  1599. GFP_KERNEL);
  1600. if (!hba->task_ctx) {
  1601. printk(KERN_ERR PFX "unable to allocate task context array\n");
  1602. rc = -1;
  1603. goto out1;
  1604. }
  1605. /*
  1606. * Allocate task_ctx_dma which is an array of dma addresses
  1607. */
  1608. hba->task_ctx_dma = kmalloc((task_ctx_arr_sz *
  1609. sizeof(dma_addr_t)), GFP_KERNEL);
  1610. if (!hba->task_ctx_dma) {
  1611. printk(KERN_ERR PFX "unable to alloc context mapping array\n");
  1612. rc = -1;
  1613. goto out2;
  1614. }
  1615. task_ctx_bdt = (struct regpair *)hba->task_ctx_bd_tbl;
  1616. for (i = 0; i < task_ctx_arr_sz; i++) {
  1617. hba->task_ctx[i] = dma_zalloc_coherent(&hba->pcidev->dev,
  1618. PAGE_SIZE,
  1619. &hba->task_ctx_dma[i],
  1620. GFP_KERNEL);
  1621. if (!hba->task_ctx[i]) {
  1622. printk(KERN_ERR PFX "unable to alloc task context\n");
  1623. rc = -1;
  1624. goto out3;
  1625. }
  1626. addr = (u64)hba->task_ctx_dma[i];
  1627. task_ctx_bdt->hi = cpu_to_le32((u64)addr >> 32);
  1628. task_ctx_bdt->lo = cpu_to_le32((u32)addr);
  1629. task_ctx_bdt++;
  1630. }
  1631. return 0;
  1632. out3:
  1633. for (i = 0; i < task_ctx_arr_sz; i++) {
  1634. if (hba->task_ctx[i]) {
  1635. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1636. hba->task_ctx[i], hba->task_ctx_dma[i]);
  1637. hba->task_ctx[i] = NULL;
  1638. }
  1639. }
  1640. kfree(hba->task_ctx_dma);
  1641. hba->task_ctx_dma = NULL;
  1642. out2:
  1643. kfree(hba->task_ctx);
  1644. hba->task_ctx = NULL;
  1645. out1:
  1646. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1647. hba->task_ctx_bd_tbl, hba->task_ctx_bd_dma);
  1648. hba->task_ctx_bd_tbl = NULL;
  1649. out:
  1650. return rc;
  1651. }
  1652. void bnx2fc_free_task_ctx(struct bnx2fc_hba *hba)
  1653. {
  1654. int task_ctx_arr_sz;
  1655. int i;
  1656. if (hba->task_ctx_bd_tbl) {
  1657. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1658. hba->task_ctx_bd_tbl,
  1659. hba->task_ctx_bd_dma);
  1660. hba->task_ctx_bd_tbl = NULL;
  1661. }
  1662. task_ctx_arr_sz = (hba->max_tasks / BNX2FC_TASKS_PER_PAGE);
  1663. if (hba->task_ctx) {
  1664. for (i = 0; i < task_ctx_arr_sz; i++) {
  1665. if (hba->task_ctx[i]) {
  1666. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1667. hba->task_ctx[i],
  1668. hba->task_ctx_dma[i]);
  1669. hba->task_ctx[i] = NULL;
  1670. }
  1671. }
  1672. kfree(hba->task_ctx);
  1673. hba->task_ctx = NULL;
  1674. }
  1675. kfree(hba->task_ctx_dma);
  1676. hba->task_ctx_dma = NULL;
  1677. }
  1678. static void bnx2fc_free_hash_table(struct bnx2fc_hba *hba)
  1679. {
  1680. int i;
  1681. int segment_count;
  1682. u32 *pbl;
  1683. if (hba->hash_tbl_segments) {
  1684. pbl = hba->hash_tbl_pbl;
  1685. if (pbl) {
  1686. segment_count = hba->hash_tbl_segment_count;
  1687. for (i = 0; i < segment_count; ++i) {
  1688. dma_addr_t dma_address;
  1689. dma_address = le32_to_cpu(*pbl);
  1690. ++pbl;
  1691. dma_address += ((u64)le32_to_cpu(*pbl)) << 32;
  1692. ++pbl;
  1693. dma_free_coherent(&hba->pcidev->dev,
  1694. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1695. hba->hash_tbl_segments[i],
  1696. dma_address);
  1697. }
  1698. }
  1699. kfree(hba->hash_tbl_segments);
  1700. hba->hash_tbl_segments = NULL;
  1701. }
  1702. if (hba->hash_tbl_pbl) {
  1703. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1704. hba->hash_tbl_pbl,
  1705. hba->hash_tbl_pbl_dma);
  1706. hba->hash_tbl_pbl = NULL;
  1707. }
  1708. }
  1709. static int bnx2fc_allocate_hash_table(struct bnx2fc_hba *hba)
  1710. {
  1711. int i;
  1712. int hash_table_size;
  1713. int segment_count;
  1714. int segment_array_size;
  1715. int dma_segment_array_size;
  1716. dma_addr_t *dma_segment_array;
  1717. u32 *pbl;
  1718. hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
  1719. sizeof(struct fcoe_hash_table_entry);
  1720. segment_count = hash_table_size + BNX2FC_HASH_TBL_CHUNK_SIZE - 1;
  1721. segment_count /= BNX2FC_HASH_TBL_CHUNK_SIZE;
  1722. hba->hash_tbl_segment_count = segment_count;
  1723. segment_array_size = segment_count * sizeof(*hba->hash_tbl_segments);
  1724. hba->hash_tbl_segments = kzalloc(segment_array_size, GFP_KERNEL);
  1725. if (!hba->hash_tbl_segments) {
  1726. printk(KERN_ERR PFX "hash table pointers alloc failed\n");
  1727. return -ENOMEM;
  1728. }
  1729. dma_segment_array_size = segment_count * sizeof(*dma_segment_array);
  1730. dma_segment_array = kzalloc(dma_segment_array_size, GFP_KERNEL);
  1731. if (!dma_segment_array) {
  1732. printk(KERN_ERR PFX "hash table pointers (dma) alloc failed\n");
  1733. goto cleanup_ht;
  1734. }
  1735. for (i = 0; i < segment_count; ++i) {
  1736. hba->hash_tbl_segments[i] = dma_zalloc_coherent(&hba->pcidev->dev,
  1737. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1738. &dma_segment_array[i],
  1739. GFP_KERNEL);
  1740. if (!hba->hash_tbl_segments[i]) {
  1741. printk(KERN_ERR PFX "hash segment alloc failed\n");
  1742. goto cleanup_dma;
  1743. }
  1744. }
  1745. hba->hash_tbl_pbl = dma_zalloc_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1746. &hba->hash_tbl_pbl_dma,
  1747. GFP_KERNEL);
  1748. if (!hba->hash_tbl_pbl) {
  1749. printk(KERN_ERR PFX "hash table pbl alloc failed\n");
  1750. goto cleanup_dma;
  1751. }
  1752. pbl = hba->hash_tbl_pbl;
  1753. for (i = 0; i < segment_count; ++i) {
  1754. u64 paddr = dma_segment_array[i];
  1755. *pbl = cpu_to_le32((u32) paddr);
  1756. ++pbl;
  1757. *pbl = cpu_to_le32((u32) (paddr >> 32));
  1758. ++pbl;
  1759. }
  1760. pbl = hba->hash_tbl_pbl;
  1761. i = 0;
  1762. while (*pbl && *(pbl + 1)) {
  1763. u32 lo;
  1764. u32 hi;
  1765. lo = *pbl;
  1766. ++pbl;
  1767. hi = *pbl;
  1768. ++pbl;
  1769. ++i;
  1770. }
  1771. kfree(dma_segment_array);
  1772. return 0;
  1773. cleanup_dma:
  1774. for (i = 0; i < segment_count; ++i) {
  1775. if (hba->hash_tbl_segments[i])
  1776. dma_free_coherent(&hba->pcidev->dev,
  1777. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1778. hba->hash_tbl_segments[i],
  1779. dma_segment_array[i]);
  1780. }
  1781. kfree(dma_segment_array);
  1782. cleanup_ht:
  1783. kfree(hba->hash_tbl_segments);
  1784. hba->hash_tbl_segments = NULL;
  1785. return -ENOMEM;
  1786. }
  1787. /**
  1788. * bnx2fc_setup_fw_resc - Allocate and map hash table and dummy buffer
  1789. *
  1790. * @hba: Pointer to adapter structure
  1791. *
  1792. */
  1793. int bnx2fc_setup_fw_resc(struct bnx2fc_hba *hba)
  1794. {
  1795. u64 addr;
  1796. u32 mem_size;
  1797. int i;
  1798. if (bnx2fc_allocate_hash_table(hba))
  1799. return -ENOMEM;
  1800. mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
  1801. hba->t2_hash_tbl_ptr = dma_zalloc_coherent(&hba->pcidev->dev,
  1802. mem_size,
  1803. &hba->t2_hash_tbl_ptr_dma,
  1804. GFP_KERNEL);
  1805. if (!hba->t2_hash_tbl_ptr) {
  1806. printk(KERN_ERR PFX "unable to allocate t2 hash table ptr\n");
  1807. bnx2fc_free_fw_resc(hba);
  1808. return -ENOMEM;
  1809. }
  1810. mem_size = BNX2FC_NUM_MAX_SESS *
  1811. sizeof(struct fcoe_t2_hash_table_entry);
  1812. hba->t2_hash_tbl = dma_zalloc_coherent(&hba->pcidev->dev, mem_size,
  1813. &hba->t2_hash_tbl_dma,
  1814. GFP_KERNEL);
  1815. if (!hba->t2_hash_tbl) {
  1816. printk(KERN_ERR PFX "unable to allocate t2 hash table\n");
  1817. bnx2fc_free_fw_resc(hba);
  1818. return -ENOMEM;
  1819. }
  1820. for (i = 0; i < BNX2FC_NUM_MAX_SESS; i++) {
  1821. addr = (unsigned long) hba->t2_hash_tbl_dma +
  1822. ((i+1) * sizeof(struct fcoe_t2_hash_table_entry));
  1823. hba->t2_hash_tbl[i].next.lo = addr & 0xffffffff;
  1824. hba->t2_hash_tbl[i].next.hi = addr >> 32;
  1825. }
  1826. hba->dummy_buffer = dma_alloc_coherent(&hba->pcidev->dev,
  1827. PAGE_SIZE, &hba->dummy_buf_dma,
  1828. GFP_KERNEL);
  1829. if (!hba->dummy_buffer) {
  1830. printk(KERN_ERR PFX "unable to alloc MP Dummy Buffer\n");
  1831. bnx2fc_free_fw_resc(hba);
  1832. return -ENOMEM;
  1833. }
  1834. hba->stats_buffer = dma_zalloc_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1835. &hba->stats_buf_dma,
  1836. GFP_KERNEL);
  1837. if (!hba->stats_buffer) {
  1838. printk(KERN_ERR PFX "unable to alloc Stats Buffer\n");
  1839. bnx2fc_free_fw_resc(hba);
  1840. return -ENOMEM;
  1841. }
  1842. return 0;
  1843. }
  1844. void bnx2fc_free_fw_resc(struct bnx2fc_hba *hba)
  1845. {
  1846. u32 mem_size;
  1847. if (hba->stats_buffer) {
  1848. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1849. hba->stats_buffer, hba->stats_buf_dma);
  1850. hba->stats_buffer = NULL;
  1851. }
  1852. if (hba->dummy_buffer) {
  1853. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1854. hba->dummy_buffer, hba->dummy_buf_dma);
  1855. hba->dummy_buffer = NULL;
  1856. }
  1857. if (hba->t2_hash_tbl_ptr) {
  1858. mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
  1859. dma_free_coherent(&hba->pcidev->dev, mem_size,
  1860. hba->t2_hash_tbl_ptr,
  1861. hba->t2_hash_tbl_ptr_dma);
  1862. hba->t2_hash_tbl_ptr = NULL;
  1863. }
  1864. if (hba->t2_hash_tbl) {
  1865. mem_size = BNX2FC_NUM_MAX_SESS *
  1866. sizeof(struct fcoe_t2_hash_table_entry);
  1867. dma_free_coherent(&hba->pcidev->dev, mem_size,
  1868. hba->t2_hash_tbl, hba->t2_hash_tbl_dma);
  1869. hba->t2_hash_tbl = NULL;
  1870. }
  1871. bnx2fc_free_hash_table(hba);
  1872. }