rtc-vr41xx.c 8.6 KB

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  1. /*
  2. * Driver for NEC VR4100 series Real Time Clock unit.
  3. *
  4. * Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. */
  20. #include <linux/err.h>
  21. #include <linux/fs.h>
  22. #include <linux/init.h>
  23. #include <linux/io.h>
  24. #include <linux/ioport.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/module.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/rtc.h>
  29. #include <linux/spinlock.h>
  30. #include <linux/types.h>
  31. #include <linux/uaccess.h>
  32. #include <linux/log2.h>
  33. #include <asm/div64.h>
  34. MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
  35. MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
  36. MODULE_LICENSE("GPL v2");
  37. /* RTC 1 registers */
  38. #define ETIMELREG 0x00
  39. #define ETIMEMREG 0x02
  40. #define ETIMEHREG 0x04
  41. /* RFU */
  42. #define ECMPLREG 0x08
  43. #define ECMPMREG 0x0a
  44. #define ECMPHREG 0x0c
  45. /* RFU */
  46. #define RTCL1LREG 0x10
  47. #define RTCL1HREG 0x12
  48. #define RTCL1CNTLREG 0x14
  49. #define RTCL1CNTHREG 0x16
  50. #define RTCL2LREG 0x18
  51. #define RTCL2HREG 0x1a
  52. #define RTCL2CNTLREG 0x1c
  53. #define RTCL2CNTHREG 0x1e
  54. /* RTC 2 registers */
  55. #define TCLKLREG 0x00
  56. #define TCLKHREG 0x02
  57. #define TCLKCNTLREG 0x04
  58. #define TCLKCNTHREG 0x06
  59. /* RFU */
  60. #define RTCINTREG 0x1e
  61. #define TCLOCK_INT 0x08
  62. #define RTCLONG2_INT 0x04
  63. #define RTCLONG1_INT 0x02
  64. #define ELAPSEDTIME_INT 0x01
  65. #define RTC_FREQUENCY 32768
  66. #define MAX_PERIODIC_RATE 6553
  67. static void __iomem *rtc1_base;
  68. static void __iomem *rtc2_base;
  69. #define rtc1_read(offset) readw(rtc1_base + (offset))
  70. #define rtc1_write(offset, value) writew((value), rtc1_base + (offset))
  71. #define rtc2_read(offset) readw(rtc2_base + (offset))
  72. #define rtc2_write(offset, value) writew((value), rtc2_base + (offset))
  73. static unsigned long epoch = 1970; /* Jan 1 1970 00:00:00 */
  74. static DEFINE_SPINLOCK(rtc_lock);
  75. static char rtc_name[] = "RTC";
  76. static unsigned long periodic_count;
  77. static unsigned int alarm_enabled;
  78. static int aie_irq;
  79. static int pie_irq;
  80. static inline time64_t read_elapsed_second(void)
  81. {
  82. unsigned long first_low, first_mid, first_high;
  83. unsigned long second_low, second_mid, second_high;
  84. do {
  85. first_low = rtc1_read(ETIMELREG);
  86. first_mid = rtc1_read(ETIMEMREG);
  87. first_high = rtc1_read(ETIMEHREG);
  88. second_low = rtc1_read(ETIMELREG);
  89. second_mid = rtc1_read(ETIMEMREG);
  90. second_high = rtc1_read(ETIMEHREG);
  91. } while (first_low != second_low || first_mid != second_mid ||
  92. first_high != second_high);
  93. return ((u64)first_high << 17) | (first_mid << 1) | (first_low >> 15);
  94. }
  95. static inline void write_elapsed_second(time64_t sec)
  96. {
  97. spin_lock_irq(&rtc_lock);
  98. rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
  99. rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
  100. rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));
  101. spin_unlock_irq(&rtc_lock);
  102. }
  103. static int vr41xx_rtc_read_time(struct device *dev, struct rtc_time *time)
  104. {
  105. time64_t epoch_sec, elapsed_sec;
  106. epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
  107. elapsed_sec = read_elapsed_second();
  108. rtc_time64_to_tm(epoch_sec + elapsed_sec, time);
  109. return 0;
  110. }
  111. static int vr41xx_rtc_set_time(struct device *dev, struct rtc_time *time)
  112. {
  113. time64_t epoch_sec, current_sec;
  114. epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
  115. current_sec = mktime64(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
  116. time->tm_hour, time->tm_min, time->tm_sec);
  117. write_elapsed_second(current_sec - epoch_sec);
  118. return 0;
  119. }
  120. static int vr41xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  121. {
  122. unsigned long low, mid, high;
  123. struct rtc_time *time = &wkalrm->time;
  124. spin_lock_irq(&rtc_lock);
  125. low = rtc1_read(ECMPLREG);
  126. mid = rtc1_read(ECMPMREG);
  127. high = rtc1_read(ECMPHREG);
  128. wkalrm->enabled = alarm_enabled;
  129. spin_unlock_irq(&rtc_lock);
  130. rtc_time_to_tm((high << 17) | (mid << 1) | (low >> 15), time);
  131. return 0;
  132. }
  133. static int vr41xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  134. {
  135. time64_t alarm_sec;
  136. struct rtc_time *time = &wkalrm->time;
  137. alarm_sec = mktime64(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
  138. time->tm_hour, time->tm_min, time->tm_sec);
  139. spin_lock_irq(&rtc_lock);
  140. if (alarm_enabled)
  141. disable_irq(aie_irq);
  142. rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
  143. rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
  144. rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));
  145. if (wkalrm->enabled)
  146. enable_irq(aie_irq);
  147. alarm_enabled = wkalrm->enabled;
  148. spin_unlock_irq(&rtc_lock);
  149. return 0;
  150. }
  151. static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
  152. {
  153. switch (cmd) {
  154. case RTC_EPOCH_READ:
  155. return put_user(epoch, (unsigned long __user *)arg);
  156. case RTC_EPOCH_SET:
  157. /* Doesn't support before 1900 */
  158. if (arg < 1900)
  159. return -EINVAL;
  160. epoch = arg;
  161. break;
  162. default:
  163. return -ENOIOCTLCMD;
  164. }
  165. return 0;
  166. }
  167. static int vr41xx_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  168. {
  169. spin_lock_irq(&rtc_lock);
  170. if (enabled) {
  171. if (!alarm_enabled) {
  172. enable_irq(aie_irq);
  173. alarm_enabled = 1;
  174. }
  175. } else {
  176. if (alarm_enabled) {
  177. disable_irq(aie_irq);
  178. alarm_enabled = 0;
  179. }
  180. }
  181. spin_unlock_irq(&rtc_lock);
  182. return 0;
  183. }
  184. static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id)
  185. {
  186. struct platform_device *pdev = (struct platform_device *)dev_id;
  187. struct rtc_device *rtc = platform_get_drvdata(pdev);
  188. rtc2_write(RTCINTREG, ELAPSEDTIME_INT);
  189. rtc_update_irq(rtc, 1, RTC_AF);
  190. return IRQ_HANDLED;
  191. }
  192. static irqreturn_t rtclong1_interrupt(int irq, void *dev_id)
  193. {
  194. struct platform_device *pdev = (struct platform_device *)dev_id;
  195. struct rtc_device *rtc = platform_get_drvdata(pdev);
  196. unsigned long count = periodic_count;
  197. rtc2_write(RTCINTREG, RTCLONG1_INT);
  198. rtc1_write(RTCL1LREG, count);
  199. rtc1_write(RTCL1HREG, count >> 16);
  200. rtc_update_irq(rtc, 1, RTC_PF);
  201. return IRQ_HANDLED;
  202. }
  203. static const struct rtc_class_ops vr41xx_rtc_ops = {
  204. .ioctl = vr41xx_rtc_ioctl,
  205. .read_time = vr41xx_rtc_read_time,
  206. .set_time = vr41xx_rtc_set_time,
  207. .read_alarm = vr41xx_rtc_read_alarm,
  208. .set_alarm = vr41xx_rtc_set_alarm,
  209. .alarm_irq_enable = vr41xx_rtc_alarm_irq_enable,
  210. };
  211. static int rtc_probe(struct platform_device *pdev)
  212. {
  213. struct resource *res;
  214. struct rtc_device *rtc;
  215. int retval;
  216. if (pdev->num_resources != 4)
  217. return -EBUSY;
  218. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  219. if (!res)
  220. return -EBUSY;
  221. rtc1_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
  222. if (!rtc1_base)
  223. return -EBUSY;
  224. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  225. if (!res) {
  226. retval = -EBUSY;
  227. goto err_rtc1_iounmap;
  228. }
  229. rtc2_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
  230. if (!rtc2_base) {
  231. retval = -EBUSY;
  232. goto err_rtc1_iounmap;
  233. }
  234. rtc = devm_rtc_allocate_device(&pdev->dev);
  235. if (IS_ERR(rtc)) {
  236. retval = PTR_ERR(rtc);
  237. goto err_iounmap_all;
  238. }
  239. rtc->ops = &vr41xx_rtc_ops;
  240. /* 48-bit counter at 32.768 kHz */
  241. rtc->range_max = (1ULL << 33) - 1;
  242. rtc->max_user_freq = MAX_PERIODIC_RATE;
  243. spin_lock_irq(&rtc_lock);
  244. rtc1_write(ECMPLREG, 0);
  245. rtc1_write(ECMPMREG, 0);
  246. rtc1_write(ECMPHREG, 0);
  247. rtc1_write(RTCL1LREG, 0);
  248. rtc1_write(RTCL1HREG, 0);
  249. spin_unlock_irq(&rtc_lock);
  250. aie_irq = platform_get_irq(pdev, 0);
  251. if (aie_irq <= 0) {
  252. retval = -EBUSY;
  253. goto err_iounmap_all;
  254. }
  255. retval = devm_request_irq(&pdev->dev, aie_irq, elapsedtime_interrupt, 0,
  256. "elapsed_time", pdev);
  257. if (retval < 0)
  258. goto err_iounmap_all;
  259. pie_irq = platform_get_irq(pdev, 1);
  260. if (pie_irq <= 0) {
  261. retval = -EBUSY;
  262. goto err_iounmap_all;
  263. }
  264. retval = devm_request_irq(&pdev->dev, pie_irq, rtclong1_interrupt, 0,
  265. "rtclong1", pdev);
  266. if (retval < 0)
  267. goto err_iounmap_all;
  268. platform_set_drvdata(pdev, rtc);
  269. disable_irq(aie_irq);
  270. disable_irq(pie_irq);
  271. dev_info(&pdev->dev, "Real Time Clock of NEC VR4100 series\n");
  272. retval = rtc_register_device(rtc);
  273. if (retval)
  274. goto err_iounmap_all;
  275. return 0;
  276. err_iounmap_all:
  277. rtc2_base = NULL;
  278. err_rtc1_iounmap:
  279. rtc1_base = NULL;
  280. return retval;
  281. }
  282. /* work with hotplug and coldplug */
  283. MODULE_ALIAS("platform:RTC");
  284. static struct platform_driver rtc_platform_driver = {
  285. .probe = rtc_probe,
  286. .driver = {
  287. .name = rtc_name,
  288. },
  289. };
  290. module_platform_driver(rtc_platform_driver);