rtc-twl.c 17 KB

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  1. /*
  2. * rtc-twl.c -- TWL Real Time Clock interface
  3. *
  4. * Copyright (C) 2007 MontaVista Software, Inc
  5. * Author: Alexandre Rusev <source@mvista.com>
  6. *
  7. * Based on original TI driver twl4030-rtc.c
  8. * Copyright (C) 2006 Texas Instruments, Inc.
  9. *
  10. * Based on rtc-omap.c
  11. * Copyright (C) 2003 MontaVista Software, Inc.
  12. * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
  13. * Copyright (C) 2006 David Brownell
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License
  17. * as published by the Free Software Foundation; either version
  18. * 2 of the License, or (at your option) any later version.
  19. */
  20. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21. #include <linux/kernel.h>
  22. #include <linux/errno.h>
  23. #include <linux/init.h>
  24. #include <linux/module.h>
  25. #include <linux/types.h>
  26. #include <linux/rtc.h>
  27. #include <linux/bcd.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/of.h>
  31. #include <linux/mfd/twl.h>
  32. enum twl_class {
  33. TWL_4030 = 0,
  34. TWL_6030,
  35. };
  36. /*
  37. * RTC block register offsets (use TWL_MODULE_RTC)
  38. */
  39. enum {
  40. REG_SECONDS_REG = 0,
  41. REG_MINUTES_REG,
  42. REG_HOURS_REG,
  43. REG_DAYS_REG,
  44. REG_MONTHS_REG,
  45. REG_YEARS_REG,
  46. REG_WEEKS_REG,
  47. REG_ALARM_SECONDS_REG,
  48. REG_ALARM_MINUTES_REG,
  49. REG_ALARM_HOURS_REG,
  50. REG_ALARM_DAYS_REG,
  51. REG_ALARM_MONTHS_REG,
  52. REG_ALARM_YEARS_REG,
  53. REG_RTC_CTRL_REG,
  54. REG_RTC_STATUS_REG,
  55. REG_RTC_INTERRUPTS_REG,
  56. REG_RTC_COMP_LSB_REG,
  57. REG_RTC_COMP_MSB_REG,
  58. };
  59. static const u8 twl4030_rtc_reg_map[] = {
  60. [REG_SECONDS_REG] = 0x00,
  61. [REG_MINUTES_REG] = 0x01,
  62. [REG_HOURS_REG] = 0x02,
  63. [REG_DAYS_REG] = 0x03,
  64. [REG_MONTHS_REG] = 0x04,
  65. [REG_YEARS_REG] = 0x05,
  66. [REG_WEEKS_REG] = 0x06,
  67. [REG_ALARM_SECONDS_REG] = 0x07,
  68. [REG_ALARM_MINUTES_REG] = 0x08,
  69. [REG_ALARM_HOURS_REG] = 0x09,
  70. [REG_ALARM_DAYS_REG] = 0x0A,
  71. [REG_ALARM_MONTHS_REG] = 0x0B,
  72. [REG_ALARM_YEARS_REG] = 0x0C,
  73. [REG_RTC_CTRL_REG] = 0x0D,
  74. [REG_RTC_STATUS_REG] = 0x0E,
  75. [REG_RTC_INTERRUPTS_REG] = 0x0F,
  76. [REG_RTC_COMP_LSB_REG] = 0x10,
  77. [REG_RTC_COMP_MSB_REG] = 0x11,
  78. };
  79. static const u8 twl6030_rtc_reg_map[] = {
  80. [REG_SECONDS_REG] = 0x00,
  81. [REG_MINUTES_REG] = 0x01,
  82. [REG_HOURS_REG] = 0x02,
  83. [REG_DAYS_REG] = 0x03,
  84. [REG_MONTHS_REG] = 0x04,
  85. [REG_YEARS_REG] = 0x05,
  86. [REG_WEEKS_REG] = 0x06,
  87. [REG_ALARM_SECONDS_REG] = 0x08,
  88. [REG_ALARM_MINUTES_REG] = 0x09,
  89. [REG_ALARM_HOURS_REG] = 0x0A,
  90. [REG_ALARM_DAYS_REG] = 0x0B,
  91. [REG_ALARM_MONTHS_REG] = 0x0C,
  92. [REG_ALARM_YEARS_REG] = 0x0D,
  93. [REG_RTC_CTRL_REG] = 0x10,
  94. [REG_RTC_STATUS_REG] = 0x11,
  95. [REG_RTC_INTERRUPTS_REG] = 0x12,
  96. [REG_RTC_COMP_LSB_REG] = 0x13,
  97. [REG_RTC_COMP_MSB_REG] = 0x14,
  98. };
  99. /* RTC_CTRL_REG bitfields */
  100. #define BIT_RTC_CTRL_REG_STOP_RTC_M 0x01
  101. #define BIT_RTC_CTRL_REG_ROUND_30S_M 0x02
  102. #define BIT_RTC_CTRL_REG_AUTO_COMP_M 0x04
  103. #define BIT_RTC_CTRL_REG_MODE_12_24_M 0x08
  104. #define BIT_RTC_CTRL_REG_TEST_MODE_M 0x10
  105. #define BIT_RTC_CTRL_REG_SET_32_COUNTER_M 0x20
  106. #define BIT_RTC_CTRL_REG_GET_TIME_M 0x40
  107. #define BIT_RTC_CTRL_REG_RTC_V_OPT 0x80
  108. /* RTC_STATUS_REG bitfields */
  109. #define BIT_RTC_STATUS_REG_RUN_M 0x02
  110. #define BIT_RTC_STATUS_REG_1S_EVENT_M 0x04
  111. #define BIT_RTC_STATUS_REG_1M_EVENT_M 0x08
  112. #define BIT_RTC_STATUS_REG_1H_EVENT_M 0x10
  113. #define BIT_RTC_STATUS_REG_1D_EVENT_M 0x20
  114. #define BIT_RTC_STATUS_REG_ALARM_M 0x40
  115. #define BIT_RTC_STATUS_REG_POWER_UP_M 0x80
  116. /* RTC_INTERRUPTS_REG bitfields */
  117. #define BIT_RTC_INTERRUPTS_REG_EVERY_M 0x03
  118. #define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M 0x04
  119. #define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M 0x08
  120. /* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
  121. #define ALL_TIME_REGS 6
  122. /*----------------------------------------------------------------------*/
  123. struct twl_rtc {
  124. struct device *dev;
  125. struct rtc_device *rtc;
  126. u8 *reg_map;
  127. /*
  128. * Cache the value for timer/alarm interrupts register; this is
  129. * only changed by callers holding rtc ops lock (or resume).
  130. */
  131. unsigned char rtc_irq_bits;
  132. bool wake_enabled;
  133. #ifdef CONFIG_PM_SLEEP
  134. unsigned char irqstat;
  135. #endif
  136. enum twl_class class;
  137. };
  138. /*
  139. * Supports 1 byte read from TWL RTC register.
  140. */
  141. static int twl_rtc_read_u8(struct twl_rtc *twl_rtc, u8 *data, u8 reg)
  142. {
  143. int ret;
  144. ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (twl_rtc->reg_map[reg]));
  145. if (ret < 0)
  146. pr_err("Could not read TWL register %X - error %d\n", reg, ret);
  147. return ret;
  148. }
  149. /*
  150. * Supports 1 byte write to TWL RTC registers.
  151. */
  152. static int twl_rtc_write_u8(struct twl_rtc *twl_rtc, u8 data, u8 reg)
  153. {
  154. int ret;
  155. ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (twl_rtc->reg_map[reg]));
  156. if (ret < 0)
  157. pr_err("Could not write TWL register %X - error %d\n",
  158. reg, ret);
  159. return ret;
  160. }
  161. /*
  162. * Enable 1/second update and/or alarm interrupts.
  163. */
  164. static int set_rtc_irq_bit(struct twl_rtc *twl_rtc, unsigned char bit)
  165. {
  166. unsigned char val;
  167. int ret;
  168. /* if the bit is set, return from here */
  169. if (twl_rtc->rtc_irq_bits & bit)
  170. return 0;
  171. val = twl_rtc->rtc_irq_bits | bit;
  172. val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M;
  173. ret = twl_rtc_write_u8(twl_rtc, val, REG_RTC_INTERRUPTS_REG);
  174. if (ret == 0)
  175. twl_rtc->rtc_irq_bits = val;
  176. return ret;
  177. }
  178. /*
  179. * Disable update and/or alarm interrupts.
  180. */
  181. static int mask_rtc_irq_bit(struct twl_rtc *twl_rtc, unsigned char bit)
  182. {
  183. unsigned char val;
  184. int ret;
  185. /* if the bit is clear, return from here */
  186. if (!(twl_rtc->rtc_irq_bits & bit))
  187. return 0;
  188. val = twl_rtc->rtc_irq_bits & ~bit;
  189. ret = twl_rtc_write_u8(twl_rtc, val, REG_RTC_INTERRUPTS_REG);
  190. if (ret == 0)
  191. twl_rtc->rtc_irq_bits = val;
  192. return ret;
  193. }
  194. static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
  195. {
  196. struct platform_device *pdev = to_platform_device(dev);
  197. struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
  198. int irq = platform_get_irq(pdev, 0);
  199. int ret;
  200. if (enabled) {
  201. ret = set_rtc_irq_bit(twl_rtc,
  202. BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
  203. if (device_can_wakeup(dev) && !twl_rtc->wake_enabled) {
  204. enable_irq_wake(irq);
  205. twl_rtc->wake_enabled = true;
  206. }
  207. } else {
  208. ret = mask_rtc_irq_bit(twl_rtc,
  209. BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
  210. if (twl_rtc->wake_enabled) {
  211. disable_irq_wake(irq);
  212. twl_rtc->wake_enabled = false;
  213. }
  214. }
  215. return ret;
  216. }
  217. /*
  218. * Gets current TWL RTC time and date parameters.
  219. *
  220. * The RTC's time/alarm representation is not what gmtime(3) requires
  221. * Linux to use:
  222. *
  223. * - Months are 1..12 vs Linux 0-11
  224. * - Years are 0..99 vs Linux 1900..N (we assume 21st century)
  225. */
  226. static int twl_rtc_read_time(struct device *dev, struct rtc_time *tm)
  227. {
  228. struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
  229. unsigned char rtc_data[ALL_TIME_REGS];
  230. int ret;
  231. u8 save_control;
  232. u8 rtc_control;
  233. ret = twl_rtc_read_u8(twl_rtc, &save_control, REG_RTC_CTRL_REG);
  234. if (ret < 0) {
  235. dev_err(dev, "%s: reading CTRL_REG, error %d\n", __func__, ret);
  236. return ret;
  237. }
  238. /* for twl6030/32 make sure BIT_RTC_CTRL_REG_GET_TIME_M is clear */
  239. if (twl_rtc->class == TWL_6030) {
  240. if (save_control & BIT_RTC_CTRL_REG_GET_TIME_M) {
  241. save_control &= ~BIT_RTC_CTRL_REG_GET_TIME_M;
  242. ret = twl_rtc_write_u8(twl_rtc, save_control,
  243. REG_RTC_CTRL_REG);
  244. if (ret < 0) {
  245. dev_err(dev, "%s clr GET_TIME, error %d\n",
  246. __func__, ret);
  247. return ret;
  248. }
  249. }
  250. }
  251. /* Copy RTC counting registers to static registers or latches */
  252. rtc_control = save_control | BIT_RTC_CTRL_REG_GET_TIME_M;
  253. /* for twl6030/32 enable read access to static shadowed registers */
  254. if (twl_rtc->class == TWL_6030)
  255. rtc_control |= BIT_RTC_CTRL_REG_RTC_V_OPT;
  256. ret = twl_rtc_write_u8(twl_rtc, rtc_control, REG_RTC_CTRL_REG);
  257. if (ret < 0) {
  258. dev_err(dev, "%s: writing CTRL_REG, error %d\n", __func__, ret);
  259. return ret;
  260. }
  261. ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
  262. (twl_rtc->reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
  263. if (ret < 0) {
  264. dev_err(dev, "%s: reading data, error %d\n", __func__, ret);
  265. return ret;
  266. }
  267. /* for twl6030 restore original state of rtc control register */
  268. if (twl_rtc->class == TWL_6030) {
  269. ret = twl_rtc_write_u8(twl_rtc, save_control, REG_RTC_CTRL_REG);
  270. if (ret < 0) {
  271. dev_err(dev, "%s: restore CTRL_REG, error %d\n",
  272. __func__, ret);
  273. return ret;
  274. }
  275. }
  276. tm->tm_sec = bcd2bin(rtc_data[0]);
  277. tm->tm_min = bcd2bin(rtc_data[1]);
  278. tm->tm_hour = bcd2bin(rtc_data[2]);
  279. tm->tm_mday = bcd2bin(rtc_data[3]);
  280. tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
  281. tm->tm_year = bcd2bin(rtc_data[5]) + 100;
  282. return ret;
  283. }
  284. static int twl_rtc_set_time(struct device *dev, struct rtc_time *tm)
  285. {
  286. struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
  287. unsigned char save_control;
  288. unsigned char rtc_data[ALL_TIME_REGS];
  289. int ret;
  290. rtc_data[0] = bin2bcd(tm->tm_sec);
  291. rtc_data[1] = bin2bcd(tm->tm_min);
  292. rtc_data[2] = bin2bcd(tm->tm_hour);
  293. rtc_data[3] = bin2bcd(tm->tm_mday);
  294. rtc_data[4] = bin2bcd(tm->tm_mon + 1);
  295. rtc_data[5] = bin2bcd(tm->tm_year - 100);
  296. /* Stop RTC while updating the TC registers */
  297. ret = twl_rtc_read_u8(twl_rtc, &save_control, REG_RTC_CTRL_REG);
  298. if (ret < 0)
  299. goto out;
  300. save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M;
  301. ret = twl_rtc_write_u8(twl_rtc, save_control, REG_RTC_CTRL_REG);
  302. if (ret < 0)
  303. goto out;
  304. /* update all the time registers in one shot */
  305. ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data,
  306. (twl_rtc->reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
  307. if (ret < 0) {
  308. dev_err(dev, "rtc_set_time error %d\n", ret);
  309. goto out;
  310. }
  311. /* Start back RTC */
  312. save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M;
  313. ret = twl_rtc_write_u8(twl_rtc, save_control, REG_RTC_CTRL_REG);
  314. out:
  315. return ret;
  316. }
  317. /*
  318. * Gets current TWL RTC alarm time.
  319. */
  320. static int twl_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
  321. {
  322. struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
  323. unsigned char rtc_data[ALL_TIME_REGS];
  324. int ret;
  325. ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
  326. twl_rtc->reg_map[REG_ALARM_SECONDS_REG], ALL_TIME_REGS);
  327. if (ret < 0) {
  328. dev_err(dev, "rtc_read_alarm error %d\n", ret);
  329. return ret;
  330. }
  331. /* some of these fields may be wildcard/"match all" */
  332. alm->time.tm_sec = bcd2bin(rtc_data[0]);
  333. alm->time.tm_min = bcd2bin(rtc_data[1]);
  334. alm->time.tm_hour = bcd2bin(rtc_data[2]);
  335. alm->time.tm_mday = bcd2bin(rtc_data[3]);
  336. alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1;
  337. alm->time.tm_year = bcd2bin(rtc_data[5]) + 100;
  338. /* report cached alarm enable state */
  339. if (twl_rtc->rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M)
  340. alm->enabled = 1;
  341. return ret;
  342. }
  343. static int twl_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
  344. {
  345. struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
  346. unsigned char alarm_data[ALL_TIME_REGS];
  347. int ret;
  348. ret = twl_rtc_alarm_irq_enable(dev, 0);
  349. if (ret)
  350. goto out;
  351. alarm_data[0] = bin2bcd(alm->time.tm_sec);
  352. alarm_data[1] = bin2bcd(alm->time.tm_min);
  353. alarm_data[2] = bin2bcd(alm->time.tm_hour);
  354. alarm_data[3] = bin2bcd(alm->time.tm_mday);
  355. alarm_data[4] = bin2bcd(alm->time.tm_mon + 1);
  356. alarm_data[5] = bin2bcd(alm->time.tm_year - 100);
  357. /* update all the alarm registers in one shot */
  358. ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data,
  359. twl_rtc->reg_map[REG_ALARM_SECONDS_REG], ALL_TIME_REGS);
  360. if (ret) {
  361. dev_err(dev, "rtc_set_alarm error %d\n", ret);
  362. goto out;
  363. }
  364. if (alm->enabled)
  365. ret = twl_rtc_alarm_irq_enable(dev, 1);
  366. out:
  367. return ret;
  368. }
  369. static irqreturn_t twl_rtc_interrupt(int irq, void *data)
  370. {
  371. struct twl_rtc *twl_rtc = data;
  372. unsigned long events;
  373. int ret = IRQ_NONE;
  374. int res;
  375. u8 rd_reg;
  376. res = twl_rtc_read_u8(twl_rtc, &rd_reg, REG_RTC_STATUS_REG);
  377. if (res)
  378. goto out;
  379. /*
  380. * Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG.
  381. * only one (ALARM or RTC) interrupt source may be enabled
  382. * at time, we also could check our results
  383. * by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM]
  384. */
  385. if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
  386. events = RTC_IRQF | RTC_AF;
  387. else
  388. events = RTC_IRQF | RTC_PF;
  389. res = twl_rtc_write_u8(twl_rtc, BIT_RTC_STATUS_REG_ALARM_M,
  390. REG_RTC_STATUS_REG);
  391. if (res)
  392. goto out;
  393. if (twl_rtc->class == TWL_4030) {
  394. /* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1
  395. * needs 2 reads to clear the interrupt. One read is done in
  396. * do_twl_pwrirq(). Doing the second read, to clear
  397. * the bit.
  398. *
  399. * FIXME the reason PWR_ISR1 needs an extra read is that
  400. * RTC_IF retriggered until we cleared REG_ALARM_M above.
  401. * But re-reading like this is a bad hack; by doing so we
  402. * risk wrongly clearing status for some other IRQ (losing
  403. * the interrupt). Be smarter about handling RTC_UF ...
  404. */
  405. res = twl_i2c_read_u8(TWL4030_MODULE_INT,
  406. &rd_reg, TWL4030_INT_PWR_ISR1);
  407. if (res)
  408. goto out;
  409. }
  410. /* Notify RTC core on event */
  411. rtc_update_irq(twl_rtc->rtc, 1, events);
  412. ret = IRQ_HANDLED;
  413. out:
  414. return ret;
  415. }
  416. static const struct rtc_class_ops twl_rtc_ops = {
  417. .read_time = twl_rtc_read_time,
  418. .set_time = twl_rtc_set_time,
  419. .read_alarm = twl_rtc_read_alarm,
  420. .set_alarm = twl_rtc_set_alarm,
  421. .alarm_irq_enable = twl_rtc_alarm_irq_enable,
  422. };
  423. /*----------------------------------------------------------------------*/
  424. static int twl_rtc_probe(struct platform_device *pdev)
  425. {
  426. struct twl_rtc *twl_rtc;
  427. struct device_node *np = pdev->dev.of_node;
  428. int ret = -EINVAL;
  429. int irq = platform_get_irq(pdev, 0);
  430. u8 rd_reg;
  431. if (!np) {
  432. dev_err(&pdev->dev, "no DT info\n");
  433. return -EINVAL;
  434. }
  435. if (irq <= 0)
  436. return ret;
  437. twl_rtc = devm_kzalloc(&pdev->dev, sizeof(*twl_rtc), GFP_KERNEL);
  438. if (!twl_rtc)
  439. return -ENOMEM;
  440. if (twl_class_is_4030()) {
  441. twl_rtc->class = TWL_4030;
  442. twl_rtc->reg_map = (u8 *)twl4030_rtc_reg_map;
  443. } else if (twl_class_is_6030()) {
  444. twl_rtc->class = TWL_6030;
  445. twl_rtc->reg_map = (u8 *)twl6030_rtc_reg_map;
  446. } else {
  447. dev_err(&pdev->dev, "TWL Class not supported.\n");
  448. return -EINVAL;
  449. }
  450. ret = twl_rtc_read_u8(twl_rtc, &rd_reg, REG_RTC_STATUS_REG);
  451. if (ret < 0)
  452. return ret;
  453. if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M)
  454. dev_warn(&pdev->dev, "Power up reset detected.\n");
  455. if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
  456. dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n");
  457. /* Clear RTC Power up reset and pending alarm interrupts */
  458. ret = twl_rtc_write_u8(twl_rtc, rd_reg, REG_RTC_STATUS_REG);
  459. if (ret < 0)
  460. return ret;
  461. if (twl_rtc->class == TWL_6030) {
  462. twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
  463. REG_INT_MSK_LINE_A);
  464. twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
  465. REG_INT_MSK_STS_A);
  466. }
  467. dev_info(&pdev->dev, "Enabling TWL-RTC\n");
  468. ret = twl_rtc_write_u8(twl_rtc, BIT_RTC_CTRL_REG_STOP_RTC_M,
  469. REG_RTC_CTRL_REG);
  470. if (ret < 0)
  471. return ret;
  472. /* ensure interrupts are disabled, bootloaders can be strange */
  473. ret = twl_rtc_write_u8(twl_rtc, 0, REG_RTC_INTERRUPTS_REG);
  474. if (ret < 0)
  475. dev_warn(&pdev->dev, "unable to disable interrupt\n");
  476. /* init cached IRQ enable bits */
  477. ret = twl_rtc_read_u8(twl_rtc, &twl_rtc->rtc_irq_bits,
  478. REG_RTC_INTERRUPTS_REG);
  479. if (ret < 0)
  480. return ret;
  481. platform_set_drvdata(pdev, twl_rtc);
  482. device_init_wakeup(&pdev->dev, 1);
  483. twl_rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
  484. &twl_rtc_ops, THIS_MODULE);
  485. if (IS_ERR(twl_rtc->rtc)) {
  486. dev_err(&pdev->dev, "can't register RTC device, err %ld\n",
  487. PTR_ERR(twl_rtc->rtc));
  488. return PTR_ERR(twl_rtc->rtc);
  489. }
  490. ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
  491. twl_rtc_interrupt,
  492. IRQF_TRIGGER_RISING | IRQF_ONESHOT,
  493. dev_name(&twl_rtc->rtc->dev), twl_rtc);
  494. if (ret < 0) {
  495. dev_err(&pdev->dev, "IRQ is not free.\n");
  496. return ret;
  497. }
  498. return 0;
  499. }
  500. /*
  501. * Disable all TWL RTC module interrupts.
  502. * Sets status flag to free.
  503. */
  504. static int twl_rtc_remove(struct platform_device *pdev)
  505. {
  506. struct twl_rtc *twl_rtc = platform_get_drvdata(pdev);
  507. /* leave rtc running, but disable irqs */
  508. mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
  509. mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
  510. if (twl_rtc->class == TWL_6030) {
  511. twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
  512. REG_INT_MSK_LINE_A);
  513. twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
  514. REG_INT_MSK_STS_A);
  515. }
  516. return 0;
  517. }
  518. static void twl_rtc_shutdown(struct platform_device *pdev)
  519. {
  520. struct twl_rtc *twl_rtc = platform_get_drvdata(pdev);
  521. /* mask timer interrupts, but leave alarm interrupts on to enable
  522. power-on when alarm is triggered */
  523. mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
  524. }
  525. #ifdef CONFIG_PM_SLEEP
  526. static int twl_rtc_suspend(struct device *dev)
  527. {
  528. struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
  529. twl_rtc->irqstat = twl_rtc->rtc_irq_bits;
  530. mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
  531. return 0;
  532. }
  533. static int twl_rtc_resume(struct device *dev)
  534. {
  535. struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
  536. set_rtc_irq_bit(twl_rtc, twl_rtc->irqstat);
  537. return 0;
  538. }
  539. #endif
  540. static SIMPLE_DEV_PM_OPS(twl_rtc_pm_ops, twl_rtc_suspend, twl_rtc_resume);
  541. static const struct of_device_id twl_rtc_of_match[] = {
  542. {.compatible = "ti,twl4030-rtc", },
  543. { },
  544. };
  545. MODULE_DEVICE_TABLE(of, twl_rtc_of_match);
  546. static struct platform_driver twl4030rtc_driver = {
  547. .probe = twl_rtc_probe,
  548. .remove = twl_rtc_remove,
  549. .shutdown = twl_rtc_shutdown,
  550. .driver = {
  551. .name = "twl_rtc",
  552. .pm = &twl_rtc_pm_ops,
  553. .of_match_table = twl_rtc_of_match,
  554. },
  555. };
  556. module_platform_driver(twl4030rtc_driver);
  557. MODULE_AUTHOR("Texas Instruments, MontaVista Software");
  558. MODULE_LICENSE("GPL");