rtc-pm8xxx.c 14 KB

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  1. /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/of.h>
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/rtc.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pm.h>
  18. #include <linux/regmap.h>
  19. #include <linux/slab.h>
  20. #include <linux/spinlock.h>
  21. /* RTC Register offsets from RTC CTRL REG */
  22. #define PM8XXX_ALARM_CTRL_OFFSET 0x01
  23. #define PM8XXX_RTC_WRITE_OFFSET 0x02
  24. #define PM8XXX_RTC_READ_OFFSET 0x06
  25. #define PM8XXX_ALARM_RW_OFFSET 0x0A
  26. /* RTC_CTRL register bit fields */
  27. #define PM8xxx_RTC_ENABLE BIT(7)
  28. #define PM8xxx_RTC_ALARM_CLEAR BIT(0)
  29. #define NUM_8_BIT_RTC_REGS 0x4
  30. /**
  31. * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
  32. * @ctrl: base address of control register
  33. * @write: base address of write register
  34. * @read: base address of read register
  35. * @alarm_ctrl: base address of alarm control register
  36. * @alarm_ctrl2: base address of alarm control2 register
  37. * @alarm_rw: base address of alarm read-write register
  38. * @alarm_en: alarm enable mask
  39. */
  40. struct pm8xxx_rtc_regs {
  41. unsigned int ctrl;
  42. unsigned int write;
  43. unsigned int read;
  44. unsigned int alarm_ctrl;
  45. unsigned int alarm_ctrl2;
  46. unsigned int alarm_rw;
  47. unsigned int alarm_en;
  48. };
  49. /**
  50. * struct pm8xxx_rtc - rtc driver internal structure
  51. * @rtc: rtc device for this driver.
  52. * @regmap: regmap used to access RTC registers
  53. * @allow_set_time: indicates whether writing to the RTC is allowed
  54. * @rtc_alarm_irq: rtc alarm irq number.
  55. * @ctrl_reg: rtc control register.
  56. * @rtc_dev: device structure.
  57. * @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
  58. */
  59. struct pm8xxx_rtc {
  60. struct rtc_device *rtc;
  61. struct regmap *regmap;
  62. bool allow_set_time;
  63. int rtc_alarm_irq;
  64. const struct pm8xxx_rtc_regs *regs;
  65. struct device *rtc_dev;
  66. spinlock_t ctrl_reg_lock;
  67. };
  68. /*
  69. * Steps to write the RTC registers.
  70. * 1. Disable alarm if enabled.
  71. * 2. Disable rtc if enabled.
  72. * 3. Write 0x00 to LSB.
  73. * 4. Write Byte[1], Byte[2], Byte[3] then Byte[0].
  74. * 5. Enable rtc if disabled in step 2.
  75. * 6. Enable alarm if disabled in step 1.
  76. */
  77. static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
  78. {
  79. int rc, i;
  80. unsigned long secs, irq_flags;
  81. u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, rtc_disabled = 0;
  82. unsigned int ctrl_reg, rtc_ctrl_reg;
  83. struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
  84. const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
  85. if (!rtc_dd->allow_set_time)
  86. return -EACCES;
  87. rtc_tm_to_time(tm, &secs);
  88. dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
  89. for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
  90. value[i] = secs & 0xFF;
  91. secs >>= 8;
  92. }
  93. spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
  94. rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
  95. if (rc)
  96. goto rtc_rw_fail;
  97. if (ctrl_reg & regs->alarm_en) {
  98. alarm_enabled = 1;
  99. ctrl_reg &= ~regs->alarm_en;
  100. rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
  101. if (rc) {
  102. dev_err(dev, "Write to RTC Alarm control register failed\n");
  103. goto rtc_rw_fail;
  104. }
  105. }
  106. /* Disable RTC H/w before writing on RTC register */
  107. rc = regmap_read(rtc_dd->regmap, regs->ctrl, &rtc_ctrl_reg);
  108. if (rc)
  109. goto rtc_rw_fail;
  110. if (rtc_ctrl_reg & PM8xxx_RTC_ENABLE) {
  111. rtc_disabled = 1;
  112. rtc_ctrl_reg &= ~PM8xxx_RTC_ENABLE;
  113. rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
  114. if (rc) {
  115. dev_err(dev, "Write to RTC control register failed\n");
  116. goto rtc_rw_fail;
  117. }
  118. }
  119. /* Write 0 to Byte[0] */
  120. rc = regmap_write(rtc_dd->regmap, regs->write, 0);
  121. if (rc) {
  122. dev_err(dev, "Write to RTC write data register failed\n");
  123. goto rtc_rw_fail;
  124. }
  125. /* Write Byte[1], Byte[2], Byte[3] */
  126. rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
  127. &value[1], sizeof(value) - 1);
  128. if (rc) {
  129. dev_err(dev, "Write to RTC write data register failed\n");
  130. goto rtc_rw_fail;
  131. }
  132. /* Write Byte[0] */
  133. rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
  134. if (rc) {
  135. dev_err(dev, "Write to RTC write data register failed\n");
  136. goto rtc_rw_fail;
  137. }
  138. /* Enable RTC H/w after writing on RTC register */
  139. if (rtc_disabled) {
  140. rtc_ctrl_reg |= PM8xxx_RTC_ENABLE;
  141. rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
  142. if (rc) {
  143. dev_err(dev, "Write to RTC control register failed\n");
  144. goto rtc_rw_fail;
  145. }
  146. }
  147. if (alarm_enabled) {
  148. ctrl_reg |= regs->alarm_en;
  149. rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
  150. if (rc) {
  151. dev_err(dev, "Write to RTC Alarm control register failed\n");
  152. goto rtc_rw_fail;
  153. }
  154. }
  155. rtc_rw_fail:
  156. spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
  157. return rc;
  158. }
  159. static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
  160. {
  161. int rc;
  162. u8 value[NUM_8_BIT_RTC_REGS];
  163. unsigned long secs;
  164. unsigned int reg;
  165. struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
  166. const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
  167. rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
  168. if (rc) {
  169. dev_err(dev, "RTC read data register failed\n");
  170. return rc;
  171. }
  172. /*
  173. * Read the LSB again and check if there has been a carry over.
  174. * If there is, redo the read operation.
  175. */
  176. rc = regmap_read(rtc_dd->regmap, regs->read, &reg);
  177. if (rc < 0) {
  178. dev_err(dev, "RTC read data register failed\n");
  179. return rc;
  180. }
  181. if (unlikely(reg < value[0])) {
  182. rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
  183. value, sizeof(value));
  184. if (rc) {
  185. dev_err(dev, "RTC read data register failed\n");
  186. return rc;
  187. }
  188. }
  189. secs = value[0] | (value[1] << 8) | (value[2] << 16) |
  190. ((unsigned long)value[3] << 24);
  191. rtc_time_to_tm(secs, tm);
  192. dev_dbg(dev, "secs = %lu, h:m:s == %d:%d:%d, d/m/y = %d/%d/%d\n",
  193. secs, tm->tm_hour, tm->tm_min, tm->tm_sec,
  194. tm->tm_mday, tm->tm_mon, tm->tm_year);
  195. return 0;
  196. }
  197. static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  198. {
  199. int rc, i;
  200. u8 value[NUM_8_BIT_RTC_REGS];
  201. unsigned int ctrl_reg;
  202. unsigned long secs, irq_flags;
  203. struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
  204. const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
  205. rtc_tm_to_time(&alarm->time, &secs);
  206. for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
  207. value[i] = secs & 0xFF;
  208. secs >>= 8;
  209. }
  210. spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
  211. rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
  212. sizeof(value));
  213. if (rc) {
  214. dev_err(dev, "Write to RTC ALARM register failed\n");
  215. goto rtc_rw_fail;
  216. }
  217. rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
  218. if (rc)
  219. goto rtc_rw_fail;
  220. if (alarm->enabled)
  221. ctrl_reg |= regs->alarm_en;
  222. else
  223. ctrl_reg &= ~regs->alarm_en;
  224. rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
  225. if (rc) {
  226. dev_err(dev, "Write to RTC alarm control register failed\n");
  227. goto rtc_rw_fail;
  228. }
  229. dev_dbg(dev, "Alarm Set for h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
  230. alarm->time.tm_hour, alarm->time.tm_min,
  231. alarm->time.tm_sec, alarm->time.tm_mday,
  232. alarm->time.tm_mon, alarm->time.tm_year);
  233. rtc_rw_fail:
  234. spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
  235. return rc;
  236. }
  237. static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  238. {
  239. int rc;
  240. u8 value[NUM_8_BIT_RTC_REGS];
  241. unsigned long secs;
  242. struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
  243. const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
  244. rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
  245. sizeof(value));
  246. if (rc) {
  247. dev_err(dev, "RTC alarm time read failed\n");
  248. return rc;
  249. }
  250. secs = value[0] | (value[1] << 8) | (value[2] << 16) |
  251. ((unsigned long)value[3] << 24);
  252. rtc_time_to_tm(secs, &alarm->time);
  253. rc = rtc_valid_tm(&alarm->time);
  254. if (rc < 0) {
  255. dev_err(dev, "Invalid alarm time read from RTC\n");
  256. return rc;
  257. }
  258. dev_dbg(dev, "Alarm set for - h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
  259. alarm->time.tm_hour, alarm->time.tm_min,
  260. alarm->time.tm_sec, alarm->time.tm_mday,
  261. alarm->time.tm_mon, alarm->time.tm_year);
  262. return 0;
  263. }
  264. static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
  265. {
  266. int rc;
  267. unsigned long irq_flags;
  268. struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
  269. const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
  270. unsigned int ctrl_reg;
  271. spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
  272. rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
  273. if (rc)
  274. goto rtc_rw_fail;
  275. if (enable)
  276. ctrl_reg |= regs->alarm_en;
  277. else
  278. ctrl_reg &= ~regs->alarm_en;
  279. rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
  280. if (rc) {
  281. dev_err(dev, "Write to RTC control register failed\n");
  282. goto rtc_rw_fail;
  283. }
  284. rtc_rw_fail:
  285. spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
  286. return rc;
  287. }
  288. static const struct rtc_class_ops pm8xxx_rtc_ops = {
  289. .read_time = pm8xxx_rtc_read_time,
  290. .set_time = pm8xxx_rtc_set_time,
  291. .set_alarm = pm8xxx_rtc_set_alarm,
  292. .read_alarm = pm8xxx_rtc_read_alarm,
  293. .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
  294. };
  295. static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
  296. {
  297. struct pm8xxx_rtc *rtc_dd = dev_id;
  298. const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
  299. unsigned int ctrl_reg;
  300. int rc;
  301. unsigned long irq_flags;
  302. rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
  303. spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
  304. /* Clear the alarm enable bit */
  305. rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
  306. if (rc) {
  307. spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
  308. goto rtc_alarm_handled;
  309. }
  310. ctrl_reg &= ~regs->alarm_en;
  311. rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
  312. if (rc) {
  313. spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
  314. dev_err(rtc_dd->rtc_dev,
  315. "Write to alarm control register failed\n");
  316. goto rtc_alarm_handled;
  317. }
  318. spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
  319. /* Clear RTC alarm register */
  320. rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
  321. if (rc) {
  322. dev_err(rtc_dd->rtc_dev,
  323. "RTC Alarm control2 register read failed\n");
  324. goto rtc_alarm_handled;
  325. }
  326. ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
  327. rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
  328. if (rc)
  329. dev_err(rtc_dd->rtc_dev,
  330. "Write to RTC Alarm control2 register failed\n");
  331. rtc_alarm_handled:
  332. return IRQ_HANDLED;
  333. }
  334. static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
  335. {
  336. const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
  337. unsigned int ctrl_reg;
  338. int rc;
  339. /* Check if the RTC is on, else turn it on */
  340. rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
  341. if (rc)
  342. return rc;
  343. if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
  344. ctrl_reg |= PM8xxx_RTC_ENABLE;
  345. rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
  346. if (rc)
  347. return rc;
  348. }
  349. return 0;
  350. }
  351. static const struct pm8xxx_rtc_regs pm8921_regs = {
  352. .ctrl = 0x11d,
  353. .write = 0x11f,
  354. .read = 0x123,
  355. .alarm_rw = 0x127,
  356. .alarm_ctrl = 0x11d,
  357. .alarm_ctrl2 = 0x11e,
  358. .alarm_en = BIT(1),
  359. };
  360. static const struct pm8xxx_rtc_regs pm8058_regs = {
  361. .ctrl = 0x1e8,
  362. .write = 0x1ea,
  363. .read = 0x1ee,
  364. .alarm_rw = 0x1f2,
  365. .alarm_ctrl = 0x1e8,
  366. .alarm_ctrl2 = 0x1e9,
  367. .alarm_en = BIT(1),
  368. };
  369. static const struct pm8xxx_rtc_regs pm8941_regs = {
  370. .ctrl = 0x6046,
  371. .write = 0x6040,
  372. .read = 0x6048,
  373. .alarm_rw = 0x6140,
  374. .alarm_ctrl = 0x6146,
  375. .alarm_ctrl2 = 0x6148,
  376. .alarm_en = BIT(7),
  377. };
  378. /*
  379. * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
  380. */
  381. static const struct of_device_id pm8xxx_id_table[] = {
  382. { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
  383. { .compatible = "qcom,pm8018-rtc", .data = &pm8921_regs },
  384. { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
  385. { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
  386. { },
  387. };
  388. MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
  389. static int pm8xxx_rtc_probe(struct platform_device *pdev)
  390. {
  391. int rc;
  392. struct pm8xxx_rtc *rtc_dd;
  393. const struct of_device_id *match;
  394. match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
  395. if (!match)
  396. return -ENXIO;
  397. rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
  398. if (rtc_dd == NULL)
  399. return -ENOMEM;
  400. /* Initialise spinlock to protect RTC control register */
  401. spin_lock_init(&rtc_dd->ctrl_reg_lock);
  402. rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
  403. if (!rtc_dd->regmap) {
  404. dev_err(&pdev->dev, "Parent regmap unavailable.\n");
  405. return -ENXIO;
  406. }
  407. rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
  408. if (rtc_dd->rtc_alarm_irq < 0) {
  409. dev_err(&pdev->dev, "Alarm IRQ resource absent!\n");
  410. return -ENXIO;
  411. }
  412. rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
  413. "allow-set-time");
  414. rtc_dd->regs = match->data;
  415. rtc_dd->rtc_dev = &pdev->dev;
  416. rc = pm8xxx_rtc_enable(rtc_dd);
  417. if (rc)
  418. return rc;
  419. platform_set_drvdata(pdev, rtc_dd);
  420. device_init_wakeup(&pdev->dev, 1);
  421. /* Register the RTC device */
  422. rtc_dd->rtc = devm_rtc_device_register(&pdev->dev, "pm8xxx_rtc",
  423. &pm8xxx_rtc_ops, THIS_MODULE);
  424. if (IS_ERR(rtc_dd->rtc)) {
  425. dev_err(&pdev->dev, "%s: RTC registration failed (%ld)\n",
  426. __func__, PTR_ERR(rtc_dd->rtc));
  427. return PTR_ERR(rtc_dd->rtc);
  428. }
  429. /* Request the alarm IRQ */
  430. rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
  431. pm8xxx_alarm_trigger,
  432. IRQF_TRIGGER_RISING,
  433. "pm8xxx_rtc_alarm", rtc_dd);
  434. if (rc < 0) {
  435. dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
  436. return rc;
  437. }
  438. dev_dbg(&pdev->dev, "Probe success !!\n");
  439. return 0;
  440. }
  441. #ifdef CONFIG_PM_SLEEP
  442. static int pm8xxx_rtc_resume(struct device *dev)
  443. {
  444. struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
  445. if (device_may_wakeup(dev))
  446. disable_irq_wake(rtc_dd->rtc_alarm_irq);
  447. return 0;
  448. }
  449. static int pm8xxx_rtc_suspend(struct device *dev)
  450. {
  451. struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
  452. if (device_may_wakeup(dev))
  453. enable_irq_wake(rtc_dd->rtc_alarm_irq);
  454. return 0;
  455. }
  456. #endif
  457. static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops,
  458. pm8xxx_rtc_suspend,
  459. pm8xxx_rtc_resume);
  460. static struct platform_driver pm8xxx_rtc_driver = {
  461. .probe = pm8xxx_rtc_probe,
  462. .driver = {
  463. .name = "rtc-pm8xxx",
  464. .pm = &pm8xxx_rtc_pm_ops,
  465. .of_match_table = pm8xxx_id_table,
  466. },
  467. };
  468. module_platform_driver(pm8xxx_rtc_driver);
  469. MODULE_ALIAS("platform:rtc-pm8xxx");
  470. MODULE_DESCRIPTION("PMIC8xxx RTC driver");
  471. MODULE_LICENSE("GPL v2");
  472. MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");