rtc-mcp795.c 12 KB

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  1. /*
  2. * SPI Driver for Microchip MCP795 RTC
  3. *
  4. * Copyright (C) Josef Gajdusek <atx@atx.name>
  5. *
  6. * based on other Linux RTC drivers
  7. *
  8. * Device datasheet:
  9. * http://ww1.microchip.com/downloads/en/DeviceDoc/22280A.pdf
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. *
  15. */
  16. #include <linux/module.h>
  17. #include <linux/kernel.h>
  18. #include <linux/device.h>
  19. #include <linux/printk.h>
  20. #include <linux/spi/spi.h>
  21. #include <linux/rtc.h>
  22. #include <linux/of.h>
  23. #include <linux/bcd.h>
  24. #include <linux/delay.h>
  25. /* MCP795 Instructions, see datasheet table 3-1 */
  26. #define MCP795_EEREAD 0x03
  27. #define MCP795_EEWRITE 0x02
  28. #define MCP795_EEWRDI 0x04
  29. #define MCP795_EEWREN 0x06
  30. #define MCP795_SRREAD 0x05
  31. #define MCP795_SRWRITE 0x01
  32. #define MCP795_READ 0x13
  33. #define MCP795_WRITE 0x12
  34. #define MCP795_UNLOCK 0x14
  35. #define MCP795_IDWRITE 0x32
  36. #define MCP795_IDREAD 0x33
  37. #define MCP795_CLRWDT 0x44
  38. #define MCP795_CLRRAM 0x54
  39. /* MCP795 RTCC registers, see datasheet table 4-1 */
  40. #define MCP795_REG_SECONDS 0x01
  41. #define MCP795_REG_DAY 0x04
  42. #define MCP795_REG_MONTH 0x06
  43. #define MCP795_REG_CONTROL 0x08
  44. #define MCP795_REG_ALM0_SECONDS 0x0C
  45. #define MCP795_REG_ALM0_DAY 0x0F
  46. #define MCP795_ST_BIT BIT(7)
  47. #define MCP795_24_BIT BIT(6)
  48. #define MCP795_LP_BIT BIT(5)
  49. #define MCP795_EXTOSC_BIT BIT(3)
  50. #define MCP795_OSCON_BIT BIT(5)
  51. #define MCP795_ALM0_BIT BIT(4)
  52. #define MCP795_ALM1_BIT BIT(5)
  53. #define MCP795_ALM0IF_BIT BIT(3)
  54. #define MCP795_ALM0C0_BIT BIT(4)
  55. #define MCP795_ALM0C1_BIT BIT(5)
  56. #define MCP795_ALM0C2_BIT BIT(6)
  57. #define SEC_PER_DAY (24 * 60 * 60)
  58. static int mcp795_rtcc_read(struct device *dev, u8 addr, u8 *buf, u8 count)
  59. {
  60. struct spi_device *spi = to_spi_device(dev);
  61. int ret;
  62. u8 tx[2];
  63. tx[0] = MCP795_READ;
  64. tx[1] = addr;
  65. ret = spi_write_then_read(spi, tx, sizeof(tx), buf, count);
  66. if (ret)
  67. dev_err(dev, "Failed reading %d bytes from address %x.\n",
  68. count, addr);
  69. return ret;
  70. }
  71. static int mcp795_rtcc_write(struct device *dev, u8 addr, u8 *data, u8 count)
  72. {
  73. struct spi_device *spi = to_spi_device(dev);
  74. int ret;
  75. u8 tx[257];
  76. tx[0] = MCP795_WRITE;
  77. tx[1] = addr;
  78. memcpy(&tx[2], data, count);
  79. ret = spi_write(spi, tx, 2 + count);
  80. if (ret)
  81. dev_err(dev, "Failed to write %d bytes to address %x.\n",
  82. count, addr);
  83. return ret;
  84. }
  85. static int mcp795_rtcc_set_bits(struct device *dev, u8 addr, u8 mask, u8 state)
  86. {
  87. int ret;
  88. u8 tmp;
  89. ret = mcp795_rtcc_read(dev, addr, &tmp, 1);
  90. if (ret)
  91. return ret;
  92. if ((tmp & mask) != state) {
  93. tmp = (tmp & ~mask) | state;
  94. ret = mcp795_rtcc_write(dev, addr, &tmp, 1);
  95. }
  96. return ret;
  97. }
  98. static int mcp795_stop_oscillator(struct device *dev, bool *extosc)
  99. {
  100. int retries = 5;
  101. int ret;
  102. u8 data;
  103. ret = mcp795_rtcc_set_bits(dev, MCP795_REG_SECONDS, MCP795_ST_BIT, 0);
  104. if (ret)
  105. return ret;
  106. ret = mcp795_rtcc_read(dev, MCP795_REG_CONTROL, &data, 1);
  107. if (ret)
  108. return ret;
  109. *extosc = !!(data & MCP795_EXTOSC_BIT);
  110. ret = mcp795_rtcc_set_bits(
  111. dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, 0);
  112. if (ret)
  113. return ret;
  114. /* wait for the OSCON bit to clear */
  115. do {
  116. usleep_range(700, 800);
  117. ret = mcp795_rtcc_read(dev, MCP795_REG_DAY, &data, 1);
  118. if (ret)
  119. break;
  120. if (!(data & MCP795_OSCON_BIT))
  121. break;
  122. } while (--retries);
  123. return !retries ? -EIO : ret;
  124. }
  125. static int mcp795_start_oscillator(struct device *dev, bool *extosc)
  126. {
  127. if (extosc) {
  128. u8 data = *extosc ? MCP795_EXTOSC_BIT : 0;
  129. int ret;
  130. ret = mcp795_rtcc_set_bits(
  131. dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, data);
  132. if (ret)
  133. return ret;
  134. }
  135. return mcp795_rtcc_set_bits(
  136. dev, MCP795_REG_SECONDS, MCP795_ST_BIT, MCP795_ST_BIT);
  137. }
  138. /* Enable or disable Alarm 0 in RTC */
  139. static int mcp795_update_alarm(struct device *dev, bool enable)
  140. {
  141. int ret;
  142. dev_dbg(dev, "%s alarm\n", enable ? "Enable" : "Disable");
  143. if (enable) {
  144. /* clear ALM0IF (Alarm 0 Interrupt Flag) bit */
  145. ret = mcp795_rtcc_set_bits(dev, MCP795_REG_ALM0_DAY,
  146. MCP795_ALM0IF_BIT, 0);
  147. if (ret)
  148. return ret;
  149. /* enable alarm 0 */
  150. ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
  151. MCP795_ALM0_BIT, MCP795_ALM0_BIT);
  152. } else {
  153. /* disable alarm 0 and alarm 1 */
  154. ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
  155. MCP795_ALM0_BIT | MCP795_ALM1_BIT, 0);
  156. }
  157. return ret;
  158. }
  159. static int mcp795_set_time(struct device *dev, struct rtc_time *tim)
  160. {
  161. int ret;
  162. u8 data[7];
  163. bool extosc;
  164. /* Stop RTC and store current value of EXTOSC bit */
  165. ret = mcp795_stop_oscillator(dev, &extosc);
  166. if (ret)
  167. return ret;
  168. /* Read first, so we can leave config bits untouched */
  169. ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
  170. if (ret)
  171. return ret;
  172. data[0] = (data[0] & 0x80) | bin2bcd(tim->tm_sec);
  173. data[1] = (data[1] & 0x80) | bin2bcd(tim->tm_min);
  174. data[2] = bin2bcd(tim->tm_hour);
  175. data[3] = (data[3] & 0xF8) | bin2bcd(tim->tm_wday + 1);
  176. data[4] = bin2bcd(tim->tm_mday);
  177. data[5] = (data[5] & MCP795_LP_BIT) | bin2bcd(tim->tm_mon + 1);
  178. if (tim->tm_year > 100)
  179. tim->tm_year -= 100;
  180. data[6] = bin2bcd(tim->tm_year);
  181. /* Always write the date and month using a separate Write command.
  182. * This is a workaround for a know silicon issue that some combinations
  183. * of date and month values may result in the date being reset to 1.
  184. */
  185. ret = mcp795_rtcc_write(dev, MCP795_REG_SECONDS, data, 5);
  186. if (ret)
  187. return ret;
  188. ret = mcp795_rtcc_write(dev, MCP795_REG_MONTH, &data[5], 2);
  189. if (ret)
  190. return ret;
  191. /* Start back RTC and restore previous value of EXTOSC bit.
  192. * There is no need to clear EXTOSC bit when the previous value was 0
  193. * because it was already cleared when stopping the RTC oscillator.
  194. */
  195. ret = mcp795_start_oscillator(dev, extosc ? &extosc : NULL);
  196. if (ret)
  197. return ret;
  198. dev_dbg(dev, "Set mcp795: %04d-%02d-%02d(%d) %02d:%02d:%02d\n",
  199. tim->tm_year + 1900, tim->tm_mon, tim->tm_mday,
  200. tim->tm_wday, tim->tm_hour, tim->tm_min, tim->tm_sec);
  201. return 0;
  202. }
  203. static int mcp795_read_time(struct device *dev, struct rtc_time *tim)
  204. {
  205. int ret;
  206. u8 data[7];
  207. ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
  208. if (ret)
  209. return ret;
  210. tim->tm_sec = bcd2bin(data[0] & 0x7F);
  211. tim->tm_min = bcd2bin(data[1] & 0x7F);
  212. tim->tm_hour = bcd2bin(data[2] & 0x3F);
  213. tim->tm_wday = bcd2bin(data[3] & 0x07) - 1;
  214. tim->tm_mday = bcd2bin(data[4] & 0x3F);
  215. tim->tm_mon = bcd2bin(data[5] & 0x1F) - 1;
  216. tim->tm_year = bcd2bin(data[6]) + 100; /* Assume we are in 20xx */
  217. dev_dbg(dev, "Read from mcp795: %04d-%02d-%02d(%d) %02d:%02d:%02d\n",
  218. tim->tm_year + 1900, tim->tm_mon, tim->tm_mday,
  219. tim->tm_wday, tim->tm_hour, tim->tm_min, tim->tm_sec);
  220. return 0;
  221. }
  222. static int mcp795_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
  223. {
  224. struct rtc_time now_tm;
  225. time64_t now;
  226. time64_t later;
  227. u8 tmp[6];
  228. int ret;
  229. /* Read current time from RTC hardware */
  230. ret = mcp795_read_time(dev, &now_tm);
  231. if (ret)
  232. return ret;
  233. /* Get the number of seconds since 1970 */
  234. now = rtc_tm_to_time64(&now_tm);
  235. later = rtc_tm_to_time64(&alm->time);
  236. if (later <= now)
  237. return -EINVAL;
  238. /* make sure alarm fires within the next one year */
  239. if ((later - now) >=
  240. (SEC_PER_DAY * (365 + is_leap_year(alm->time.tm_year))))
  241. return -EDOM;
  242. /* disable alarm */
  243. ret = mcp795_update_alarm(dev, false);
  244. if (ret)
  245. return ret;
  246. /* Read registers, so we can leave configuration bits untouched */
  247. ret = mcp795_rtcc_read(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
  248. if (ret)
  249. return ret;
  250. alm->time.tm_year = -1;
  251. alm->time.tm_isdst = -1;
  252. alm->time.tm_yday = -1;
  253. tmp[0] = (tmp[0] & 0x80) | bin2bcd(alm->time.tm_sec);
  254. tmp[1] = (tmp[1] & 0x80) | bin2bcd(alm->time.tm_min);
  255. tmp[2] = (tmp[2] & 0xE0) | bin2bcd(alm->time.tm_hour);
  256. tmp[3] = (tmp[3] & 0x80) | bin2bcd(alm->time.tm_wday + 1);
  257. /* set alarm match: seconds, minutes, hour, day, date and month */
  258. tmp[3] |= (MCP795_ALM0C2_BIT | MCP795_ALM0C1_BIT | MCP795_ALM0C0_BIT);
  259. tmp[4] = (tmp[4] & 0xC0) | bin2bcd(alm->time.tm_mday);
  260. tmp[5] = (tmp[5] & 0xE0) | bin2bcd(alm->time.tm_mon + 1);
  261. ret = mcp795_rtcc_write(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
  262. if (ret)
  263. return ret;
  264. /* enable alarm if requested */
  265. if (alm->enabled) {
  266. ret = mcp795_update_alarm(dev, true);
  267. if (ret)
  268. return ret;
  269. dev_dbg(dev, "Alarm IRQ armed\n");
  270. }
  271. dev_dbg(dev, "Set alarm: %02d-%02d(%d) %02d:%02d:%02d\n",
  272. alm->time.tm_mon, alm->time.tm_mday, alm->time.tm_wday,
  273. alm->time.tm_hour, alm->time.tm_min, alm->time.tm_sec);
  274. return 0;
  275. }
  276. static int mcp795_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
  277. {
  278. u8 data[6];
  279. int ret;
  280. ret = mcp795_rtcc_read(
  281. dev, MCP795_REG_ALM0_SECONDS, data, sizeof(data));
  282. if (ret)
  283. return ret;
  284. alm->time.tm_sec = bcd2bin(data[0] & 0x7F);
  285. alm->time.tm_min = bcd2bin(data[1] & 0x7F);
  286. alm->time.tm_hour = bcd2bin(data[2] & 0x1F);
  287. alm->time.tm_wday = bcd2bin(data[3] & 0x07) - 1;
  288. alm->time.tm_mday = bcd2bin(data[4] & 0x3F);
  289. alm->time.tm_mon = bcd2bin(data[5] & 0x1F) - 1;
  290. alm->time.tm_year = -1;
  291. alm->time.tm_isdst = -1;
  292. alm->time.tm_yday = -1;
  293. dev_dbg(dev, "Read alarm: %02d-%02d(%d) %02d:%02d:%02d\n",
  294. alm->time.tm_mon, alm->time.tm_mday, alm->time.tm_wday,
  295. alm->time.tm_hour, alm->time.tm_min, alm->time.tm_sec);
  296. return 0;
  297. }
  298. static int mcp795_alarm_irq_enable(struct device *dev, unsigned int enabled)
  299. {
  300. return mcp795_update_alarm(dev, !!enabled);
  301. }
  302. static irqreturn_t mcp795_irq(int irq, void *data)
  303. {
  304. struct spi_device *spi = data;
  305. struct rtc_device *rtc = spi_get_drvdata(spi);
  306. struct mutex *lock = &rtc->ops_lock;
  307. int ret;
  308. mutex_lock(lock);
  309. /* Disable alarm.
  310. * There is no need to clear ALM0IF (Alarm 0 Interrupt Flag) bit,
  311. * because it is done every time when alarm is enabled.
  312. */
  313. ret = mcp795_update_alarm(&spi->dev, false);
  314. if (ret)
  315. dev_err(&spi->dev,
  316. "Failed to disable alarm in IRQ (ret=%d)\n", ret);
  317. rtc_update_irq(rtc, 1, RTC_AF | RTC_IRQF);
  318. mutex_unlock(lock);
  319. return IRQ_HANDLED;
  320. }
  321. static const struct rtc_class_ops mcp795_rtc_ops = {
  322. .read_time = mcp795_read_time,
  323. .set_time = mcp795_set_time,
  324. .read_alarm = mcp795_read_alarm,
  325. .set_alarm = mcp795_set_alarm,
  326. .alarm_irq_enable = mcp795_alarm_irq_enable
  327. };
  328. static int mcp795_probe(struct spi_device *spi)
  329. {
  330. struct rtc_device *rtc;
  331. int ret;
  332. spi->mode = SPI_MODE_0;
  333. spi->bits_per_word = 8;
  334. ret = spi_setup(spi);
  335. if (ret) {
  336. dev_err(&spi->dev, "Unable to setup SPI\n");
  337. return ret;
  338. }
  339. /* Start the oscillator but don't set the value of EXTOSC bit */
  340. mcp795_start_oscillator(&spi->dev, NULL);
  341. /* Clear the 12 hour mode flag*/
  342. mcp795_rtcc_set_bits(&spi->dev, 0x03, MCP795_24_BIT, 0);
  343. rtc = devm_rtc_device_register(&spi->dev, "rtc-mcp795",
  344. &mcp795_rtc_ops, THIS_MODULE);
  345. if (IS_ERR(rtc))
  346. return PTR_ERR(rtc);
  347. spi_set_drvdata(spi, rtc);
  348. if (spi->irq > 0) {
  349. dev_dbg(&spi->dev, "Alarm support enabled\n");
  350. /* Clear any pending alarm (ALM0IF bit) before requesting
  351. * the interrupt.
  352. */
  353. mcp795_rtcc_set_bits(&spi->dev, MCP795_REG_ALM0_DAY,
  354. MCP795_ALM0IF_BIT, 0);
  355. ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
  356. mcp795_irq, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  357. dev_name(&rtc->dev), spi);
  358. if (ret)
  359. dev_err(&spi->dev, "Failed to request IRQ: %d: %d\n",
  360. spi->irq, ret);
  361. else
  362. device_init_wakeup(&spi->dev, true);
  363. }
  364. return 0;
  365. }
  366. #ifdef CONFIG_OF
  367. static const struct of_device_id mcp795_of_match[] = {
  368. { .compatible = "maxim,mcp795" },
  369. { }
  370. };
  371. MODULE_DEVICE_TABLE(of, mcp795_of_match);
  372. #endif
  373. static struct spi_driver mcp795_driver = {
  374. .driver = {
  375. .name = "rtc-mcp795",
  376. .of_match_table = of_match_ptr(mcp795_of_match),
  377. },
  378. .probe = mcp795_probe,
  379. };
  380. module_spi_driver(mcp795_driver);
  381. MODULE_DESCRIPTION("MCP795 RTC SPI Driver");
  382. MODULE_AUTHOR("Josef Gajdusek <atx@atx.name>");
  383. MODULE_LICENSE("GPL");
  384. MODULE_ALIAS("spi:mcp795");