lib82596.c 38 KB

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  1. /* lasi_82596.c -- driver for the intel 82596 ethernet controller, as
  2. munged into HPPA boxen .
  3. This driver is based upon 82596.c, original credits are below...
  4. but there were too many hoops which HP wants jumped through to
  5. keep this code in there in a sane manner.
  6. 3 primary sources of the mess --
  7. 1) hppa needs *lots* of cacheline flushing to keep this kind of
  8. MMIO running.
  9. 2) The 82596 needs to see all of its pointers as their physical
  10. address. Thus virt_to_bus/bus_to_virt are *everywhere*.
  11. 3) The implementation HP is using seems to be significantly pickier
  12. about when and how the command and RX units are started. some
  13. command ordering was changed.
  14. Examination of the mach driver leads one to believe that there
  15. might be a saner way to pull this off... anyone who feels like a
  16. full rewrite can be my guest.
  17. Split 02/13/2000 Sam Creasey (sammy@oh.verio.com)
  18. 02/01/2000 Initial modifications for parisc by Helge Deller (deller@gmx.de)
  19. 03/02/2000 changes for better/correct(?) cache-flushing (deller)
  20. */
  21. /* 82596.c: A generic 82596 ethernet driver for linux. */
  22. /*
  23. Based on Apricot.c
  24. Written 1994 by Mark Evans.
  25. This driver is for the Apricot 82596 bus-master interface
  26. Modularised 12/94 Mark Evans
  27. Modified to support the 82596 ethernet chips on 680x0 VME boards.
  28. by Richard Hirst <richard@sleepie.demon.co.uk>
  29. Renamed to be 82596.c
  30. 980825: Changed to receive directly in to sk_buffs which are
  31. allocated at open() time. Eliminates copy on incoming frames
  32. (small ones are still copied). Shared data now held in a
  33. non-cached page, so we can run on 68060 in copyback mode.
  34. TBD:
  35. * look at deferring rx frames rather than discarding (as per tulip)
  36. * handle tx ring full as per tulip
  37. * performance test to tune rx_copybreak
  38. Most of my modifications relate to the braindead big-endian
  39. implementation by Intel. When the i596 is operating in
  40. 'big-endian' mode, it thinks a 32 bit value of 0x12345678
  41. should be stored as 0x56781234. This is a real pain, when
  42. you have linked lists which are shared by the 680x0 and the
  43. i596.
  44. Driver skeleton
  45. Written 1993 by Donald Becker.
  46. Copyright 1993 United States Government as represented by the Director,
  47. National Security Agency. This software may only be used and distributed
  48. according to the terms of the GNU General Public License as modified by SRC,
  49. incorporated herein by reference.
  50. The author may be reached as becker@scyld.com, or C/O
  51. Scyld Computing Corporation, 410 Severn Ave., Suite 210, Annapolis MD 21403
  52. */
  53. #include <linux/module.h>
  54. #include <linux/kernel.h>
  55. #include <linux/string.h>
  56. #include <linux/errno.h>
  57. #include <linux/ioport.h>
  58. #include <linux/interrupt.h>
  59. #include <linux/delay.h>
  60. #include <linux/netdevice.h>
  61. #include <linux/etherdevice.h>
  62. #include <linux/skbuff.h>
  63. #include <linux/types.h>
  64. #include <linux/bitops.h>
  65. #include <linux/dma-mapping.h>
  66. #include <linux/io.h>
  67. #include <linux/irq.h>
  68. #include <linux/gfp.h>
  69. /* DEBUG flags
  70. */
  71. #define DEB_INIT 0x0001
  72. #define DEB_PROBE 0x0002
  73. #define DEB_SERIOUS 0x0004
  74. #define DEB_ERRORS 0x0008
  75. #define DEB_MULTI 0x0010
  76. #define DEB_TDR 0x0020
  77. #define DEB_OPEN 0x0040
  78. #define DEB_RESET 0x0080
  79. #define DEB_ADDCMD 0x0100
  80. #define DEB_STATUS 0x0200
  81. #define DEB_STARTTX 0x0400
  82. #define DEB_RXADDR 0x0800
  83. #define DEB_TXADDR 0x1000
  84. #define DEB_RXFRAME 0x2000
  85. #define DEB_INTS 0x4000
  86. #define DEB_STRUCT 0x8000
  87. #define DEB_ANY 0xffff
  88. #define DEB(x, y) if (i596_debug & (x)) { y; }
  89. /*
  90. * The MPU_PORT command allows direct access to the 82596. With PORT access
  91. * the following commands are available (p5-18). The 32-bit port command
  92. * must be word-swapped with the most significant word written first.
  93. * This only applies to VME boards.
  94. */
  95. #define PORT_RESET 0x00 /* reset 82596 */
  96. #define PORT_SELFTEST 0x01 /* selftest */
  97. #define PORT_ALTSCP 0x02 /* alternate SCB address */
  98. #define PORT_ALTDUMP 0x03 /* Alternate DUMP address */
  99. static int i596_debug = (DEB_SERIOUS|DEB_PROBE);
  100. /* Copy frames shorter than rx_copybreak, otherwise pass on up in
  101. * a full sized sk_buff. Value of 100 stolen from tulip.c (!alpha).
  102. */
  103. static int rx_copybreak = 100;
  104. #define PKT_BUF_SZ 1536
  105. #define MAX_MC_CNT 64
  106. #define ISCP_BUSY 0x0001
  107. #define I596_NULL ((u32)0xffffffff)
  108. #define CMD_EOL 0x8000 /* The last command of the list, stop. */
  109. #define CMD_SUSP 0x4000 /* Suspend after doing cmd. */
  110. #define CMD_INTR 0x2000 /* Interrupt after doing cmd. */
  111. #define CMD_FLEX 0x0008 /* Enable flexible memory model */
  112. enum commands {
  113. CmdNOp = 0, CmdSASetup = 1, CmdConfigure = 2, CmdMulticastList = 3,
  114. CmdTx = 4, CmdTDR = 5, CmdDump = 6, CmdDiagnose = 7
  115. };
  116. #define STAT_C 0x8000 /* Set to 0 after execution */
  117. #define STAT_B 0x4000 /* Command being executed */
  118. #define STAT_OK 0x2000 /* Command executed ok */
  119. #define STAT_A 0x1000 /* Command aborted */
  120. #define CUC_START 0x0100
  121. #define CUC_RESUME 0x0200
  122. #define CUC_SUSPEND 0x0300
  123. #define CUC_ABORT 0x0400
  124. #define RX_START 0x0010
  125. #define RX_RESUME 0x0020
  126. #define RX_SUSPEND 0x0030
  127. #define RX_ABORT 0x0040
  128. #define TX_TIMEOUT (HZ/20)
  129. struct i596_reg {
  130. unsigned short porthi;
  131. unsigned short portlo;
  132. u32 ca;
  133. };
  134. #define EOF 0x8000
  135. #define SIZE_MASK 0x3fff
  136. struct i596_tbd {
  137. unsigned short size;
  138. unsigned short pad;
  139. u32 next;
  140. u32 data;
  141. u32 cache_pad[5]; /* Total 32 bytes... */
  142. };
  143. /* The command structure has two 'next' pointers; v_next is the address of
  144. * the next command as seen by the CPU, b_next is the address of the next
  145. * command as seen by the 82596. The b_next pointer, as used by the 82596
  146. * always references the status field of the next command, rather than the
  147. * v_next field, because the 82596 is unaware of v_next. It may seem more
  148. * logical to put v_next at the end of the structure, but we cannot do that
  149. * because the 82596 expects other fields to be there, depending on command
  150. * type.
  151. */
  152. struct i596_cmd {
  153. struct i596_cmd *v_next; /* Address from CPUs viewpoint */
  154. unsigned short status;
  155. unsigned short command;
  156. u32 b_next; /* Address from i596 viewpoint */
  157. };
  158. struct tx_cmd {
  159. struct i596_cmd cmd;
  160. u32 tbd;
  161. unsigned short size;
  162. unsigned short pad;
  163. struct sk_buff *skb; /* So we can free it after tx */
  164. dma_addr_t dma_addr;
  165. #ifdef __LP64__
  166. u32 cache_pad[6]; /* Total 64 bytes... */
  167. #else
  168. u32 cache_pad[1]; /* Total 32 bytes... */
  169. #endif
  170. };
  171. struct tdr_cmd {
  172. struct i596_cmd cmd;
  173. unsigned short status;
  174. unsigned short pad;
  175. };
  176. struct mc_cmd {
  177. struct i596_cmd cmd;
  178. short mc_cnt;
  179. char mc_addrs[MAX_MC_CNT*6];
  180. };
  181. struct sa_cmd {
  182. struct i596_cmd cmd;
  183. char eth_addr[8];
  184. };
  185. struct cf_cmd {
  186. struct i596_cmd cmd;
  187. char i596_config[16];
  188. };
  189. struct i596_rfd {
  190. unsigned short stat;
  191. unsigned short cmd;
  192. u32 b_next; /* Address from i596 viewpoint */
  193. u32 rbd;
  194. unsigned short count;
  195. unsigned short size;
  196. struct i596_rfd *v_next; /* Address from CPUs viewpoint */
  197. struct i596_rfd *v_prev;
  198. #ifndef __LP64__
  199. u32 cache_pad[2]; /* Total 32 bytes... */
  200. #endif
  201. };
  202. struct i596_rbd {
  203. /* hardware data */
  204. unsigned short count;
  205. unsigned short zero1;
  206. u32 b_next;
  207. u32 b_data; /* Address from i596 viewpoint */
  208. unsigned short size;
  209. unsigned short zero2;
  210. /* driver data */
  211. struct sk_buff *skb;
  212. struct i596_rbd *v_next;
  213. u32 b_addr; /* This rbd addr from i596 view */
  214. unsigned char *v_data; /* Address from CPUs viewpoint */
  215. /* Total 32 bytes... */
  216. #ifdef __LP64__
  217. u32 cache_pad[4];
  218. #endif
  219. };
  220. /* These values as chosen so struct i596_dma fits in one page... */
  221. #define TX_RING_SIZE 32
  222. #define RX_RING_SIZE 16
  223. struct i596_scb {
  224. unsigned short status;
  225. unsigned short command;
  226. u32 cmd;
  227. u32 rfd;
  228. u32 crc_err;
  229. u32 align_err;
  230. u32 resource_err;
  231. u32 over_err;
  232. u32 rcvdt_err;
  233. u32 short_err;
  234. unsigned short t_on;
  235. unsigned short t_off;
  236. };
  237. struct i596_iscp {
  238. u32 stat;
  239. u32 scb;
  240. };
  241. struct i596_scp {
  242. u32 sysbus;
  243. u32 pad;
  244. u32 iscp;
  245. };
  246. struct i596_dma {
  247. struct i596_scp scp __attribute__((aligned(32)));
  248. volatile struct i596_iscp iscp __attribute__((aligned(32)));
  249. volatile struct i596_scb scb __attribute__((aligned(32)));
  250. struct sa_cmd sa_cmd __attribute__((aligned(32)));
  251. struct cf_cmd cf_cmd __attribute__((aligned(32)));
  252. struct tdr_cmd tdr_cmd __attribute__((aligned(32)));
  253. struct mc_cmd mc_cmd __attribute__((aligned(32)));
  254. struct i596_rfd rfds[RX_RING_SIZE] __attribute__((aligned(32)));
  255. struct i596_rbd rbds[RX_RING_SIZE] __attribute__((aligned(32)));
  256. struct tx_cmd tx_cmds[TX_RING_SIZE] __attribute__((aligned(32)));
  257. struct i596_tbd tbds[TX_RING_SIZE] __attribute__((aligned(32)));
  258. };
  259. struct i596_private {
  260. struct i596_dma *dma;
  261. u32 stat;
  262. int last_restart;
  263. struct i596_rfd *rfd_head;
  264. struct i596_rbd *rbd_head;
  265. struct i596_cmd *cmd_tail;
  266. struct i596_cmd *cmd_head;
  267. int cmd_backlog;
  268. u32 last_cmd;
  269. int next_tx_cmd;
  270. int options;
  271. spinlock_t lock; /* serialize access to chip */
  272. dma_addr_t dma_addr;
  273. void __iomem *mpu_port;
  274. void __iomem *ca;
  275. };
  276. static const char init_setup[] =
  277. {
  278. 0x8E, /* length, prefetch on */
  279. 0xC8, /* fifo to 8, monitor off */
  280. 0x80, /* don't save bad frames */
  281. 0x2E, /* No source address insertion, 8 byte preamble */
  282. 0x00, /* priority and backoff defaults */
  283. 0x60, /* interframe spacing */
  284. 0x00, /* slot time LSB */
  285. 0xf2, /* slot time and retries */
  286. 0x00, /* promiscuous mode */
  287. 0x00, /* collision detect */
  288. 0x40, /* minimum frame length */
  289. 0xff,
  290. 0x00,
  291. 0x7f /* *multi IA */ };
  292. static int i596_open(struct net_device *dev);
  293. static netdev_tx_t i596_start_xmit(struct sk_buff *skb, struct net_device *dev);
  294. static irqreturn_t i596_interrupt(int irq, void *dev_id);
  295. static int i596_close(struct net_device *dev);
  296. static void i596_add_cmd(struct net_device *dev, struct i596_cmd *cmd);
  297. static void i596_tx_timeout (struct net_device *dev);
  298. static void print_eth(unsigned char *buf, char *str);
  299. static void set_multicast_list(struct net_device *dev);
  300. static inline void ca(struct net_device *dev);
  301. static void mpu_port(struct net_device *dev, int c, dma_addr_t x);
  302. static int rx_ring_size = RX_RING_SIZE;
  303. static int ticks_limit = 100;
  304. static int max_cmd_backlog = TX_RING_SIZE-1;
  305. #ifdef CONFIG_NET_POLL_CONTROLLER
  306. static void i596_poll_controller(struct net_device *dev);
  307. #endif
  308. static inline int wait_istat(struct net_device *dev, struct i596_dma *dma, int delcnt, char *str)
  309. {
  310. DMA_INV(dev, &(dma->iscp), sizeof(struct i596_iscp));
  311. while (--delcnt && dma->iscp.stat) {
  312. udelay(10);
  313. DMA_INV(dev, &(dma->iscp), sizeof(struct i596_iscp));
  314. }
  315. if (!delcnt) {
  316. printk(KERN_ERR "%s: %s, iscp.stat %04x, didn't clear\n",
  317. dev->name, str, SWAP16(dma->iscp.stat));
  318. return -1;
  319. } else
  320. return 0;
  321. }
  322. static inline int wait_cmd(struct net_device *dev, struct i596_dma *dma, int delcnt, char *str)
  323. {
  324. DMA_INV(dev, &(dma->scb), sizeof(struct i596_scb));
  325. while (--delcnt && dma->scb.command) {
  326. udelay(10);
  327. DMA_INV(dev, &(dma->scb), sizeof(struct i596_scb));
  328. }
  329. if (!delcnt) {
  330. printk(KERN_ERR "%s: %s, status %4.4x, cmd %4.4x.\n",
  331. dev->name, str,
  332. SWAP16(dma->scb.status),
  333. SWAP16(dma->scb.command));
  334. return -1;
  335. } else
  336. return 0;
  337. }
  338. static void i596_display_data(struct net_device *dev)
  339. {
  340. struct i596_private *lp = netdev_priv(dev);
  341. struct i596_dma *dma = lp->dma;
  342. struct i596_cmd *cmd;
  343. struct i596_rfd *rfd;
  344. struct i596_rbd *rbd;
  345. printk(KERN_DEBUG "lp and scp at %p, .sysbus = %08x, .iscp = %08x\n",
  346. &dma->scp, dma->scp.sysbus, SWAP32(dma->scp.iscp));
  347. printk(KERN_DEBUG "iscp at %p, iscp.stat = %08x, .scb = %08x\n",
  348. &dma->iscp, SWAP32(dma->iscp.stat), SWAP32(dma->iscp.scb));
  349. printk(KERN_DEBUG "scb at %p, scb.status = %04x, .command = %04x,"
  350. " .cmd = %08x, .rfd = %08x\n",
  351. &dma->scb, SWAP16(dma->scb.status), SWAP16(dma->scb.command),
  352. SWAP16(dma->scb.cmd), SWAP32(dma->scb.rfd));
  353. printk(KERN_DEBUG " errors: crc %x, align %x, resource %x,"
  354. " over %x, rcvdt %x, short %x\n",
  355. SWAP32(dma->scb.crc_err), SWAP32(dma->scb.align_err),
  356. SWAP32(dma->scb.resource_err), SWAP32(dma->scb.over_err),
  357. SWAP32(dma->scb.rcvdt_err), SWAP32(dma->scb.short_err));
  358. cmd = lp->cmd_head;
  359. while (cmd != NULL) {
  360. printk(KERN_DEBUG
  361. "cmd at %p, .status = %04x, .command = %04x,"
  362. " .b_next = %08x\n",
  363. cmd, SWAP16(cmd->status), SWAP16(cmd->command),
  364. SWAP32(cmd->b_next));
  365. cmd = cmd->v_next;
  366. }
  367. rfd = lp->rfd_head;
  368. printk(KERN_DEBUG "rfd_head = %p\n", rfd);
  369. do {
  370. printk(KERN_DEBUG
  371. " %p .stat %04x, .cmd %04x, b_next %08x, rbd %08x,"
  372. " count %04x\n",
  373. rfd, SWAP16(rfd->stat), SWAP16(rfd->cmd),
  374. SWAP32(rfd->b_next), SWAP32(rfd->rbd),
  375. SWAP16(rfd->count));
  376. rfd = rfd->v_next;
  377. } while (rfd != lp->rfd_head);
  378. rbd = lp->rbd_head;
  379. printk(KERN_DEBUG "rbd_head = %p\n", rbd);
  380. do {
  381. printk(KERN_DEBUG
  382. " %p .count %04x, b_next %08x, b_data %08x,"
  383. " size %04x\n",
  384. rbd, SWAP16(rbd->count), SWAP32(rbd->b_next),
  385. SWAP32(rbd->b_data), SWAP16(rbd->size));
  386. rbd = rbd->v_next;
  387. } while (rbd != lp->rbd_head);
  388. DMA_INV(dev, dma, sizeof(struct i596_dma));
  389. }
  390. #define virt_to_dma(lp, v) ((lp)->dma_addr + (dma_addr_t)((unsigned long)(v)-(unsigned long)((lp)->dma)))
  391. static inline int init_rx_bufs(struct net_device *dev)
  392. {
  393. struct i596_private *lp = netdev_priv(dev);
  394. struct i596_dma *dma = lp->dma;
  395. int i;
  396. struct i596_rfd *rfd;
  397. struct i596_rbd *rbd;
  398. /* First build the Receive Buffer Descriptor List */
  399. for (i = 0, rbd = dma->rbds; i < rx_ring_size; i++, rbd++) {
  400. dma_addr_t dma_addr;
  401. struct sk_buff *skb;
  402. skb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ);
  403. if (skb == NULL)
  404. return -1;
  405. dma_addr = dma_map_single(dev->dev.parent, skb->data,
  406. PKT_BUF_SZ, DMA_FROM_DEVICE);
  407. rbd->v_next = rbd+1;
  408. rbd->b_next = SWAP32(virt_to_dma(lp, rbd+1));
  409. rbd->b_addr = SWAP32(virt_to_dma(lp, rbd));
  410. rbd->skb = skb;
  411. rbd->v_data = skb->data;
  412. rbd->b_data = SWAP32(dma_addr);
  413. rbd->size = SWAP16(PKT_BUF_SZ);
  414. }
  415. lp->rbd_head = dma->rbds;
  416. rbd = dma->rbds + rx_ring_size - 1;
  417. rbd->v_next = dma->rbds;
  418. rbd->b_next = SWAP32(virt_to_dma(lp, dma->rbds));
  419. /* Now build the Receive Frame Descriptor List */
  420. for (i = 0, rfd = dma->rfds; i < rx_ring_size; i++, rfd++) {
  421. rfd->rbd = I596_NULL;
  422. rfd->v_next = rfd+1;
  423. rfd->v_prev = rfd-1;
  424. rfd->b_next = SWAP32(virt_to_dma(lp, rfd+1));
  425. rfd->cmd = SWAP16(CMD_FLEX);
  426. }
  427. lp->rfd_head = dma->rfds;
  428. dma->scb.rfd = SWAP32(virt_to_dma(lp, dma->rfds));
  429. rfd = dma->rfds;
  430. rfd->rbd = SWAP32(virt_to_dma(lp, lp->rbd_head));
  431. rfd->v_prev = dma->rfds + rx_ring_size - 1;
  432. rfd = dma->rfds + rx_ring_size - 1;
  433. rfd->v_next = dma->rfds;
  434. rfd->b_next = SWAP32(virt_to_dma(lp, dma->rfds));
  435. rfd->cmd = SWAP16(CMD_EOL|CMD_FLEX);
  436. DMA_WBACK_INV(dev, dma, sizeof(struct i596_dma));
  437. return 0;
  438. }
  439. static inline void remove_rx_bufs(struct net_device *dev)
  440. {
  441. struct i596_private *lp = netdev_priv(dev);
  442. struct i596_rbd *rbd;
  443. int i;
  444. for (i = 0, rbd = lp->dma->rbds; i < rx_ring_size; i++, rbd++) {
  445. if (rbd->skb == NULL)
  446. break;
  447. dma_unmap_single(dev->dev.parent,
  448. (dma_addr_t)SWAP32(rbd->b_data),
  449. PKT_BUF_SZ, DMA_FROM_DEVICE);
  450. dev_kfree_skb(rbd->skb);
  451. }
  452. }
  453. static void rebuild_rx_bufs(struct net_device *dev)
  454. {
  455. struct i596_private *lp = netdev_priv(dev);
  456. struct i596_dma *dma = lp->dma;
  457. int i;
  458. /* Ensure rx frame/buffer descriptors are tidy */
  459. for (i = 0; i < rx_ring_size; i++) {
  460. dma->rfds[i].rbd = I596_NULL;
  461. dma->rfds[i].cmd = SWAP16(CMD_FLEX);
  462. }
  463. dma->rfds[rx_ring_size-1].cmd = SWAP16(CMD_EOL|CMD_FLEX);
  464. lp->rfd_head = dma->rfds;
  465. dma->scb.rfd = SWAP32(virt_to_dma(lp, dma->rfds));
  466. lp->rbd_head = dma->rbds;
  467. dma->rfds[0].rbd = SWAP32(virt_to_dma(lp, dma->rbds));
  468. DMA_WBACK_INV(dev, dma, sizeof(struct i596_dma));
  469. }
  470. static int init_i596_mem(struct net_device *dev)
  471. {
  472. struct i596_private *lp = netdev_priv(dev);
  473. struct i596_dma *dma = lp->dma;
  474. unsigned long flags;
  475. mpu_port(dev, PORT_RESET, 0);
  476. udelay(100); /* Wait 100us - seems to help */
  477. /* change the scp address */
  478. lp->last_cmd = jiffies;
  479. dma->scp.sysbus = SYSBUS;
  480. dma->scp.iscp = SWAP32(virt_to_dma(lp, &(dma->iscp)));
  481. dma->iscp.scb = SWAP32(virt_to_dma(lp, &(dma->scb)));
  482. dma->iscp.stat = SWAP32(ISCP_BUSY);
  483. lp->cmd_backlog = 0;
  484. lp->cmd_head = NULL;
  485. dma->scb.cmd = I596_NULL;
  486. DEB(DEB_INIT, printk(KERN_DEBUG "%s: starting i82596.\n", dev->name));
  487. DMA_WBACK(dev, &(dma->scp), sizeof(struct i596_scp));
  488. DMA_WBACK(dev, &(dma->iscp), sizeof(struct i596_iscp));
  489. DMA_WBACK(dev, &(dma->scb), sizeof(struct i596_scb));
  490. mpu_port(dev, PORT_ALTSCP, virt_to_dma(lp, &dma->scp));
  491. ca(dev);
  492. if (wait_istat(dev, dma, 1000, "initialization timed out"))
  493. goto failed;
  494. DEB(DEB_INIT, printk(KERN_DEBUG
  495. "%s: i82596 initialization successful\n",
  496. dev->name));
  497. if (request_irq(dev->irq, i596_interrupt, 0, "i82596", dev)) {
  498. printk(KERN_ERR "%s: IRQ %d not free\n", dev->name, dev->irq);
  499. goto failed;
  500. }
  501. /* Ensure rx frame/buffer descriptors are tidy */
  502. rebuild_rx_bufs(dev);
  503. dma->scb.command = 0;
  504. DMA_WBACK(dev, &(dma->scb), sizeof(struct i596_scb));
  505. DEB(DEB_INIT, printk(KERN_DEBUG
  506. "%s: queuing CmdConfigure\n", dev->name));
  507. memcpy(dma->cf_cmd.i596_config, init_setup, 14);
  508. dma->cf_cmd.cmd.command = SWAP16(CmdConfigure);
  509. DMA_WBACK(dev, &(dma->cf_cmd), sizeof(struct cf_cmd));
  510. i596_add_cmd(dev, &dma->cf_cmd.cmd);
  511. DEB(DEB_INIT, printk(KERN_DEBUG "%s: queuing CmdSASetup\n", dev->name));
  512. memcpy(dma->sa_cmd.eth_addr, dev->dev_addr, ETH_ALEN);
  513. dma->sa_cmd.cmd.command = SWAP16(CmdSASetup);
  514. DMA_WBACK(dev, &(dma->sa_cmd), sizeof(struct sa_cmd));
  515. i596_add_cmd(dev, &dma->sa_cmd.cmd);
  516. DEB(DEB_INIT, printk(KERN_DEBUG "%s: queuing CmdTDR\n", dev->name));
  517. dma->tdr_cmd.cmd.command = SWAP16(CmdTDR);
  518. DMA_WBACK(dev, &(dma->tdr_cmd), sizeof(struct tdr_cmd));
  519. i596_add_cmd(dev, &dma->tdr_cmd.cmd);
  520. spin_lock_irqsave (&lp->lock, flags);
  521. if (wait_cmd(dev, dma, 1000, "timed out waiting to issue RX_START")) {
  522. spin_unlock_irqrestore (&lp->lock, flags);
  523. goto failed_free_irq;
  524. }
  525. DEB(DEB_INIT, printk(KERN_DEBUG "%s: Issuing RX_START\n", dev->name));
  526. dma->scb.command = SWAP16(RX_START);
  527. dma->scb.rfd = SWAP32(virt_to_dma(lp, dma->rfds));
  528. DMA_WBACK(dev, &(dma->scb), sizeof(struct i596_scb));
  529. ca(dev);
  530. spin_unlock_irqrestore (&lp->lock, flags);
  531. if (wait_cmd(dev, dma, 1000, "RX_START not processed"))
  532. goto failed_free_irq;
  533. DEB(DEB_INIT, printk(KERN_DEBUG
  534. "%s: Receive unit started OK\n", dev->name));
  535. return 0;
  536. failed_free_irq:
  537. free_irq(dev->irq, dev);
  538. failed:
  539. printk(KERN_ERR "%s: Failed to initialise 82596\n", dev->name);
  540. mpu_port(dev, PORT_RESET, 0);
  541. return -1;
  542. }
  543. static inline int i596_rx(struct net_device *dev)
  544. {
  545. struct i596_private *lp = netdev_priv(dev);
  546. struct i596_rfd *rfd;
  547. struct i596_rbd *rbd;
  548. int frames = 0;
  549. DEB(DEB_RXFRAME, printk(KERN_DEBUG
  550. "i596_rx(), rfd_head %p, rbd_head %p\n",
  551. lp->rfd_head, lp->rbd_head));
  552. rfd = lp->rfd_head; /* Ref next frame to check */
  553. DMA_INV(dev, rfd, sizeof(struct i596_rfd));
  554. while (rfd->stat & SWAP16(STAT_C)) { /* Loop while complete frames */
  555. if (rfd->rbd == I596_NULL)
  556. rbd = NULL;
  557. else if (rfd->rbd == lp->rbd_head->b_addr) {
  558. rbd = lp->rbd_head;
  559. DMA_INV(dev, rbd, sizeof(struct i596_rbd));
  560. } else {
  561. printk(KERN_ERR "%s: rbd chain broken!\n", dev->name);
  562. /* XXX Now what? */
  563. rbd = NULL;
  564. }
  565. DEB(DEB_RXFRAME, printk(KERN_DEBUG
  566. " rfd %p, rfd.rbd %08x, rfd.stat %04x\n",
  567. rfd, rfd->rbd, rfd->stat));
  568. if (rbd != NULL && (rfd->stat & SWAP16(STAT_OK))) {
  569. /* a good frame */
  570. int pkt_len = SWAP16(rbd->count) & 0x3fff;
  571. struct sk_buff *skb = rbd->skb;
  572. int rx_in_place = 0;
  573. DEB(DEB_RXADDR, print_eth(rbd->v_data, "received"));
  574. frames++;
  575. /* Check if the packet is long enough to just accept
  576. * without copying to a properly sized skbuff.
  577. */
  578. if (pkt_len > rx_copybreak) {
  579. struct sk_buff *newskb;
  580. dma_addr_t dma_addr;
  581. dma_unmap_single(dev->dev.parent,
  582. (dma_addr_t)SWAP32(rbd->b_data),
  583. PKT_BUF_SZ, DMA_FROM_DEVICE);
  584. /* Get fresh skbuff to replace filled one. */
  585. newskb = netdev_alloc_skb_ip_align(dev,
  586. PKT_BUF_SZ);
  587. if (newskb == NULL) {
  588. skb = NULL; /* drop pkt */
  589. goto memory_squeeze;
  590. }
  591. /* Pass up the skb already on the Rx ring. */
  592. skb_put(skb, pkt_len);
  593. rx_in_place = 1;
  594. rbd->skb = newskb;
  595. dma_addr = dma_map_single(dev->dev.parent,
  596. newskb->data,
  597. PKT_BUF_SZ,
  598. DMA_FROM_DEVICE);
  599. rbd->v_data = newskb->data;
  600. rbd->b_data = SWAP32(dma_addr);
  601. DMA_WBACK_INV(dev, rbd, sizeof(struct i596_rbd));
  602. } else {
  603. skb = netdev_alloc_skb_ip_align(dev, pkt_len);
  604. }
  605. memory_squeeze:
  606. if (skb == NULL) {
  607. /* XXX tulip.c can defer packets here!! */
  608. dev->stats.rx_dropped++;
  609. } else {
  610. if (!rx_in_place) {
  611. /* 16 byte align the data fields */
  612. dma_sync_single_for_cpu(dev->dev.parent,
  613. (dma_addr_t)SWAP32(rbd->b_data),
  614. PKT_BUF_SZ, DMA_FROM_DEVICE);
  615. skb_put_data(skb, rbd->v_data,
  616. pkt_len);
  617. dma_sync_single_for_device(dev->dev.parent,
  618. (dma_addr_t)SWAP32(rbd->b_data),
  619. PKT_BUF_SZ, DMA_FROM_DEVICE);
  620. }
  621. skb->len = pkt_len;
  622. skb->protocol = eth_type_trans(skb, dev);
  623. netif_rx(skb);
  624. dev->stats.rx_packets++;
  625. dev->stats.rx_bytes += pkt_len;
  626. }
  627. } else {
  628. DEB(DEB_ERRORS, printk(KERN_DEBUG
  629. "%s: Error, rfd.stat = 0x%04x\n",
  630. dev->name, rfd->stat));
  631. dev->stats.rx_errors++;
  632. if (rfd->stat & SWAP16(0x0100))
  633. dev->stats.collisions++;
  634. if (rfd->stat & SWAP16(0x8000))
  635. dev->stats.rx_length_errors++;
  636. if (rfd->stat & SWAP16(0x0001))
  637. dev->stats.rx_over_errors++;
  638. if (rfd->stat & SWAP16(0x0002))
  639. dev->stats.rx_fifo_errors++;
  640. if (rfd->stat & SWAP16(0x0004))
  641. dev->stats.rx_frame_errors++;
  642. if (rfd->stat & SWAP16(0x0008))
  643. dev->stats.rx_crc_errors++;
  644. if (rfd->stat & SWAP16(0x0010))
  645. dev->stats.rx_length_errors++;
  646. }
  647. /* Clear the buffer descriptor count and EOF + F flags */
  648. if (rbd != NULL && (rbd->count & SWAP16(0x4000))) {
  649. rbd->count = 0;
  650. lp->rbd_head = rbd->v_next;
  651. DMA_WBACK_INV(dev, rbd, sizeof(struct i596_rbd));
  652. }
  653. /* Tidy the frame descriptor, marking it as end of list */
  654. rfd->rbd = I596_NULL;
  655. rfd->stat = 0;
  656. rfd->cmd = SWAP16(CMD_EOL|CMD_FLEX);
  657. rfd->count = 0;
  658. /* Update record of next frame descriptor to process */
  659. lp->dma->scb.rfd = rfd->b_next;
  660. lp->rfd_head = rfd->v_next;
  661. DMA_WBACK_INV(dev, rfd, sizeof(struct i596_rfd));
  662. /* Remove end-of-list from old end descriptor */
  663. rfd->v_prev->cmd = SWAP16(CMD_FLEX);
  664. DMA_WBACK_INV(dev, rfd->v_prev, sizeof(struct i596_rfd));
  665. rfd = lp->rfd_head;
  666. DMA_INV(dev, rfd, sizeof(struct i596_rfd));
  667. }
  668. DEB(DEB_RXFRAME, printk(KERN_DEBUG "frames %d\n", frames));
  669. return 0;
  670. }
  671. static inline void i596_cleanup_cmd(struct net_device *dev, struct i596_private *lp)
  672. {
  673. struct i596_cmd *ptr;
  674. while (lp->cmd_head != NULL) {
  675. ptr = lp->cmd_head;
  676. lp->cmd_head = ptr->v_next;
  677. lp->cmd_backlog--;
  678. switch (SWAP16(ptr->command) & 0x7) {
  679. case CmdTx:
  680. {
  681. struct tx_cmd *tx_cmd = (struct tx_cmd *) ptr;
  682. struct sk_buff *skb = tx_cmd->skb;
  683. dma_unmap_single(dev->dev.parent,
  684. tx_cmd->dma_addr,
  685. skb->len, DMA_TO_DEVICE);
  686. dev_kfree_skb(skb);
  687. dev->stats.tx_errors++;
  688. dev->stats.tx_aborted_errors++;
  689. ptr->v_next = NULL;
  690. ptr->b_next = I596_NULL;
  691. tx_cmd->cmd.command = 0; /* Mark as free */
  692. break;
  693. }
  694. default:
  695. ptr->v_next = NULL;
  696. ptr->b_next = I596_NULL;
  697. }
  698. DMA_WBACK_INV(dev, ptr, sizeof(struct i596_cmd));
  699. }
  700. wait_cmd(dev, lp->dma, 100, "i596_cleanup_cmd timed out");
  701. lp->dma->scb.cmd = I596_NULL;
  702. DMA_WBACK(dev, &(lp->dma->scb), sizeof(struct i596_scb));
  703. }
  704. static inline void i596_reset(struct net_device *dev, struct i596_private *lp)
  705. {
  706. unsigned long flags;
  707. DEB(DEB_RESET, printk(KERN_DEBUG "i596_reset\n"));
  708. spin_lock_irqsave (&lp->lock, flags);
  709. wait_cmd(dev, lp->dma, 100, "i596_reset timed out");
  710. netif_stop_queue(dev);
  711. /* FIXME: this command might cause an lpmc */
  712. lp->dma->scb.command = SWAP16(CUC_ABORT | RX_ABORT);
  713. DMA_WBACK(dev, &(lp->dma->scb), sizeof(struct i596_scb));
  714. ca(dev);
  715. /* wait for shutdown */
  716. wait_cmd(dev, lp->dma, 1000, "i596_reset 2 timed out");
  717. spin_unlock_irqrestore (&lp->lock, flags);
  718. i596_cleanup_cmd(dev, lp);
  719. i596_rx(dev);
  720. netif_start_queue(dev);
  721. init_i596_mem(dev);
  722. }
  723. static void i596_add_cmd(struct net_device *dev, struct i596_cmd *cmd)
  724. {
  725. struct i596_private *lp = netdev_priv(dev);
  726. struct i596_dma *dma = lp->dma;
  727. unsigned long flags;
  728. DEB(DEB_ADDCMD, printk(KERN_DEBUG "i596_add_cmd cmd_head %p\n",
  729. lp->cmd_head));
  730. cmd->status = 0;
  731. cmd->command |= SWAP16(CMD_EOL | CMD_INTR);
  732. cmd->v_next = NULL;
  733. cmd->b_next = I596_NULL;
  734. DMA_WBACK(dev, cmd, sizeof(struct i596_cmd));
  735. spin_lock_irqsave (&lp->lock, flags);
  736. if (lp->cmd_head != NULL) {
  737. lp->cmd_tail->v_next = cmd;
  738. lp->cmd_tail->b_next = SWAP32(virt_to_dma(lp, &cmd->status));
  739. DMA_WBACK(dev, lp->cmd_tail, sizeof(struct i596_cmd));
  740. } else {
  741. lp->cmd_head = cmd;
  742. wait_cmd(dev, dma, 100, "i596_add_cmd timed out");
  743. dma->scb.cmd = SWAP32(virt_to_dma(lp, &cmd->status));
  744. dma->scb.command = SWAP16(CUC_START);
  745. DMA_WBACK(dev, &(dma->scb), sizeof(struct i596_scb));
  746. ca(dev);
  747. }
  748. lp->cmd_tail = cmd;
  749. lp->cmd_backlog++;
  750. spin_unlock_irqrestore (&lp->lock, flags);
  751. if (lp->cmd_backlog > max_cmd_backlog) {
  752. unsigned long tickssofar = jiffies - lp->last_cmd;
  753. if (tickssofar < ticks_limit)
  754. return;
  755. printk(KERN_ERR
  756. "%s: command unit timed out, status resetting.\n",
  757. dev->name);
  758. #if 1
  759. i596_reset(dev, lp);
  760. #endif
  761. }
  762. }
  763. static int i596_open(struct net_device *dev)
  764. {
  765. DEB(DEB_OPEN, printk(KERN_DEBUG
  766. "%s: i596_open() irq %d.\n", dev->name, dev->irq));
  767. if (init_rx_bufs(dev)) {
  768. printk(KERN_ERR "%s: Failed to init rx bufs\n", dev->name);
  769. return -EAGAIN;
  770. }
  771. if (init_i596_mem(dev)) {
  772. printk(KERN_ERR "%s: Failed to init memory\n", dev->name);
  773. goto out_remove_rx_bufs;
  774. }
  775. netif_start_queue(dev);
  776. return 0;
  777. out_remove_rx_bufs:
  778. remove_rx_bufs(dev);
  779. return -EAGAIN;
  780. }
  781. static void i596_tx_timeout (struct net_device *dev)
  782. {
  783. struct i596_private *lp = netdev_priv(dev);
  784. /* Transmitter timeout, serious problems. */
  785. DEB(DEB_ERRORS, printk(KERN_DEBUG
  786. "%s: transmit timed out, status resetting.\n",
  787. dev->name));
  788. dev->stats.tx_errors++;
  789. /* Try to restart the adaptor */
  790. if (lp->last_restart == dev->stats.tx_packets) {
  791. DEB(DEB_ERRORS, printk(KERN_DEBUG "Resetting board.\n"));
  792. /* Shutdown and restart */
  793. i596_reset (dev, lp);
  794. } else {
  795. /* Issue a channel attention signal */
  796. DEB(DEB_ERRORS, printk(KERN_DEBUG "Kicking board.\n"));
  797. lp->dma->scb.command = SWAP16(CUC_START | RX_START);
  798. DMA_WBACK_INV(dev, &(lp->dma->scb), sizeof(struct i596_scb));
  799. ca (dev);
  800. lp->last_restart = dev->stats.tx_packets;
  801. }
  802. netif_trans_update(dev); /* prevent tx timeout */
  803. netif_wake_queue (dev);
  804. }
  805. static netdev_tx_t i596_start_xmit(struct sk_buff *skb, struct net_device *dev)
  806. {
  807. struct i596_private *lp = netdev_priv(dev);
  808. struct tx_cmd *tx_cmd;
  809. struct i596_tbd *tbd;
  810. short length = skb->len;
  811. DEB(DEB_STARTTX, printk(KERN_DEBUG
  812. "%s: i596_start_xmit(%x,%p) called\n",
  813. dev->name, skb->len, skb->data));
  814. if (length < ETH_ZLEN) {
  815. if (skb_padto(skb, ETH_ZLEN))
  816. return NETDEV_TX_OK;
  817. length = ETH_ZLEN;
  818. }
  819. netif_stop_queue(dev);
  820. tx_cmd = lp->dma->tx_cmds + lp->next_tx_cmd;
  821. tbd = lp->dma->tbds + lp->next_tx_cmd;
  822. if (tx_cmd->cmd.command) {
  823. DEB(DEB_ERRORS, printk(KERN_DEBUG
  824. "%s: xmit ring full, dropping packet.\n",
  825. dev->name));
  826. dev->stats.tx_dropped++;
  827. dev_kfree_skb_any(skb);
  828. } else {
  829. if (++lp->next_tx_cmd == TX_RING_SIZE)
  830. lp->next_tx_cmd = 0;
  831. tx_cmd->tbd = SWAP32(virt_to_dma(lp, tbd));
  832. tbd->next = I596_NULL;
  833. tx_cmd->cmd.command = SWAP16(CMD_FLEX | CmdTx);
  834. tx_cmd->skb = skb;
  835. tx_cmd->pad = 0;
  836. tx_cmd->size = 0;
  837. tbd->pad = 0;
  838. tbd->size = SWAP16(EOF | length);
  839. tx_cmd->dma_addr = dma_map_single(dev->dev.parent, skb->data,
  840. skb->len, DMA_TO_DEVICE);
  841. tbd->data = SWAP32(tx_cmd->dma_addr);
  842. DEB(DEB_TXADDR, print_eth(skb->data, "tx-queued"));
  843. DMA_WBACK_INV(dev, tx_cmd, sizeof(struct tx_cmd));
  844. DMA_WBACK_INV(dev, tbd, sizeof(struct i596_tbd));
  845. i596_add_cmd(dev, &tx_cmd->cmd);
  846. dev->stats.tx_packets++;
  847. dev->stats.tx_bytes += length;
  848. }
  849. netif_start_queue(dev);
  850. return NETDEV_TX_OK;
  851. }
  852. static void print_eth(unsigned char *add, char *str)
  853. {
  854. printk(KERN_DEBUG "i596 0x%p, %pM --> %pM %02X%02X, %s\n",
  855. add, add + 6, add, add[12], add[13], str);
  856. }
  857. static const struct net_device_ops i596_netdev_ops = {
  858. .ndo_open = i596_open,
  859. .ndo_stop = i596_close,
  860. .ndo_start_xmit = i596_start_xmit,
  861. .ndo_set_rx_mode = set_multicast_list,
  862. .ndo_tx_timeout = i596_tx_timeout,
  863. .ndo_validate_addr = eth_validate_addr,
  864. .ndo_set_mac_address = eth_mac_addr,
  865. #ifdef CONFIG_NET_POLL_CONTROLLER
  866. .ndo_poll_controller = i596_poll_controller,
  867. #endif
  868. };
  869. static int i82596_probe(struct net_device *dev)
  870. {
  871. int i;
  872. struct i596_private *lp = netdev_priv(dev);
  873. struct i596_dma *dma;
  874. /* This lot is ensure things have been cache line aligned. */
  875. BUILD_BUG_ON(sizeof(struct i596_rfd) != 32);
  876. BUILD_BUG_ON(sizeof(struct i596_rbd) & 31);
  877. BUILD_BUG_ON(sizeof(struct tx_cmd) & 31);
  878. BUILD_BUG_ON(sizeof(struct i596_tbd) != 32);
  879. #ifndef __LP64__
  880. BUILD_BUG_ON(sizeof(struct i596_dma) > 4096);
  881. #endif
  882. if (!dev->base_addr || !dev->irq)
  883. return -ENODEV;
  884. dma = dma_alloc_attrs(dev->dev.parent, sizeof(struct i596_dma),
  885. &lp->dma_addr, GFP_KERNEL,
  886. LIB82596_DMA_ATTR);
  887. if (!dma) {
  888. printk(KERN_ERR "%s: Couldn't get shared memory\n", __FILE__);
  889. return -ENOMEM;
  890. }
  891. dev->netdev_ops = &i596_netdev_ops;
  892. dev->watchdog_timeo = TX_TIMEOUT;
  893. memset(dma, 0, sizeof(struct i596_dma));
  894. lp->dma = dma;
  895. dma->scb.command = 0;
  896. dma->scb.cmd = I596_NULL;
  897. dma->scb.rfd = I596_NULL;
  898. spin_lock_init(&lp->lock);
  899. DMA_WBACK_INV(dev, dma, sizeof(struct i596_dma));
  900. i = register_netdev(dev);
  901. if (i) {
  902. dma_free_attrs(dev->dev.parent, sizeof(struct i596_dma),
  903. dma, lp->dma_addr, LIB82596_DMA_ATTR);
  904. return i;
  905. }
  906. DEB(DEB_PROBE, printk(KERN_INFO "%s: 82596 at %#3lx, %pM IRQ %d.\n",
  907. dev->name, dev->base_addr, dev->dev_addr,
  908. dev->irq));
  909. DEB(DEB_INIT, printk(KERN_INFO
  910. "%s: dma at 0x%p (%d bytes), lp->scb at 0x%p\n",
  911. dev->name, dma, (int)sizeof(struct i596_dma),
  912. &dma->scb));
  913. return 0;
  914. }
  915. #ifdef CONFIG_NET_POLL_CONTROLLER
  916. static void i596_poll_controller(struct net_device *dev)
  917. {
  918. disable_irq(dev->irq);
  919. i596_interrupt(dev->irq, dev);
  920. enable_irq(dev->irq);
  921. }
  922. #endif
  923. static irqreturn_t i596_interrupt(int irq, void *dev_id)
  924. {
  925. struct net_device *dev = dev_id;
  926. struct i596_private *lp;
  927. struct i596_dma *dma;
  928. unsigned short status, ack_cmd = 0;
  929. lp = netdev_priv(dev);
  930. dma = lp->dma;
  931. spin_lock (&lp->lock);
  932. wait_cmd(dev, dma, 100, "i596 interrupt, timeout");
  933. status = SWAP16(dma->scb.status);
  934. DEB(DEB_INTS, printk(KERN_DEBUG
  935. "%s: i596 interrupt, IRQ %d, status %4.4x.\n",
  936. dev->name, dev->irq, status));
  937. ack_cmd = status & 0xf000;
  938. if (!ack_cmd) {
  939. DEB(DEB_ERRORS, printk(KERN_DEBUG
  940. "%s: interrupt with no events\n",
  941. dev->name));
  942. spin_unlock (&lp->lock);
  943. return IRQ_NONE;
  944. }
  945. if ((status & 0x8000) || (status & 0x2000)) {
  946. struct i596_cmd *ptr;
  947. if ((status & 0x8000))
  948. DEB(DEB_INTS,
  949. printk(KERN_DEBUG
  950. "%s: i596 interrupt completed command.\n",
  951. dev->name));
  952. if ((status & 0x2000))
  953. DEB(DEB_INTS,
  954. printk(KERN_DEBUG
  955. "%s: i596 interrupt command unit inactive %x.\n",
  956. dev->name, status & 0x0700));
  957. while (lp->cmd_head != NULL) {
  958. DMA_INV(dev, lp->cmd_head, sizeof(struct i596_cmd));
  959. if (!(lp->cmd_head->status & SWAP16(STAT_C)))
  960. break;
  961. ptr = lp->cmd_head;
  962. DEB(DEB_STATUS,
  963. printk(KERN_DEBUG
  964. "cmd_head->status = %04x, ->command = %04x\n",
  965. SWAP16(lp->cmd_head->status),
  966. SWAP16(lp->cmd_head->command)));
  967. lp->cmd_head = ptr->v_next;
  968. lp->cmd_backlog--;
  969. switch (SWAP16(ptr->command) & 0x7) {
  970. case CmdTx:
  971. {
  972. struct tx_cmd *tx_cmd = (struct tx_cmd *) ptr;
  973. struct sk_buff *skb = tx_cmd->skb;
  974. if (ptr->status & SWAP16(STAT_OK)) {
  975. DEB(DEB_TXADDR,
  976. print_eth(skb->data, "tx-done"));
  977. } else {
  978. dev->stats.tx_errors++;
  979. if (ptr->status & SWAP16(0x0020))
  980. dev->stats.collisions++;
  981. if (!(ptr->status & SWAP16(0x0040)))
  982. dev->stats.tx_heartbeat_errors++;
  983. if (ptr->status & SWAP16(0x0400))
  984. dev->stats.tx_carrier_errors++;
  985. if (ptr->status & SWAP16(0x0800))
  986. dev->stats.collisions++;
  987. if (ptr->status & SWAP16(0x1000))
  988. dev->stats.tx_aborted_errors++;
  989. }
  990. dma_unmap_single(dev->dev.parent,
  991. tx_cmd->dma_addr,
  992. skb->len, DMA_TO_DEVICE);
  993. dev_kfree_skb_irq(skb);
  994. tx_cmd->cmd.command = 0; /* Mark free */
  995. break;
  996. }
  997. case CmdTDR:
  998. {
  999. unsigned short status = SWAP16(((struct tdr_cmd *)ptr)->status);
  1000. if (status & 0x8000) {
  1001. DEB(DEB_ANY,
  1002. printk(KERN_DEBUG "%s: link ok.\n",
  1003. dev->name));
  1004. } else {
  1005. if (status & 0x4000)
  1006. printk(KERN_ERR
  1007. "%s: Transceiver problem.\n",
  1008. dev->name);
  1009. if (status & 0x2000)
  1010. printk(KERN_ERR
  1011. "%s: Termination problem.\n",
  1012. dev->name);
  1013. if (status & 0x1000)
  1014. printk(KERN_ERR
  1015. "%s: Short circuit.\n",
  1016. dev->name);
  1017. DEB(DEB_TDR,
  1018. printk(KERN_DEBUG "%s: Time %d.\n",
  1019. dev->name, status & 0x07ff));
  1020. }
  1021. break;
  1022. }
  1023. case CmdConfigure:
  1024. /*
  1025. * Zap command so set_multicast_list() know
  1026. * it is free
  1027. */
  1028. ptr->command = 0;
  1029. break;
  1030. }
  1031. ptr->v_next = NULL;
  1032. ptr->b_next = I596_NULL;
  1033. DMA_WBACK(dev, ptr, sizeof(struct i596_cmd));
  1034. lp->last_cmd = jiffies;
  1035. }
  1036. /* This mess is arranging that only the last of any outstanding
  1037. * commands has the interrupt bit set. Should probably really
  1038. * only add to the cmd queue when the CU is stopped.
  1039. */
  1040. ptr = lp->cmd_head;
  1041. while ((ptr != NULL) && (ptr != lp->cmd_tail)) {
  1042. struct i596_cmd *prev = ptr;
  1043. ptr->command &= SWAP16(0x1fff);
  1044. ptr = ptr->v_next;
  1045. DMA_WBACK_INV(dev, prev, sizeof(struct i596_cmd));
  1046. }
  1047. if (lp->cmd_head != NULL)
  1048. ack_cmd |= CUC_START;
  1049. dma->scb.cmd = SWAP32(virt_to_dma(lp, &lp->cmd_head->status));
  1050. DMA_WBACK_INV(dev, &dma->scb, sizeof(struct i596_scb));
  1051. }
  1052. if ((status & 0x1000) || (status & 0x4000)) {
  1053. if ((status & 0x4000))
  1054. DEB(DEB_INTS,
  1055. printk(KERN_DEBUG
  1056. "%s: i596 interrupt received a frame.\n",
  1057. dev->name));
  1058. i596_rx(dev);
  1059. /* Only RX_START if stopped - RGH 07-07-96 */
  1060. if (status & 0x1000) {
  1061. if (netif_running(dev)) {
  1062. DEB(DEB_ERRORS,
  1063. printk(KERN_DEBUG
  1064. "%s: i596 interrupt receive unit inactive, status 0x%x\n",
  1065. dev->name, status));
  1066. ack_cmd |= RX_START;
  1067. dev->stats.rx_errors++;
  1068. dev->stats.rx_fifo_errors++;
  1069. rebuild_rx_bufs(dev);
  1070. }
  1071. }
  1072. }
  1073. wait_cmd(dev, dma, 100, "i596 interrupt, timeout");
  1074. dma->scb.command = SWAP16(ack_cmd);
  1075. DMA_WBACK(dev, &dma->scb, sizeof(struct i596_scb));
  1076. /* DANGER: I suspect that some kind of interrupt
  1077. acknowledgement aside from acking the 82596 might be needed
  1078. here... but it's running acceptably without */
  1079. ca(dev);
  1080. wait_cmd(dev, dma, 100, "i596 interrupt, exit timeout");
  1081. DEB(DEB_INTS, printk(KERN_DEBUG "%s: exiting interrupt.\n", dev->name));
  1082. spin_unlock (&lp->lock);
  1083. return IRQ_HANDLED;
  1084. }
  1085. static int i596_close(struct net_device *dev)
  1086. {
  1087. struct i596_private *lp = netdev_priv(dev);
  1088. unsigned long flags;
  1089. netif_stop_queue(dev);
  1090. DEB(DEB_INIT,
  1091. printk(KERN_DEBUG
  1092. "%s: Shutting down ethercard, status was %4.4x.\n",
  1093. dev->name, SWAP16(lp->dma->scb.status)));
  1094. spin_lock_irqsave(&lp->lock, flags);
  1095. wait_cmd(dev, lp->dma, 100, "close1 timed out");
  1096. lp->dma->scb.command = SWAP16(CUC_ABORT | RX_ABORT);
  1097. DMA_WBACK(dev, &lp->dma->scb, sizeof(struct i596_scb));
  1098. ca(dev);
  1099. wait_cmd(dev, lp->dma, 100, "close2 timed out");
  1100. spin_unlock_irqrestore(&lp->lock, flags);
  1101. DEB(DEB_STRUCT, i596_display_data(dev));
  1102. i596_cleanup_cmd(dev, lp);
  1103. free_irq(dev->irq, dev);
  1104. remove_rx_bufs(dev);
  1105. return 0;
  1106. }
  1107. /*
  1108. * Set or clear the multicast filter for this adaptor.
  1109. */
  1110. static void set_multicast_list(struct net_device *dev)
  1111. {
  1112. struct i596_private *lp = netdev_priv(dev);
  1113. struct i596_dma *dma = lp->dma;
  1114. int config = 0, cnt;
  1115. DEB(DEB_MULTI,
  1116. printk(KERN_DEBUG
  1117. "%s: set multicast list, %d entries, promisc %s, allmulti %s\n",
  1118. dev->name, netdev_mc_count(dev),
  1119. dev->flags & IFF_PROMISC ? "ON" : "OFF",
  1120. dev->flags & IFF_ALLMULTI ? "ON" : "OFF"));
  1121. if ((dev->flags & IFF_PROMISC) &&
  1122. !(dma->cf_cmd.i596_config[8] & 0x01)) {
  1123. dma->cf_cmd.i596_config[8] |= 0x01;
  1124. config = 1;
  1125. }
  1126. if (!(dev->flags & IFF_PROMISC) &&
  1127. (dma->cf_cmd.i596_config[8] & 0x01)) {
  1128. dma->cf_cmd.i596_config[8] &= ~0x01;
  1129. config = 1;
  1130. }
  1131. if ((dev->flags & IFF_ALLMULTI) &&
  1132. (dma->cf_cmd.i596_config[11] & 0x20)) {
  1133. dma->cf_cmd.i596_config[11] &= ~0x20;
  1134. config = 1;
  1135. }
  1136. if (!(dev->flags & IFF_ALLMULTI) &&
  1137. !(dma->cf_cmd.i596_config[11] & 0x20)) {
  1138. dma->cf_cmd.i596_config[11] |= 0x20;
  1139. config = 1;
  1140. }
  1141. if (config) {
  1142. if (dma->cf_cmd.cmd.command)
  1143. printk(KERN_INFO
  1144. "%s: config change request already queued\n",
  1145. dev->name);
  1146. else {
  1147. dma->cf_cmd.cmd.command = SWAP16(CmdConfigure);
  1148. DMA_WBACK_INV(dev, &dma->cf_cmd, sizeof(struct cf_cmd));
  1149. i596_add_cmd(dev, &dma->cf_cmd.cmd);
  1150. }
  1151. }
  1152. cnt = netdev_mc_count(dev);
  1153. if (cnt > MAX_MC_CNT) {
  1154. cnt = MAX_MC_CNT;
  1155. printk(KERN_NOTICE "%s: Only %d multicast addresses supported",
  1156. dev->name, cnt);
  1157. }
  1158. if (!netdev_mc_empty(dev)) {
  1159. struct netdev_hw_addr *ha;
  1160. unsigned char *cp;
  1161. struct mc_cmd *cmd;
  1162. cmd = &dma->mc_cmd;
  1163. cmd->cmd.command = SWAP16(CmdMulticastList);
  1164. cmd->mc_cnt = SWAP16(netdev_mc_count(dev) * 6);
  1165. cp = cmd->mc_addrs;
  1166. netdev_for_each_mc_addr(ha, dev) {
  1167. if (!cnt--)
  1168. break;
  1169. memcpy(cp, ha->addr, ETH_ALEN);
  1170. if (i596_debug > 1)
  1171. DEB(DEB_MULTI,
  1172. printk(KERN_DEBUG
  1173. "%s: Adding address %pM\n",
  1174. dev->name, cp));
  1175. cp += ETH_ALEN;
  1176. }
  1177. DMA_WBACK_INV(dev, &dma->mc_cmd, sizeof(struct mc_cmd));
  1178. i596_add_cmd(dev, &cmd->cmd);
  1179. }
  1180. }