ethoc.c 32 KB

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  1. /*
  2. * linux/drivers/net/ethernet/ethoc.c
  3. *
  4. * Copyright (C) 2007-2008 Avionic Design Development GmbH
  5. * Copyright (C) 2008-2009 Avionic Design GmbH
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * Written by Thierry Reding <thierry.reding@avionic-design.de>
  12. */
  13. #include <linux/dma-mapping.h>
  14. #include <linux/etherdevice.h>
  15. #include <linux/clk.h>
  16. #include <linux/crc32.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/io.h>
  19. #include <linux/mii.h>
  20. #include <linux/phy.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/sched.h>
  23. #include <linux/slab.h>
  24. #include <linux/of.h>
  25. #include <linux/of_net.h>
  26. #include <linux/module.h>
  27. #include <net/ethoc.h>
  28. static int buffer_size = 0x8000; /* 32 KBytes */
  29. module_param(buffer_size, int, 0);
  30. MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");
  31. /* register offsets */
  32. #define MODER 0x00
  33. #define INT_SOURCE 0x04
  34. #define INT_MASK 0x08
  35. #define IPGT 0x0c
  36. #define IPGR1 0x10
  37. #define IPGR2 0x14
  38. #define PACKETLEN 0x18
  39. #define COLLCONF 0x1c
  40. #define TX_BD_NUM 0x20
  41. #define CTRLMODER 0x24
  42. #define MIIMODER 0x28
  43. #define MIICOMMAND 0x2c
  44. #define MIIADDRESS 0x30
  45. #define MIITX_DATA 0x34
  46. #define MIIRX_DATA 0x38
  47. #define MIISTATUS 0x3c
  48. #define MAC_ADDR0 0x40
  49. #define MAC_ADDR1 0x44
  50. #define ETH_HASH0 0x48
  51. #define ETH_HASH1 0x4c
  52. #define ETH_TXCTRL 0x50
  53. #define ETH_END 0x54
  54. /* mode register */
  55. #define MODER_RXEN (1 << 0) /* receive enable */
  56. #define MODER_TXEN (1 << 1) /* transmit enable */
  57. #define MODER_NOPRE (1 << 2) /* no preamble */
  58. #define MODER_BRO (1 << 3) /* broadcast address */
  59. #define MODER_IAM (1 << 4) /* individual address mode */
  60. #define MODER_PRO (1 << 5) /* promiscuous mode */
  61. #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
  62. #define MODER_LOOP (1 << 7) /* loopback */
  63. #define MODER_NBO (1 << 8) /* no back-off */
  64. #define MODER_EDE (1 << 9) /* excess defer enable */
  65. #define MODER_FULLD (1 << 10) /* full duplex */
  66. #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
  67. #define MODER_DCRC (1 << 12) /* delayed CRC enable */
  68. #define MODER_CRC (1 << 13) /* CRC enable */
  69. #define MODER_HUGE (1 << 14) /* huge packets enable */
  70. #define MODER_PAD (1 << 15) /* padding enabled */
  71. #define MODER_RSM (1 << 16) /* receive small packets */
  72. /* interrupt source and mask registers */
  73. #define INT_MASK_TXF (1 << 0) /* transmit frame */
  74. #define INT_MASK_TXE (1 << 1) /* transmit error */
  75. #define INT_MASK_RXF (1 << 2) /* receive frame */
  76. #define INT_MASK_RXE (1 << 3) /* receive error */
  77. #define INT_MASK_BUSY (1 << 4)
  78. #define INT_MASK_TXC (1 << 5) /* transmit control frame */
  79. #define INT_MASK_RXC (1 << 6) /* receive control frame */
  80. #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
  81. #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
  82. #define INT_MASK_ALL ( \
  83. INT_MASK_TXF | INT_MASK_TXE | \
  84. INT_MASK_RXF | INT_MASK_RXE | \
  85. INT_MASK_TXC | INT_MASK_RXC | \
  86. INT_MASK_BUSY \
  87. )
  88. /* packet length register */
  89. #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
  90. #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
  91. #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
  92. PACKETLEN_MAX(max))
  93. /* transmit buffer number register */
  94. #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
  95. /* control module mode register */
  96. #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
  97. #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
  98. #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
  99. /* MII mode register */
  100. #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
  101. #define MIIMODER_NOPRE (1 << 8) /* no preamble */
  102. /* MII command register */
  103. #define MIICOMMAND_SCAN (1 << 0) /* scan status */
  104. #define MIICOMMAND_READ (1 << 1) /* read status */
  105. #define MIICOMMAND_WRITE (1 << 2) /* write control data */
  106. /* MII address register */
  107. #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
  108. #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
  109. #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
  110. MIIADDRESS_RGAD(reg))
  111. /* MII transmit data register */
  112. #define MIITX_DATA_VAL(x) ((x) & 0xffff)
  113. /* MII receive data register */
  114. #define MIIRX_DATA_VAL(x) ((x) & 0xffff)
  115. /* MII status register */
  116. #define MIISTATUS_LINKFAIL (1 << 0)
  117. #define MIISTATUS_BUSY (1 << 1)
  118. #define MIISTATUS_INVALID (1 << 2)
  119. /* TX buffer descriptor */
  120. #define TX_BD_CS (1 << 0) /* carrier sense lost */
  121. #define TX_BD_DF (1 << 1) /* defer indication */
  122. #define TX_BD_LC (1 << 2) /* late collision */
  123. #define TX_BD_RL (1 << 3) /* retransmission limit */
  124. #define TX_BD_RETRY_MASK (0x00f0)
  125. #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
  126. #define TX_BD_UR (1 << 8) /* transmitter underrun */
  127. #define TX_BD_CRC (1 << 11) /* TX CRC enable */
  128. #define TX_BD_PAD (1 << 12) /* pad enable for short packets */
  129. #define TX_BD_WRAP (1 << 13)
  130. #define TX_BD_IRQ (1 << 14) /* interrupt request enable */
  131. #define TX_BD_READY (1 << 15) /* TX buffer ready */
  132. #define TX_BD_LEN(x) (((x) & 0xffff) << 16)
  133. #define TX_BD_LEN_MASK (0xffff << 16)
  134. #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
  135. TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
  136. /* RX buffer descriptor */
  137. #define RX_BD_LC (1 << 0) /* late collision */
  138. #define RX_BD_CRC (1 << 1) /* RX CRC error */
  139. #define RX_BD_SF (1 << 2) /* short frame */
  140. #define RX_BD_TL (1 << 3) /* too long */
  141. #define RX_BD_DN (1 << 4) /* dribble nibble */
  142. #define RX_BD_IS (1 << 5) /* invalid symbol */
  143. #define RX_BD_OR (1 << 6) /* receiver overrun */
  144. #define RX_BD_MISS (1 << 7)
  145. #define RX_BD_CF (1 << 8) /* control frame */
  146. #define RX_BD_WRAP (1 << 13)
  147. #define RX_BD_IRQ (1 << 14) /* interrupt request enable */
  148. #define RX_BD_EMPTY (1 << 15)
  149. #define RX_BD_LEN(x) (((x) & 0xffff) << 16)
  150. #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
  151. RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
  152. #define ETHOC_BUFSIZ 1536
  153. #define ETHOC_ZLEN 64
  154. #define ETHOC_BD_BASE 0x400
  155. #define ETHOC_TIMEOUT (HZ / 2)
  156. #define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
  157. /**
  158. * struct ethoc - driver-private device structure
  159. * @iobase: pointer to I/O memory region
  160. * @membase: pointer to buffer memory region
  161. * @num_bd: number of buffer descriptors
  162. * @num_tx: number of send buffers
  163. * @cur_tx: last send buffer written
  164. * @dty_tx: last buffer actually sent
  165. * @num_rx: number of receive buffers
  166. * @cur_rx: current receive buffer
  167. * @vma: pointer to array of virtual memory addresses for buffers
  168. * @netdev: pointer to network device structure
  169. * @napi: NAPI structure
  170. * @msg_enable: device state flags
  171. * @lock: device lock
  172. * @mdio: MDIO bus for PHY access
  173. * @phy_id: address of attached PHY
  174. */
  175. struct ethoc {
  176. void __iomem *iobase;
  177. void __iomem *membase;
  178. bool big_endian;
  179. unsigned int num_bd;
  180. unsigned int num_tx;
  181. unsigned int cur_tx;
  182. unsigned int dty_tx;
  183. unsigned int num_rx;
  184. unsigned int cur_rx;
  185. void **vma;
  186. struct net_device *netdev;
  187. struct napi_struct napi;
  188. u32 msg_enable;
  189. spinlock_t lock;
  190. struct mii_bus *mdio;
  191. struct clk *clk;
  192. s8 phy_id;
  193. int old_link;
  194. int old_duplex;
  195. };
  196. /**
  197. * struct ethoc_bd - buffer descriptor
  198. * @stat: buffer statistics
  199. * @addr: physical memory address
  200. */
  201. struct ethoc_bd {
  202. u32 stat;
  203. u32 addr;
  204. };
  205. static inline u32 ethoc_read(struct ethoc *dev, loff_t offset)
  206. {
  207. if (dev->big_endian)
  208. return ioread32be(dev->iobase + offset);
  209. else
  210. return ioread32(dev->iobase + offset);
  211. }
  212. static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
  213. {
  214. if (dev->big_endian)
  215. iowrite32be(data, dev->iobase + offset);
  216. else
  217. iowrite32(data, dev->iobase + offset);
  218. }
  219. static inline void ethoc_read_bd(struct ethoc *dev, int index,
  220. struct ethoc_bd *bd)
  221. {
  222. loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
  223. bd->stat = ethoc_read(dev, offset + 0);
  224. bd->addr = ethoc_read(dev, offset + 4);
  225. }
  226. static inline void ethoc_write_bd(struct ethoc *dev, int index,
  227. const struct ethoc_bd *bd)
  228. {
  229. loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
  230. ethoc_write(dev, offset + 0, bd->stat);
  231. ethoc_write(dev, offset + 4, bd->addr);
  232. }
  233. static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask)
  234. {
  235. u32 imask = ethoc_read(dev, INT_MASK);
  236. imask |= mask;
  237. ethoc_write(dev, INT_MASK, imask);
  238. }
  239. static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask)
  240. {
  241. u32 imask = ethoc_read(dev, INT_MASK);
  242. imask &= ~mask;
  243. ethoc_write(dev, INT_MASK, imask);
  244. }
  245. static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask)
  246. {
  247. ethoc_write(dev, INT_SOURCE, mask);
  248. }
  249. static inline void ethoc_enable_rx_and_tx(struct ethoc *dev)
  250. {
  251. u32 mode = ethoc_read(dev, MODER);
  252. mode |= MODER_RXEN | MODER_TXEN;
  253. ethoc_write(dev, MODER, mode);
  254. }
  255. static inline void ethoc_disable_rx_and_tx(struct ethoc *dev)
  256. {
  257. u32 mode = ethoc_read(dev, MODER);
  258. mode &= ~(MODER_RXEN | MODER_TXEN);
  259. ethoc_write(dev, MODER, mode);
  260. }
  261. static int ethoc_init_ring(struct ethoc *dev, unsigned long mem_start)
  262. {
  263. struct ethoc_bd bd;
  264. int i;
  265. void *vma;
  266. dev->cur_tx = 0;
  267. dev->dty_tx = 0;
  268. dev->cur_rx = 0;
  269. ethoc_write(dev, TX_BD_NUM, dev->num_tx);
  270. /* setup transmission buffers */
  271. bd.addr = mem_start;
  272. bd.stat = TX_BD_IRQ | TX_BD_CRC;
  273. vma = dev->membase;
  274. for (i = 0; i < dev->num_tx; i++) {
  275. if (i == dev->num_tx - 1)
  276. bd.stat |= TX_BD_WRAP;
  277. ethoc_write_bd(dev, i, &bd);
  278. bd.addr += ETHOC_BUFSIZ;
  279. dev->vma[i] = vma;
  280. vma += ETHOC_BUFSIZ;
  281. }
  282. bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
  283. for (i = 0; i < dev->num_rx; i++) {
  284. if (i == dev->num_rx - 1)
  285. bd.stat |= RX_BD_WRAP;
  286. ethoc_write_bd(dev, dev->num_tx + i, &bd);
  287. bd.addr += ETHOC_BUFSIZ;
  288. dev->vma[dev->num_tx + i] = vma;
  289. vma += ETHOC_BUFSIZ;
  290. }
  291. return 0;
  292. }
  293. static int ethoc_reset(struct ethoc *dev)
  294. {
  295. u32 mode;
  296. /* TODO: reset controller? */
  297. ethoc_disable_rx_and_tx(dev);
  298. /* TODO: setup registers */
  299. /* enable FCS generation and automatic padding */
  300. mode = ethoc_read(dev, MODER);
  301. mode |= MODER_CRC | MODER_PAD;
  302. ethoc_write(dev, MODER, mode);
  303. /* set full-duplex mode */
  304. mode = ethoc_read(dev, MODER);
  305. mode |= MODER_FULLD;
  306. ethoc_write(dev, MODER, mode);
  307. ethoc_write(dev, IPGT, 0x15);
  308. ethoc_ack_irq(dev, INT_MASK_ALL);
  309. ethoc_enable_irq(dev, INT_MASK_ALL);
  310. ethoc_enable_rx_and_tx(dev);
  311. return 0;
  312. }
  313. static unsigned int ethoc_update_rx_stats(struct ethoc *dev,
  314. struct ethoc_bd *bd)
  315. {
  316. struct net_device *netdev = dev->netdev;
  317. unsigned int ret = 0;
  318. if (bd->stat & RX_BD_TL) {
  319. dev_err(&netdev->dev, "RX: frame too long\n");
  320. netdev->stats.rx_length_errors++;
  321. ret++;
  322. }
  323. if (bd->stat & RX_BD_SF) {
  324. dev_err(&netdev->dev, "RX: frame too short\n");
  325. netdev->stats.rx_length_errors++;
  326. ret++;
  327. }
  328. if (bd->stat & RX_BD_DN) {
  329. dev_err(&netdev->dev, "RX: dribble nibble\n");
  330. netdev->stats.rx_frame_errors++;
  331. }
  332. if (bd->stat & RX_BD_CRC) {
  333. dev_err(&netdev->dev, "RX: wrong CRC\n");
  334. netdev->stats.rx_crc_errors++;
  335. ret++;
  336. }
  337. if (bd->stat & RX_BD_OR) {
  338. dev_err(&netdev->dev, "RX: overrun\n");
  339. netdev->stats.rx_over_errors++;
  340. ret++;
  341. }
  342. if (bd->stat & RX_BD_MISS)
  343. netdev->stats.rx_missed_errors++;
  344. if (bd->stat & RX_BD_LC) {
  345. dev_err(&netdev->dev, "RX: late collision\n");
  346. netdev->stats.collisions++;
  347. ret++;
  348. }
  349. return ret;
  350. }
  351. static int ethoc_rx(struct net_device *dev, int limit)
  352. {
  353. struct ethoc *priv = netdev_priv(dev);
  354. int count;
  355. for (count = 0; count < limit; ++count) {
  356. unsigned int entry;
  357. struct ethoc_bd bd;
  358. entry = priv->num_tx + priv->cur_rx;
  359. ethoc_read_bd(priv, entry, &bd);
  360. if (bd.stat & RX_BD_EMPTY) {
  361. ethoc_ack_irq(priv, INT_MASK_RX);
  362. /* If packet (interrupt) came in between checking
  363. * BD_EMTPY and clearing the interrupt source, then we
  364. * risk missing the packet as the RX interrupt won't
  365. * trigger right away when we reenable it; hence, check
  366. * BD_EMTPY here again to make sure there isn't such a
  367. * packet waiting for us...
  368. */
  369. ethoc_read_bd(priv, entry, &bd);
  370. if (bd.stat & RX_BD_EMPTY)
  371. break;
  372. }
  373. if (ethoc_update_rx_stats(priv, &bd) == 0) {
  374. int size = bd.stat >> 16;
  375. struct sk_buff *skb;
  376. size -= 4; /* strip the CRC */
  377. skb = netdev_alloc_skb_ip_align(dev, size);
  378. if (likely(skb)) {
  379. void *src = priv->vma[entry];
  380. memcpy_fromio(skb_put(skb, size), src, size);
  381. skb->protocol = eth_type_trans(skb, dev);
  382. dev->stats.rx_packets++;
  383. dev->stats.rx_bytes += size;
  384. netif_receive_skb(skb);
  385. } else {
  386. if (net_ratelimit())
  387. dev_warn(&dev->dev,
  388. "low on memory - packet dropped\n");
  389. dev->stats.rx_dropped++;
  390. break;
  391. }
  392. }
  393. /* clear the buffer descriptor so it can be reused */
  394. bd.stat &= ~RX_BD_STATS;
  395. bd.stat |= RX_BD_EMPTY;
  396. ethoc_write_bd(priv, entry, &bd);
  397. if (++priv->cur_rx == priv->num_rx)
  398. priv->cur_rx = 0;
  399. }
  400. return count;
  401. }
  402. static void ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
  403. {
  404. struct net_device *netdev = dev->netdev;
  405. if (bd->stat & TX_BD_LC) {
  406. dev_err(&netdev->dev, "TX: late collision\n");
  407. netdev->stats.tx_window_errors++;
  408. }
  409. if (bd->stat & TX_BD_RL) {
  410. dev_err(&netdev->dev, "TX: retransmit limit\n");
  411. netdev->stats.tx_aborted_errors++;
  412. }
  413. if (bd->stat & TX_BD_UR) {
  414. dev_err(&netdev->dev, "TX: underrun\n");
  415. netdev->stats.tx_fifo_errors++;
  416. }
  417. if (bd->stat & TX_BD_CS) {
  418. dev_err(&netdev->dev, "TX: carrier sense lost\n");
  419. netdev->stats.tx_carrier_errors++;
  420. }
  421. if (bd->stat & TX_BD_STATS)
  422. netdev->stats.tx_errors++;
  423. netdev->stats.collisions += (bd->stat >> 4) & 0xf;
  424. netdev->stats.tx_bytes += bd->stat >> 16;
  425. netdev->stats.tx_packets++;
  426. }
  427. static int ethoc_tx(struct net_device *dev, int limit)
  428. {
  429. struct ethoc *priv = netdev_priv(dev);
  430. int count;
  431. struct ethoc_bd bd;
  432. for (count = 0; count < limit; ++count) {
  433. unsigned int entry;
  434. entry = priv->dty_tx & (priv->num_tx-1);
  435. ethoc_read_bd(priv, entry, &bd);
  436. if (bd.stat & TX_BD_READY || (priv->dty_tx == priv->cur_tx)) {
  437. ethoc_ack_irq(priv, INT_MASK_TX);
  438. /* If interrupt came in between reading in the BD
  439. * and clearing the interrupt source, then we risk
  440. * missing the event as the TX interrupt won't trigger
  441. * right away when we reenable it; hence, check
  442. * BD_EMPTY here again to make sure there isn't such an
  443. * event pending...
  444. */
  445. ethoc_read_bd(priv, entry, &bd);
  446. if (bd.stat & TX_BD_READY ||
  447. (priv->dty_tx == priv->cur_tx))
  448. break;
  449. }
  450. ethoc_update_tx_stats(priv, &bd);
  451. priv->dty_tx++;
  452. }
  453. if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
  454. netif_wake_queue(dev);
  455. return count;
  456. }
  457. static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
  458. {
  459. struct net_device *dev = dev_id;
  460. struct ethoc *priv = netdev_priv(dev);
  461. u32 pending;
  462. u32 mask;
  463. /* Figure out what triggered the interrupt...
  464. * The tricky bit here is that the interrupt source bits get
  465. * set in INT_SOURCE for an event regardless of whether that
  466. * event is masked or not. Thus, in order to figure out what
  467. * triggered the interrupt, we need to remove the sources
  468. * for all events that are currently masked. This behaviour
  469. * is not particularly well documented but reasonable...
  470. */
  471. mask = ethoc_read(priv, INT_MASK);
  472. pending = ethoc_read(priv, INT_SOURCE);
  473. pending &= mask;
  474. if (unlikely(pending == 0))
  475. return IRQ_NONE;
  476. ethoc_ack_irq(priv, pending);
  477. /* We always handle the dropped packet interrupt */
  478. if (pending & INT_MASK_BUSY) {
  479. dev_dbg(&dev->dev, "packet dropped\n");
  480. dev->stats.rx_dropped++;
  481. }
  482. /* Handle receive/transmit event by switching to polling */
  483. if (pending & (INT_MASK_TX | INT_MASK_RX)) {
  484. ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX);
  485. napi_schedule(&priv->napi);
  486. }
  487. return IRQ_HANDLED;
  488. }
  489. static int ethoc_get_mac_address(struct net_device *dev, void *addr)
  490. {
  491. struct ethoc *priv = netdev_priv(dev);
  492. u8 *mac = (u8 *)addr;
  493. u32 reg;
  494. reg = ethoc_read(priv, MAC_ADDR0);
  495. mac[2] = (reg >> 24) & 0xff;
  496. mac[3] = (reg >> 16) & 0xff;
  497. mac[4] = (reg >> 8) & 0xff;
  498. mac[5] = (reg >> 0) & 0xff;
  499. reg = ethoc_read(priv, MAC_ADDR1);
  500. mac[0] = (reg >> 8) & 0xff;
  501. mac[1] = (reg >> 0) & 0xff;
  502. return 0;
  503. }
  504. static int ethoc_poll(struct napi_struct *napi, int budget)
  505. {
  506. struct ethoc *priv = container_of(napi, struct ethoc, napi);
  507. int rx_work_done = 0;
  508. int tx_work_done = 0;
  509. rx_work_done = ethoc_rx(priv->netdev, budget);
  510. tx_work_done = ethoc_tx(priv->netdev, budget);
  511. if (rx_work_done < budget && tx_work_done < budget) {
  512. napi_complete_done(napi, rx_work_done);
  513. ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX);
  514. }
  515. return rx_work_done;
  516. }
  517. static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
  518. {
  519. struct ethoc *priv = bus->priv;
  520. int i;
  521. ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
  522. ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
  523. for (i = 0; i < 5; i++) {
  524. u32 status = ethoc_read(priv, MIISTATUS);
  525. if (!(status & MIISTATUS_BUSY)) {
  526. u32 data = ethoc_read(priv, MIIRX_DATA);
  527. /* reset MII command register */
  528. ethoc_write(priv, MIICOMMAND, 0);
  529. return data;
  530. }
  531. usleep_range(100, 200);
  532. }
  533. return -EBUSY;
  534. }
  535. static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
  536. {
  537. struct ethoc *priv = bus->priv;
  538. int i;
  539. ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
  540. ethoc_write(priv, MIITX_DATA, val);
  541. ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
  542. for (i = 0; i < 5; i++) {
  543. u32 stat = ethoc_read(priv, MIISTATUS);
  544. if (!(stat & MIISTATUS_BUSY)) {
  545. /* reset MII command register */
  546. ethoc_write(priv, MIICOMMAND, 0);
  547. return 0;
  548. }
  549. usleep_range(100, 200);
  550. }
  551. return -EBUSY;
  552. }
  553. static void ethoc_mdio_poll(struct net_device *dev)
  554. {
  555. struct ethoc *priv = netdev_priv(dev);
  556. struct phy_device *phydev = dev->phydev;
  557. bool changed = false;
  558. u32 mode;
  559. if (priv->old_link != phydev->link) {
  560. changed = true;
  561. priv->old_link = phydev->link;
  562. }
  563. if (priv->old_duplex != phydev->duplex) {
  564. changed = true;
  565. priv->old_duplex = phydev->duplex;
  566. }
  567. if (!changed)
  568. return;
  569. mode = ethoc_read(priv, MODER);
  570. if (phydev->duplex == DUPLEX_FULL)
  571. mode |= MODER_FULLD;
  572. else
  573. mode &= ~MODER_FULLD;
  574. ethoc_write(priv, MODER, mode);
  575. phy_print_status(phydev);
  576. }
  577. static int ethoc_mdio_probe(struct net_device *dev)
  578. {
  579. struct ethoc *priv = netdev_priv(dev);
  580. struct phy_device *phy;
  581. int err;
  582. if (priv->phy_id != -1)
  583. phy = mdiobus_get_phy(priv->mdio, priv->phy_id);
  584. else
  585. phy = phy_find_first(priv->mdio);
  586. if (!phy) {
  587. dev_err(&dev->dev, "no PHY found\n");
  588. return -ENXIO;
  589. }
  590. priv->old_duplex = -1;
  591. priv->old_link = -1;
  592. err = phy_connect_direct(dev, phy, ethoc_mdio_poll,
  593. PHY_INTERFACE_MODE_GMII);
  594. if (err) {
  595. dev_err(&dev->dev, "could not attach to PHY\n");
  596. return err;
  597. }
  598. phy->advertising &= ~(ADVERTISED_1000baseT_Full |
  599. ADVERTISED_1000baseT_Half);
  600. phy->supported &= ~(SUPPORTED_1000baseT_Full |
  601. SUPPORTED_1000baseT_Half);
  602. return 0;
  603. }
  604. static int ethoc_open(struct net_device *dev)
  605. {
  606. struct ethoc *priv = netdev_priv(dev);
  607. int ret;
  608. ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED,
  609. dev->name, dev);
  610. if (ret)
  611. return ret;
  612. napi_enable(&priv->napi);
  613. ethoc_init_ring(priv, dev->mem_start);
  614. ethoc_reset(priv);
  615. if (netif_queue_stopped(dev)) {
  616. dev_dbg(&dev->dev, " resuming queue\n");
  617. netif_wake_queue(dev);
  618. } else {
  619. dev_dbg(&dev->dev, " starting queue\n");
  620. netif_start_queue(dev);
  621. }
  622. priv->old_link = -1;
  623. priv->old_duplex = -1;
  624. phy_start(dev->phydev);
  625. if (netif_msg_ifup(priv)) {
  626. dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",
  627. dev->base_addr, dev->mem_start, dev->mem_end);
  628. }
  629. return 0;
  630. }
  631. static int ethoc_stop(struct net_device *dev)
  632. {
  633. struct ethoc *priv = netdev_priv(dev);
  634. napi_disable(&priv->napi);
  635. if (dev->phydev)
  636. phy_stop(dev->phydev);
  637. ethoc_disable_rx_and_tx(priv);
  638. free_irq(dev->irq, dev);
  639. if (!netif_queue_stopped(dev))
  640. netif_stop_queue(dev);
  641. return 0;
  642. }
  643. static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  644. {
  645. struct ethoc *priv = netdev_priv(dev);
  646. struct mii_ioctl_data *mdio = if_mii(ifr);
  647. struct phy_device *phy = NULL;
  648. if (!netif_running(dev))
  649. return -EINVAL;
  650. if (cmd != SIOCGMIIPHY) {
  651. if (mdio->phy_id >= PHY_MAX_ADDR)
  652. return -ERANGE;
  653. phy = mdiobus_get_phy(priv->mdio, mdio->phy_id);
  654. if (!phy)
  655. return -ENODEV;
  656. } else {
  657. phy = dev->phydev;
  658. }
  659. return phy_mii_ioctl(phy, ifr, cmd);
  660. }
  661. static void ethoc_do_set_mac_address(struct net_device *dev)
  662. {
  663. struct ethoc *priv = netdev_priv(dev);
  664. unsigned char *mac = dev->dev_addr;
  665. ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
  666. (mac[4] << 8) | (mac[5] << 0));
  667. ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
  668. }
  669. static int ethoc_set_mac_address(struct net_device *dev, void *p)
  670. {
  671. const struct sockaddr *addr = p;
  672. if (!is_valid_ether_addr(addr->sa_data))
  673. return -EADDRNOTAVAIL;
  674. memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
  675. ethoc_do_set_mac_address(dev);
  676. return 0;
  677. }
  678. static void ethoc_set_multicast_list(struct net_device *dev)
  679. {
  680. struct ethoc *priv = netdev_priv(dev);
  681. u32 mode = ethoc_read(priv, MODER);
  682. struct netdev_hw_addr *ha;
  683. u32 hash[2] = { 0, 0 };
  684. /* set loopback mode if requested */
  685. if (dev->flags & IFF_LOOPBACK)
  686. mode |= MODER_LOOP;
  687. else
  688. mode &= ~MODER_LOOP;
  689. /* receive broadcast frames if requested */
  690. if (dev->flags & IFF_BROADCAST)
  691. mode &= ~MODER_BRO;
  692. else
  693. mode |= MODER_BRO;
  694. /* enable promiscuous mode if requested */
  695. if (dev->flags & IFF_PROMISC)
  696. mode |= MODER_PRO;
  697. else
  698. mode &= ~MODER_PRO;
  699. ethoc_write(priv, MODER, mode);
  700. /* receive multicast frames */
  701. if (dev->flags & IFF_ALLMULTI) {
  702. hash[0] = 0xffffffff;
  703. hash[1] = 0xffffffff;
  704. } else {
  705. netdev_for_each_mc_addr(ha, dev) {
  706. u32 crc = ether_crc(ETH_ALEN, ha->addr);
  707. int bit = (crc >> 26) & 0x3f;
  708. hash[bit >> 5] |= 1 << (bit & 0x1f);
  709. }
  710. }
  711. ethoc_write(priv, ETH_HASH0, hash[0]);
  712. ethoc_write(priv, ETH_HASH1, hash[1]);
  713. }
  714. static int ethoc_change_mtu(struct net_device *dev, int new_mtu)
  715. {
  716. return -ENOSYS;
  717. }
  718. static void ethoc_tx_timeout(struct net_device *dev)
  719. {
  720. struct ethoc *priv = netdev_priv(dev);
  721. u32 pending = ethoc_read(priv, INT_SOURCE);
  722. if (likely(pending))
  723. ethoc_interrupt(dev->irq, dev);
  724. }
  725. static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
  726. {
  727. struct ethoc *priv = netdev_priv(dev);
  728. struct ethoc_bd bd;
  729. unsigned int entry;
  730. void *dest;
  731. if (skb_put_padto(skb, ETHOC_ZLEN)) {
  732. dev->stats.tx_errors++;
  733. goto out_no_free;
  734. }
  735. if (unlikely(skb->len > ETHOC_BUFSIZ)) {
  736. dev->stats.tx_errors++;
  737. goto out;
  738. }
  739. entry = priv->cur_tx % priv->num_tx;
  740. spin_lock_irq(&priv->lock);
  741. priv->cur_tx++;
  742. ethoc_read_bd(priv, entry, &bd);
  743. if (unlikely(skb->len < ETHOC_ZLEN))
  744. bd.stat |= TX_BD_PAD;
  745. else
  746. bd.stat &= ~TX_BD_PAD;
  747. dest = priv->vma[entry];
  748. memcpy_toio(dest, skb->data, skb->len);
  749. bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
  750. bd.stat |= TX_BD_LEN(skb->len);
  751. ethoc_write_bd(priv, entry, &bd);
  752. bd.stat |= TX_BD_READY;
  753. ethoc_write_bd(priv, entry, &bd);
  754. if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) {
  755. dev_dbg(&dev->dev, "stopping queue\n");
  756. netif_stop_queue(dev);
  757. }
  758. spin_unlock_irq(&priv->lock);
  759. skb_tx_timestamp(skb);
  760. out:
  761. dev_kfree_skb(skb);
  762. out_no_free:
  763. return NETDEV_TX_OK;
  764. }
  765. static int ethoc_get_regs_len(struct net_device *netdev)
  766. {
  767. return ETH_END;
  768. }
  769. static void ethoc_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  770. void *p)
  771. {
  772. struct ethoc *priv = netdev_priv(dev);
  773. u32 *regs_buff = p;
  774. unsigned i;
  775. regs->version = 0;
  776. for (i = 0; i < ETH_END / sizeof(u32); ++i)
  777. regs_buff[i] = ethoc_read(priv, i * sizeof(u32));
  778. }
  779. static void ethoc_get_ringparam(struct net_device *dev,
  780. struct ethtool_ringparam *ring)
  781. {
  782. struct ethoc *priv = netdev_priv(dev);
  783. ring->rx_max_pending = priv->num_bd - 1;
  784. ring->rx_mini_max_pending = 0;
  785. ring->rx_jumbo_max_pending = 0;
  786. ring->tx_max_pending = priv->num_bd - 1;
  787. ring->rx_pending = priv->num_rx;
  788. ring->rx_mini_pending = 0;
  789. ring->rx_jumbo_pending = 0;
  790. ring->tx_pending = priv->num_tx;
  791. }
  792. static int ethoc_set_ringparam(struct net_device *dev,
  793. struct ethtool_ringparam *ring)
  794. {
  795. struct ethoc *priv = netdev_priv(dev);
  796. if (ring->tx_pending < 1 || ring->rx_pending < 1 ||
  797. ring->tx_pending + ring->rx_pending > priv->num_bd)
  798. return -EINVAL;
  799. if (ring->rx_mini_pending || ring->rx_jumbo_pending)
  800. return -EINVAL;
  801. if (netif_running(dev)) {
  802. netif_tx_disable(dev);
  803. ethoc_disable_rx_and_tx(priv);
  804. ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX);
  805. synchronize_irq(dev->irq);
  806. }
  807. priv->num_tx = rounddown_pow_of_two(ring->tx_pending);
  808. priv->num_rx = ring->rx_pending;
  809. ethoc_init_ring(priv, dev->mem_start);
  810. if (netif_running(dev)) {
  811. ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX);
  812. ethoc_enable_rx_and_tx(priv);
  813. netif_wake_queue(dev);
  814. }
  815. return 0;
  816. }
  817. static const struct ethtool_ops ethoc_ethtool_ops = {
  818. .get_regs_len = ethoc_get_regs_len,
  819. .get_regs = ethoc_get_regs,
  820. .nway_reset = phy_ethtool_nway_reset,
  821. .get_link = ethtool_op_get_link,
  822. .get_ringparam = ethoc_get_ringparam,
  823. .set_ringparam = ethoc_set_ringparam,
  824. .get_ts_info = ethtool_op_get_ts_info,
  825. .get_link_ksettings = phy_ethtool_get_link_ksettings,
  826. .set_link_ksettings = phy_ethtool_set_link_ksettings,
  827. };
  828. static const struct net_device_ops ethoc_netdev_ops = {
  829. .ndo_open = ethoc_open,
  830. .ndo_stop = ethoc_stop,
  831. .ndo_do_ioctl = ethoc_ioctl,
  832. .ndo_set_mac_address = ethoc_set_mac_address,
  833. .ndo_set_rx_mode = ethoc_set_multicast_list,
  834. .ndo_change_mtu = ethoc_change_mtu,
  835. .ndo_tx_timeout = ethoc_tx_timeout,
  836. .ndo_start_xmit = ethoc_start_xmit,
  837. };
  838. /**
  839. * ethoc_probe - initialize OpenCores ethernet MAC
  840. * pdev: platform device
  841. */
  842. static int ethoc_probe(struct platform_device *pdev)
  843. {
  844. struct net_device *netdev = NULL;
  845. struct resource *res = NULL;
  846. struct resource *mmio = NULL;
  847. struct resource *mem = NULL;
  848. struct ethoc *priv = NULL;
  849. int num_bd;
  850. int ret = 0;
  851. struct ethoc_platform_data *pdata = dev_get_platdata(&pdev->dev);
  852. u32 eth_clkfreq = pdata ? pdata->eth_clkfreq : 0;
  853. /* allocate networking device */
  854. netdev = alloc_etherdev(sizeof(struct ethoc));
  855. if (!netdev) {
  856. ret = -ENOMEM;
  857. goto out;
  858. }
  859. SET_NETDEV_DEV(netdev, &pdev->dev);
  860. platform_set_drvdata(pdev, netdev);
  861. /* obtain I/O memory space */
  862. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  863. if (!res) {
  864. dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
  865. ret = -ENXIO;
  866. goto free;
  867. }
  868. mmio = devm_request_mem_region(&pdev->dev, res->start,
  869. resource_size(res), res->name);
  870. if (!mmio) {
  871. dev_err(&pdev->dev, "cannot request I/O memory space\n");
  872. ret = -ENXIO;
  873. goto free;
  874. }
  875. netdev->base_addr = mmio->start;
  876. /* obtain buffer memory space */
  877. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  878. if (res) {
  879. mem = devm_request_mem_region(&pdev->dev, res->start,
  880. resource_size(res), res->name);
  881. if (!mem) {
  882. dev_err(&pdev->dev, "cannot request memory space\n");
  883. ret = -ENXIO;
  884. goto free;
  885. }
  886. netdev->mem_start = mem->start;
  887. netdev->mem_end = mem->end;
  888. }
  889. /* obtain device IRQ number */
  890. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  891. if (!res) {
  892. dev_err(&pdev->dev, "cannot obtain IRQ\n");
  893. ret = -ENXIO;
  894. goto free;
  895. }
  896. netdev->irq = res->start;
  897. /* setup driver-private data */
  898. priv = netdev_priv(netdev);
  899. priv->netdev = netdev;
  900. priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
  901. resource_size(mmio));
  902. if (!priv->iobase) {
  903. dev_err(&pdev->dev, "cannot remap I/O memory space\n");
  904. ret = -ENXIO;
  905. goto free;
  906. }
  907. if (netdev->mem_end) {
  908. priv->membase = devm_ioremap_nocache(&pdev->dev,
  909. netdev->mem_start, resource_size(mem));
  910. if (!priv->membase) {
  911. dev_err(&pdev->dev, "cannot remap memory space\n");
  912. ret = -ENXIO;
  913. goto free;
  914. }
  915. } else {
  916. /* Allocate buffer memory */
  917. priv->membase = dmam_alloc_coherent(&pdev->dev,
  918. buffer_size, (void *)&netdev->mem_start,
  919. GFP_KERNEL);
  920. if (!priv->membase) {
  921. dev_err(&pdev->dev, "cannot allocate %dB buffer\n",
  922. buffer_size);
  923. ret = -ENOMEM;
  924. goto free;
  925. }
  926. netdev->mem_end = netdev->mem_start + buffer_size;
  927. }
  928. priv->big_endian = pdata ? pdata->big_endian :
  929. of_device_is_big_endian(pdev->dev.of_node);
  930. /* calculate the number of TX/RX buffers, maximum 128 supported */
  931. num_bd = min_t(unsigned int,
  932. 128, (netdev->mem_end - netdev->mem_start + 1) / ETHOC_BUFSIZ);
  933. if (num_bd < 4) {
  934. ret = -ENODEV;
  935. goto free;
  936. }
  937. priv->num_bd = num_bd;
  938. /* num_tx must be a power of two */
  939. priv->num_tx = rounddown_pow_of_two(num_bd >> 1);
  940. priv->num_rx = num_bd - priv->num_tx;
  941. dev_dbg(&pdev->dev, "ethoc: num_tx: %d num_rx: %d\n",
  942. priv->num_tx, priv->num_rx);
  943. priv->vma = devm_kcalloc(&pdev->dev, num_bd, sizeof(void *),
  944. GFP_KERNEL);
  945. if (!priv->vma) {
  946. ret = -ENOMEM;
  947. goto free;
  948. }
  949. /* Allow the platform setup code to pass in a MAC address. */
  950. if (pdata) {
  951. ether_addr_copy(netdev->dev_addr, pdata->hwaddr);
  952. priv->phy_id = pdata->phy_id;
  953. } else {
  954. const void *mac;
  955. mac = of_get_mac_address(pdev->dev.of_node);
  956. if (mac)
  957. ether_addr_copy(netdev->dev_addr, mac);
  958. priv->phy_id = -1;
  959. }
  960. /* Check that the given MAC address is valid. If it isn't, read the
  961. * current MAC from the controller.
  962. */
  963. if (!is_valid_ether_addr(netdev->dev_addr))
  964. ethoc_get_mac_address(netdev, netdev->dev_addr);
  965. /* Check the MAC again for validity, if it still isn't choose and
  966. * program a random one.
  967. */
  968. if (!is_valid_ether_addr(netdev->dev_addr))
  969. eth_hw_addr_random(netdev);
  970. ethoc_do_set_mac_address(netdev);
  971. /* Allow the platform setup code to adjust MII management bus clock. */
  972. if (!eth_clkfreq) {
  973. struct clk *clk = devm_clk_get(&pdev->dev, NULL);
  974. if (!IS_ERR(clk)) {
  975. priv->clk = clk;
  976. clk_prepare_enable(clk);
  977. eth_clkfreq = clk_get_rate(clk);
  978. }
  979. }
  980. if (eth_clkfreq) {
  981. u32 clkdiv = MIIMODER_CLKDIV(eth_clkfreq / 2500000 + 1);
  982. if (!clkdiv)
  983. clkdiv = 2;
  984. dev_dbg(&pdev->dev, "setting MII clkdiv to %u\n", clkdiv);
  985. ethoc_write(priv, MIIMODER,
  986. (ethoc_read(priv, MIIMODER) & MIIMODER_NOPRE) |
  987. clkdiv);
  988. }
  989. /* register MII bus */
  990. priv->mdio = mdiobus_alloc();
  991. if (!priv->mdio) {
  992. ret = -ENOMEM;
  993. goto free2;
  994. }
  995. priv->mdio->name = "ethoc-mdio";
  996. snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
  997. priv->mdio->name, pdev->id);
  998. priv->mdio->read = ethoc_mdio_read;
  999. priv->mdio->write = ethoc_mdio_write;
  1000. priv->mdio->priv = priv;
  1001. ret = mdiobus_register(priv->mdio);
  1002. if (ret) {
  1003. dev_err(&netdev->dev, "failed to register MDIO bus\n");
  1004. goto free2;
  1005. }
  1006. ret = ethoc_mdio_probe(netdev);
  1007. if (ret) {
  1008. dev_err(&netdev->dev, "failed to probe MDIO bus\n");
  1009. goto error;
  1010. }
  1011. /* setup the net_device structure */
  1012. netdev->netdev_ops = &ethoc_netdev_ops;
  1013. netdev->watchdog_timeo = ETHOC_TIMEOUT;
  1014. netdev->features |= 0;
  1015. netdev->ethtool_ops = &ethoc_ethtool_ops;
  1016. /* setup NAPI */
  1017. netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);
  1018. spin_lock_init(&priv->lock);
  1019. ret = register_netdev(netdev);
  1020. if (ret < 0) {
  1021. dev_err(&netdev->dev, "failed to register interface\n");
  1022. goto error2;
  1023. }
  1024. goto out;
  1025. error2:
  1026. netif_napi_del(&priv->napi);
  1027. error:
  1028. mdiobus_unregister(priv->mdio);
  1029. mdiobus_free(priv->mdio);
  1030. free2:
  1031. clk_disable_unprepare(priv->clk);
  1032. free:
  1033. free_netdev(netdev);
  1034. out:
  1035. return ret;
  1036. }
  1037. /**
  1038. * ethoc_remove - shutdown OpenCores ethernet MAC
  1039. * @pdev: platform device
  1040. */
  1041. static int ethoc_remove(struct platform_device *pdev)
  1042. {
  1043. struct net_device *netdev = platform_get_drvdata(pdev);
  1044. struct ethoc *priv = netdev_priv(netdev);
  1045. if (netdev) {
  1046. netif_napi_del(&priv->napi);
  1047. phy_disconnect(netdev->phydev);
  1048. if (priv->mdio) {
  1049. mdiobus_unregister(priv->mdio);
  1050. mdiobus_free(priv->mdio);
  1051. }
  1052. clk_disable_unprepare(priv->clk);
  1053. unregister_netdev(netdev);
  1054. free_netdev(netdev);
  1055. }
  1056. return 0;
  1057. }
  1058. #ifdef CONFIG_PM
  1059. static int ethoc_suspend(struct platform_device *pdev, pm_message_t state)
  1060. {
  1061. return -ENOSYS;
  1062. }
  1063. static int ethoc_resume(struct platform_device *pdev)
  1064. {
  1065. return -ENOSYS;
  1066. }
  1067. #else
  1068. # define ethoc_suspend NULL
  1069. # define ethoc_resume NULL
  1070. #endif
  1071. static const struct of_device_id ethoc_match[] = {
  1072. { .compatible = "opencores,ethoc", },
  1073. {},
  1074. };
  1075. MODULE_DEVICE_TABLE(of, ethoc_match);
  1076. static struct platform_driver ethoc_driver = {
  1077. .probe = ethoc_probe,
  1078. .remove = ethoc_remove,
  1079. .suspend = ethoc_suspend,
  1080. .resume = ethoc_resume,
  1081. .driver = {
  1082. .name = "ethoc",
  1083. .of_match_table = ethoc_match,
  1084. },
  1085. };
  1086. module_platform_driver(ethoc_driver);
  1087. MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
  1088. MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
  1089. MODULE_LICENSE("GPL v2");