ep93xx_eth.c 20 KB

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  1. /*
  2. * EP93xx ethernet network device driver
  3. * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
  4. * Dedicated to Marija Kulikova.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. */
  11. #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
  12. #include <linux/dma-mapping.h>
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/netdevice.h>
  16. #include <linux/mii.h>
  17. #include <linux/etherdevice.h>
  18. #include <linux/ethtool.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/moduleparam.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/delay.h>
  23. #include <linux/io.h>
  24. #include <linux/slab.h>
  25. #include <mach/hardware.h>
  26. #define DRV_MODULE_NAME "ep93xx-eth"
  27. #define DRV_MODULE_VERSION "0.1"
  28. #define RX_QUEUE_ENTRIES 64
  29. #define TX_QUEUE_ENTRIES 8
  30. #define MAX_PKT_SIZE 2044
  31. #define PKT_BUF_SIZE 2048
  32. #define REG_RXCTL 0x0000
  33. #define REG_RXCTL_DEFAULT 0x00073800
  34. #define REG_TXCTL 0x0004
  35. #define REG_TXCTL_ENABLE 0x00000001
  36. #define REG_MIICMD 0x0010
  37. #define REG_MIICMD_READ 0x00008000
  38. #define REG_MIICMD_WRITE 0x00004000
  39. #define REG_MIIDATA 0x0014
  40. #define REG_MIISTS 0x0018
  41. #define REG_MIISTS_BUSY 0x00000001
  42. #define REG_SELFCTL 0x0020
  43. #define REG_SELFCTL_RESET 0x00000001
  44. #define REG_INTEN 0x0024
  45. #define REG_INTEN_TX 0x00000008
  46. #define REG_INTEN_RX 0x00000007
  47. #define REG_INTSTSP 0x0028
  48. #define REG_INTSTS_TX 0x00000008
  49. #define REG_INTSTS_RX 0x00000004
  50. #define REG_INTSTSC 0x002c
  51. #define REG_AFP 0x004c
  52. #define REG_INDAD0 0x0050
  53. #define REG_INDAD1 0x0051
  54. #define REG_INDAD2 0x0052
  55. #define REG_INDAD3 0x0053
  56. #define REG_INDAD4 0x0054
  57. #define REG_INDAD5 0x0055
  58. #define REG_GIINTMSK 0x0064
  59. #define REG_GIINTMSK_ENABLE 0x00008000
  60. #define REG_BMCTL 0x0080
  61. #define REG_BMCTL_ENABLE_TX 0x00000100
  62. #define REG_BMCTL_ENABLE_RX 0x00000001
  63. #define REG_BMSTS 0x0084
  64. #define REG_BMSTS_RX_ACTIVE 0x00000008
  65. #define REG_RXDQBADD 0x0090
  66. #define REG_RXDQBLEN 0x0094
  67. #define REG_RXDCURADD 0x0098
  68. #define REG_RXDENQ 0x009c
  69. #define REG_RXSTSQBADD 0x00a0
  70. #define REG_RXSTSQBLEN 0x00a4
  71. #define REG_RXSTSQCURADD 0x00a8
  72. #define REG_RXSTSENQ 0x00ac
  73. #define REG_TXDQBADD 0x00b0
  74. #define REG_TXDQBLEN 0x00b4
  75. #define REG_TXDQCURADD 0x00b8
  76. #define REG_TXDENQ 0x00bc
  77. #define REG_TXSTSQBADD 0x00c0
  78. #define REG_TXSTSQBLEN 0x00c4
  79. #define REG_TXSTSQCURADD 0x00c8
  80. #define REG_MAXFRMLEN 0x00e8
  81. struct ep93xx_rdesc
  82. {
  83. u32 buf_addr;
  84. u32 rdesc1;
  85. };
  86. #define RDESC1_NSOF 0x80000000
  87. #define RDESC1_BUFFER_INDEX 0x7fff0000
  88. #define RDESC1_BUFFER_LENGTH 0x0000ffff
  89. struct ep93xx_rstat
  90. {
  91. u32 rstat0;
  92. u32 rstat1;
  93. };
  94. #define RSTAT0_RFP 0x80000000
  95. #define RSTAT0_RWE 0x40000000
  96. #define RSTAT0_EOF 0x20000000
  97. #define RSTAT0_EOB 0x10000000
  98. #define RSTAT0_AM 0x00c00000
  99. #define RSTAT0_RX_ERR 0x00200000
  100. #define RSTAT0_OE 0x00100000
  101. #define RSTAT0_FE 0x00080000
  102. #define RSTAT0_RUNT 0x00040000
  103. #define RSTAT0_EDATA 0x00020000
  104. #define RSTAT0_CRCE 0x00010000
  105. #define RSTAT0_CRCI 0x00008000
  106. #define RSTAT0_HTI 0x00003f00
  107. #define RSTAT1_RFP 0x80000000
  108. #define RSTAT1_BUFFER_INDEX 0x7fff0000
  109. #define RSTAT1_FRAME_LENGTH 0x0000ffff
  110. struct ep93xx_tdesc
  111. {
  112. u32 buf_addr;
  113. u32 tdesc1;
  114. };
  115. #define TDESC1_EOF 0x80000000
  116. #define TDESC1_BUFFER_INDEX 0x7fff0000
  117. #define TDESC1_BUFFER_ABORT 0x00008000
  118. #define TDESC1_BUFFER_LENGTH 0x00000fff
  119. struct ep93xx_tstat
  120. {
  121. u32 tstat0;
  122. };
  123. #define TSTAT0_TXFP 0x80000000
  124. #define TSTAT0_TXWE 0x40000000
  125. #define TSTAT0_FA 0x20000000
  126. #define TSTAT0_LCRS 0x10000000
  127. #define TSTAT0_OW 0x04000000
  128. #define TSTAT0_TXU 0x02000000
  129. #define TSTAT0_ECOLL 0x01000000
  130. #define TSTAT0_NCOLL 0x001f0000
  131. #define TSTAT0_BUFFER_INDEX 0x00007fff
  132. struct ep93xx_descs
  133. {
  134. struct ep93xx_rdesc rdesc[RX_QUEUE_ENTRIES];
  135. struct ep93xx_tdesc tdesc[TX_QUEUE_ENTRIES];
  136. struct ep93xx_rstat rstat[RX_QUEUE_ENTRIES];
  137. struct ep93xx_tstat tstat[TX_QUEUE_ENTRIES];
  138. };
  139. struct ep93xx_priv
  140. {
  141. struct resource *res;
  142. void __iomem *base_addr;
  143. int irq;
  144. struct ep93xx_descs *descs;
  145. dma_addr_t descs_dma_addr;
  146. void *rx_buf[RX_QUEUE_ENTRIES];
  147. void *tx_buf[TX_QUEUE_ENTRIES];
  148. spinlock_t rx_lock;
  149. unsigned int rx_pointer;
  150. unsigned int tx_clean_pointer;
  151. unsigned int tx_pointer;
  152. spinlock_t tx_pending_lock;
  153. unsigned int tx_pending;
  154. struct net_device *dev;
  155. struct napi_struct napi;
  156. struct mii_if_info mii;
  157. u8 mdc_divisor;
  158. };
  159. #define rdb(ep, off) __raw_readb((ep)->base_addr + (off))
  160. #define rdw(ep, off) __raw_readw((ep)->base_addr + (off))
  161. #define rdl(ep, off) __raw_readl((ep)->base_addr + (off))
  162. #define wrb(ep, off, val) __raw_writeb((val), (ep)->base_addr + (off))
  163. #define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off))
  164. #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off))
  165. static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg)
  166. {
  167. struct ep93xx_priv *ep = netdev_priv(dev);
  168. int data;
  169. int i;
  170. wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg);
  171. for (i = 0; i < 10; i++) {
  172. if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
  173. break;
  174. msleep(1);
  175. }
  176. if (i == 10) {
  177. pr_info("mdio read timed out\n");
  178. data = 0xffff;
  179. } else {
  180. data = rdl(ep, REG_MIIDATA);
  181. }
  182. return data;
  183. }
  184. static void ep93xx_mdio_write(struct net_device *dev, int phy_id, int reg, int data)
  185. {
  186. struct ep93xx_priv *ep = netdev_priv(dev);
  187. int i;
  188. wrl(ep, REG_MIIDATA, data);
  189. wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg);
  190. for (i = 0; i < 10; i++) {
  191. if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
  192. break;
  193. msleep(1);
  194. }
  195. if (i == 10)
  196. pr_info("mdio write timed out\n");
  197. }
  198. static int ep93xx_rx(struct net_device *dev, int budget)
  199. {
  200. struct ep93xx_priv *ep = netdev_priv(dev);
  201. int processed = 0;
  202. while (processed < budget) {
  203. int entry;
  204. struct ep93xx_rstat *rstat;
  205. u32 rstat0;
  206. u32 rstat1;
  207. int length;
  208. struct sk_buff *skb;
  209. entry = ep->rx_pointer;
  210. rstat = ep->descs->rstat + entry;
  211. rstat0 = rstat->rstat0;
  212. rstat1 = rstat->rstat1;
  213. if (!(rstat0 & RSTAT0_RFP) || !(rstat1 & RSTAT1_RFP))
  214. break;
  215. rstat->rstat0 = 0;
  216. rstat->rstat1 = 0;
  217. if (!(rstat0 & RSTAT0_EOF))
  218. pr_crit("not end-of-frame %.8x %.8x\n", rstat0, rstat1);
  219. if (!(rstat0 & RSTAT0_EOB))
  220. pr_crit("not end-of-buffer %.8x %.8x\n", rstat0, rstat1);
  221. if ((rstat1 & RSTAT1_BUFFER_INDEX) >> 16 != entry)
  222. pr_crit("entry mismatch %.8x %.8x\n", rstat0, rstat1);
  223. if (!(rstat0 & RSTAT0_RWE)) {
  224. dev->stats.rx_errors++;
  225. if (rstat0 & RSTAT0_OE)
  226. dev->stats.rx_fifo_errors++;
  227. if (rstat0 & RSTAT0_FE)
  228. dev->stats.rx_frame_errors++;
  229. if (rstat0 & (RSTAT0_RUNT | RSTAT0_EDATA))
  230. dev->stats.rx_length_errors++;
  231. if (rstat0 & RSTAT0_CRCE)
  232. dev->stats.rx_crc_errors++;
  233. goto err;
  234. }
  235. length = rstat1 & RSTAT1_FRAME_LENGTH;
  236. if (length > MAX_PKT_SIZE) {
  237. pr_notice("invalid length %.8x %.8x\n", rstat0, rstat1);
  238. goto err;
  239. }
  240. /* Strip FCS. */
  241. if (rstat0 & RSTAT0_CRCI)
  242. length -= 4;
  243. skb = netdev_alloc_skb(dev, length + 2);
  244. if (likely(skb != NULL)) {
  245. struct ep93xx_rdesc *rxd = &ep->descs->rdesc[entry];
  246. skb_reserve(skb, 2);
  247. dma_sync_single_for_cpu(dev->dev.parent, rxd->buf_addr,
  248. length, DMA_FROM_DEVICE);
  249. skb_copy_to_linear_data(skb, ep->rx_buf[entry], length);
  250. dma_sync_single_for_device(dev->dev.parent,
  251. rxd->buf_addr, length,
  252. DMA_FROM_DEVICE);
  253. skb_put(skb, length);
  254. skb->protocol = eth_type_trans(skb, dev);
  255. napi_gro_receive(&ep->napi, skb);
  256. dev->stats.rx_packets++;
  257. dev->stats.rx_bytes += length;
  258. } else {
  259. dev->stats.rx_dropped++;
  260. }
  261. err:
  262. ep->rx_pointer = (entry + 1) & (RX_QUEUE_ENTRIES - 1);
  263. processed++;
  264. }
  265. return processed;
  266. }
  267. static int ep93xx_poll(struct napi_struct *napi, int budget)
  268. {
  269. struct ep93xx_priv *ep = container_of(napi, struct ep93xx_priv, napi);
  270. struct net_device *dev = ep->dev;
  271. int rx;
  272. rx = ep93xx_rx(dev, budget);
  273. if (rx < budget && napi_complete_done(napi, rx)) {
  274. spin_lock_irq(&ep->rx_lock);
  275. wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
  276. spin_unlock_irq(&ep->rx_lock);
  277. }
  278. if (rx) {
  279. wrw(ep, REG_RXDENQ, rx);
  280. wrw(ep, REG_RXSTSENQ, rx);
  281. }
  282. return rx;
  283. }
  284. static netdev_tx_t ep93xx_xmit(struct sk_buff *skb, struct net_device *dev)
  285. {
  286. struct ep93xx_priv *ep = netdev_priv(dev);
  287. struct ep93xx_tdesc *txd;
  288. int entry;
  289. if (unlikely(skb->len > MAX_PKT_SIZE)) {
  290. dev->stats.tx_dropped++;
  291. dev_kfree_skb(skb);
  292. return NETDEV_TX_OK;
  293. }
  294. entry = ep->tx_pointer;
  295. ep->tx_pointer = (ep->tx_pointer + 1) & (TX_QUEUE_ENTRIES - 1);
  296. txd = &ep->descs->tdesc[entry];
  297. txd->tdesc1 = TDESC1_EOF | (entry << 16) | (skb->len & 0xfff);
  298. dma_sync_single_for_cpu(dev->dev.parent, txd->buf_addr, skb->len,
  299. DMA_TO_DEVICE);
  300. skb_copy_and_csum_dev(skb, ep->tx_buf[entry]);
  301. dma_sync_single_for_device(dev->dev.parent, txd->buf_addr, skb->len,
  302. DMA_TO_DEVICE);
  303. dev_kfree_skb(skb);
  304. spin_lock_irq(&ep->tx_pending_lock);
  305. ep->tx_pending++;
  306. if (ep->tx_pending == TX_QUEUE_ENTRIES)
  307. netif_stop_queue(dev);
  308. spin_unlock_irq(&ep->tx_pending_lock);
  309. wrl(ep, REG_TXDENQ, 1);
  310. return NETDEV_TX_OK;
  311. }
  312. static void ep93xx_tx_complete(struct net_device *dev)
  313. {
  314. struct ep93xx_priv *ep = netdev_priv(dev);
  315. int wake;
  316. wake = 0;
  317. spin_lock(&ep->tx_pending_lock);
  318. while (1) {
  319. int entry;
  320. struct ep93xx_tstat *tstat;
  321. u32 tstat0;
  322. entry = ep->tx_clean_pointer;
  323. tstat = ep->descs->tstat + entry;
  324. tstat0 = tstat->tstat0;
  325. if (!(tstat0 & TSTAT0_TXFP))
  326. break;
  327. tstat->tstat0 = 0;
  328. if (tstat0 & TSTAT0_FA)
  329. pr_crit("frame aborted %.8x\n", tstat0);
  330. if ((tstat0 & TSTAT0_BUFFER_INDEX) != entry)
  331. pr_crit("entry mismatch %.8x\n", tstat0);
  332. if (tstat0 & TSTAT0_TXWE) {
  333. int length = ep->descs->tdesc[entry].tdesc1 & 0xfff;
  334. dev->stats.tx_packets++;
  335. dev->stats.tx_bytes += length;
  336. } else {
  337. dev->stats.tx_errors++;
  338. }
  339. if (tstat0 & TSTAT0_OW)
  340. dev->stats.tx_window_errors++;
  341. if (tstat0 & TSTAT0_TXU)
  342. dev->stats.tx_fifo_errors++;
  343. dev->stats.collisions += (tstat0 >> 16) & 0x1f;
  344. ep->tx_clean_pointer = (entry + 1) & (TX_QUEUE_ENTRIES - 1);
  345. if (ep->tx_pending == TX_QUEUE_ENTRIES)
  346. wake = 1;
  347. ep->tx_pending--;
  348. }
  349. spin_unlock(&ep->tx_pending_lock);
  350. if (wake)
  351. netif_wake_queue(dev);
  352. }
  353. static irqreturn_t ep93xx_irq(int irq, void *dev_id)
  354. {
  355. struct net_device *dev = dev_id;
  356. struct ep93xx_priv *ep = netdev_priv(dev);
  357. u32 status;
  358. status = rdl(ep, REG_INTSTSC);
  359. if (status == 0)
  360. return IRQ_NONE;
  361. if (status & REG_INTSTS_RX) {
  362. spin_lock(&ep->rx_lock);
  363. if (likely(napi_schedule_prep(&ep->napi))) {
  364. wrl(ep, REG_INTEN, REG_INTEN_TX);
  365. __napi_schedule(&ep->napi);
  366. }
  367. spin_unlock(&ep->rx_lock);
  368. }
  369. if (status & REG_INTSTS_TX)
  370. ep93xx_tx_complete(dev);
  371. return IRQ_HANDLED;
  372. }
  373. static void ep93xx_free_buffers(struct ep93xx_priv *ep)
  374. {
  375. struct device *dev = ep->dev->dev.parent;
  376. int i;
  377. if (!ep->descs)
  378. return;
  379. for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
  380. dma_addr_t d;
  381. d = ep->descs->rdesc[i].buf_addr;
  382. if (d)
  383. dma_unmap_single(dev, d, PKT_BUF_SIZE, DMA_FROM_DEVICE);
  384. kfree(ep->rx_buf[i]);
  385. }
  386. for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
  387. dma_addr_t d;
  388. d = ep->descs->tdesc[i].buf_addr;
  389. if (d)
  390. dma_unmap_single(dev, d, PKT_BUF_SIZE, DMA_TO_DEVICE);
  391. kfree(ep->tx_buf[i]);
  392. }
  393. dma_free_coherent(dev, sizeof(struct ep93xx_descs), ep->descs,
  394. ep->descs_dma_addr);
  395. ep->descs = NULL;
  396. }
  397. static int ep93xx_alloc_buffers(struct ep93xx_priv *ep)
  398. {
  399. struct device *dev = ep->dev->dev.parent;
  400. int i;
  401. ep->descs = dma_alloc_coherent(dev, sizeof(struct ep93xx_descs),
  402. &ep->descs_dma_addr, GFP_KERNEL);
  403. if (ep->descs == NULL)
  404. return 1;
  405. for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
  406. void *buf;
  407. dma_addr_t d;
  408. buf = kmalloc(PKT_BUF_SIZE, GFP_KERNEL);
  409. if (buf == NULL)
  410. goto err;
  411. d = dma_map_single(dev, buf, PKT_BUF_SIZE, DMA_FROM_DEVICE);
  412. if (dma_mapping_error(dev, d)) {
  413. kfree(buf);
  414. goto err;
  415. }
  416. ep->rx_buf[i] = buf;
  417. ep->descs->rdesc[i].buf_addr = d;
  418. ep->descs->rdesc[i].rdesc1 = (i << 16) | PKT_BUF_SIZE;
  419. }
  420. for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
  421. void *buf;
  422. dma_addr_t d;
  423. buf = kmalloc(PKT_BUF_SIZE, GFP_KERNEL);
  424. if (buf == NULL)
  425. goto err;
  426. d = dma_map_single(dev, buf, PKT_BUF_SIZE, DMA_TO_DEVICE);
  427. if (dma_mapping_error(dev, d)) {
  428. kfree(buf);
  429. goto err;
  430. }
  431. ep->tx_buf[i] = buf;
  432. ep->descs->tdesc[i].buf_addr = d;
  433. }
  434. return 0;
  435. err:
  436. ep93xx_free_buffers(ep);
  437. return 1;
  438. }
  439. static int ep93xx_start_hw(struct net_device *dev)
  440. {
  441. struct ep93xx_priv *ep = netdev_priv(dev);
  442. unsigned long addr;
  443. int i;
  444. wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
  445. for (i = 0; i < 10; i++) {
  446. if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
  447. break;
  448. msleep(1);
  449. }
  450. if (i == 10) {
  451. pr_crit("hw failed to reset\n");
  452. return 1;
  453. }
  454. wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9));
  455. /* Does the PHY support preamble suppress? */
  456. if ((ep93xx_mdio_read(dev, ep->mii.phy_id, MII_BMSR) & 0x0040) != 0)
  457. wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8));
  458. /* Receive descriptor ring. */
  459. addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rdesc);
  460. wrl(ep, REG_RXDQBADD, addr);
  461. wrl(ep, REG_RXDCURADD, addr);
  462. wrw(ep, REG_RXDQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rdesc));
  463. /* Receive status ring. */
  464. addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rstat);
  465. wrl(ep, REG_RXSTSQBADD, addr);
  466. wrl(ep, REG_RXSTSQCURADD, addr);
  467. wrw(ep, REG_RXSTSQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rstat));
  468. /* Transmit descriptor ring. */
  469. addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tdesc);
  470. wrl(ep, REG_TXDQBADD, addr);
  471. wrl(ep, REG_TXDQCURADD, addr);
  472. wrw(ep, REG_TXDQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tdesc));
  473. /* Transmit status ring. */
  474. addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tstat);
  475. wrl(ep, REG_TXSTSQBADD, addr);
  476. wrl(ep, REG_TXSTSQCURADD, addr);
  477. wrw(ep, REG_TXSTSQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tstat));
  478. wrl(ep, REG_BMCTL, REG_BMCTL_ENABLE_TX | REG_BMCTL_ENABLE_RX);
  479. wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
  480. wrl(ep, REG_GIINTMSK, 0);
  481. for (i = 0; i < 10; i++) {
  482. if ((rdl(ep, REG_BMSTS) & REG_BMSTS_RX_ACTIVE) != 0)
  483. break;
  484. msleep(1);
  485. }
  486. if (i == 10) {
  487. pr_crit("hw failed to start\n");
  488. return 1;
  489. }
  490. wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);
  491. wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);
  492. wrb(ep, REG_INDAD0, dev->dev_addr[0]);
  493. wrb(ep, REG_INDAD1, dev->dev_addr[1]);
  494. wrb(ep, REG_INDAD2, dev->dev_addr[2]);
  495. wrb(ep, REG_INDAD3, dev->dev_addr[3]);
  496. wrb(ep, REG_INDAD4, dev->dev_addr[4]);
  497. wrb(ep, REG_INDAD5, dev->dev_addr[5]);
  498. wrl(ep, REG_AFP, 0);
  499. wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);
  500. wrl(ep, REG_RXCTL, REG_RXCTL_DEFAULT);
  501. wrl(ep, REG_TXCTL, REG_TXCTL_ENABLE);
  502. return 0;
  503. }
  504. static void ep93xx_stop_hw(struct net_device *dev)
  505. {
  506. struct ep93xx_priv *ep = netdev_priv(dev);
  507. int i;
  508. wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
  509. for (i = 0; i < 10; i++) {
  510. if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
  511. break;
  512. msleep(1);
  513. }
  514. if (i == 10)
  515. pr_crit("hw failed to reset\n");
  516. }
  517. static int ep93xx_open(struct net_device *dev)
  518. {
  519. struct ep93xx_priv *ep = netdev_priv(dev);
  520. int err;
  521. if (ep93xx_alloc_buffers(ep))
  522. return -ENOMEM;
  523. napi_enable(&ep->napi);
  524. if (ep93xx_start_hw(dev)) {
  525. napi_disable(&ep->napi);
  526. ep93xx_free_buffers(ep);
  527. return -EIO;
  528. }
  529. spin_lock_init(&ep->rx_lock);
  530. ep->rx_pointer = 0;
  531. ep->tx_clean_pointer = 0;
  532. ep->tx_pointer = 0;
  533. spin_lock_init(&ep->tx_pending_lock);
  534. ep->tx_pending = 0;
  535. err = request_irq(ep->irq, ep93xx_irq, IRQF_SHARED, dev->name, dev);
  536. if (err) {
  537. napi_disable(&ep->napi);
  538. ep93xx_stop_hw(dev);
  539. ep93xx_free_buffers(ep);
  540. return err;
  541. }
  542. wrl(ep, REG_GIINTMSK, REG_GIINTMSK_ENABLE);
  543. netif_start_queue(dev);
  544. return 0;
  545. }
  546. static int ep93xx_close(struct net_device *dev)
  547. {
  548. struct ep93xx_priv *ep = netdev_priv(dev);
  549. napi_disable(&ep->napi);
  550. netif_stop_queue(dev);
  551. wrl(ep, REG_GIINTMSK, 0);
  552. free_irq(ep->irq, dev);
  553. ep93xx_stop_hw(dev);
  554. ep93xx_free_buffers(ep);
  555. return 0;
  556. }
  557. static int ep93xx_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  558. {
  559. struct ep93xx_priv *ep = netdev_priv(dev);
  560. struct mii_ioctl_data *data = if_mii(ifr);
  561. return generic_mii_ioctl(&ep->mii, data, cmd, NULL);
  562. }
  563. static void ep93xx_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  564. {
  565. strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
  566. strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
  567. }
  568. static int ep93xx_get_link_ksettings(struct net_device *dev,
  569. struct ethtool_link_ksettings *cmd)
  570. {
  571. struct ep93xx_priv *ep = netdev_priv(dev);
  572. mii_ethtool_get_link_ksettings(&ep->mii, cmd);
  573. return 0;
  574. }
  575. static int ep93xx_set_link_ksettings(struct net_device *dev,
  576. const struct ethtool_link_ksettings *cmd)
  577. {
  578. struct ep93xx_priv *ep = netdev_priv(dev);
  579. return mii_ethtool_set_link_ksettings(&ep->mii, cmd);
  580. }
  581. static int ep93xx_nway_reset(struct net_device *dev)
  582. {
  583. struct ep93xx_priv *ep = netdev_priv(dev);
  584. return mii_nway_restart(&ep->mii);
  585. }
  586. static u32 ep93xx_get_link(struct net_device *dev)
  587. {
  588. struct ep93xx_priv *ep = netdev_priv(dev);
  589. return mii_link_ok(&ep->mii);
  590. }
  591. static const struct ethtool_ops ep93xx_ethtool_ops = {
  592. .get_drvinfo = ep93xx_get_drvinfo,
  593. .nway_reset = ep93xx_nway_reset,
  594. .get_link = ep93xx_get_link,
  595. .get_link_ksettings = ep93xx_get_link_ksettings,
  596. .set_link_ksettings = ep93xx_set_link_ksettings,
  597. };
  598. static const struct net_device_ops ep93xx_netdev_ops = {
  599. .ndo_open = ep93xx_open,
  600. .ndo_stop = ep93xx_close,
  601. .ndo_start_xmit = ep93xx_xmit,
  602. .ndo_do_ioctl = ep93xx_ioctl,
  603. .ndo_validate_addr = eth_validate_addr,
  604. .ndo_set_mac_address = eth_mac_addr,
  605. };
  606. static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data)
  607. {
  608. struct net_device *dev;
  609. dev = alloc_etherdev(sizeof(struct ep93xx_priv));
  610. if (dev == NULL)
  611. return NULL;
  612. memcpy(dev->dev_addr, data->dev_addr, ETH_ALEN);
  613. dev->ethtool_ops = &ep93xx_ethtool_ops;
  614. dev->netdev_ops = &ep93xx_netdev_ops;
  615. dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
  616. return dev;
  617. }
  618. static int ep93xx_eth_remove(struct platform_device *pdev)
  619. {
  620. struct net_device *dev;
  621. struct ep93xx_priv *ep;
  622. struct resource *mem;
  623. dev = platform_get_drvdata(pdev);
  624. if (dev == NULL)
  625. return 0;
  626. ep = netdev_priv(dev);
  627. /* @@@ Force down. */
  628. unregister_netdev(dev);
  629. ep93xx_free_buffers(ep);
  630. if (ep->base_addr != NULL)
  631. iounmap(ep->base_addr);
  632. if (ep->res != NULL) {
  633. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  634. release_mem_region(mem->start, resource_size(mem));
  635. }
  636. free_netdev(dev);
  637. return 0;
  638. }
  639. static int ep93xx_eth_probe(struct platform_device *pdev)
  640. {
  641. struct ep93xx_eth_data *data;
  642. struct net_device *dev;
  643. struct ep93xx_priv *ep;
  644. struct resource *mem;
  645. int irq;
  646. int err;
  647. if (pdev == NULL)
  648. return -ENODEV;
  649. data = dev_get_platdata(&pdev->dev);
  650. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  651. irq = platform_get_irq(pdev, 0);
  652. if (!mem || irq < 0)
  653. return -ENXIO;
  654. dev = ep93xx_dev_alloc(data);
  655. if (dev == NULL) {
  656. err = -ENOMEM;
  657. goto err_out;
  658. }
  659. ep = netdev_priv(dev);
  660. ep->dev = dev;
  661. SET_NETDEV_DEV(dev, &pdev->dev);
  662. netif_napi_add(dev, &ep->napi, ep93xx_poll, 64);
  663. platform_set_drvdata(pdev, dev);
  664. ep->res = request_mem_region(mem->start, resource_size(mem),
  665. dev_name(&pdev->dev));
  666. if (ep->res == NULL) {
  667. dev_err(&pdev->dev, "Could not reserve memory region\n");
  668. err = -ENOMEM;
  669. goto err_out;
  670. }
  671. ep->base_addr = ioremap(mem->start, resource_size(mem));
  672. if (ep->base_addr == NULL) {
  673. dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
  674. err = -EIO;
  675. goto err_out;
  676. }
  677. ep->irq = irq;
  678. ep->mii.phy_id = data->phy_id;
  679. ep->mii.phy_id_mask = 0x1f;
  680. ep->mii.reg_num_mask = 0x1f;
  681. ep->mii.dev = dev;
  682. ep->mii.mdio_read = ep93xx_mdio_read;
  683. ep->mii.mdio_write = ep93xx_mdio_write;
  684. ep->mdc_divisor = 40; /* Max HCLK 100 MHz, min MDIO clk 2.5 MHz. */
  685. if (is_zero_ether_addr(dev->dev_addr))
  686. eth_hw_addr_random(dev);
  687. err = register_netdev(dev);
  688. if (err) {
  689. dev_err(&pdev->dev, "Failed to register netdev\n");
  690. goto err_out;
  691. }
  692. printk(KERN_INFO "%s: ep93xx on-chip ethernet, IRQ %d, %pM\n",
  693. dev->name, ep->irq, dev->dev_addr);
  694. return 0;
  695. err_out:
  696. ep93xx_eth_remove(pdev);
  697. return err;
  698. }
  699. static struct platform_driver ep93xx_eth_driver = {
  700. .probe = ep93xx_eth_probe,
  701. .remove = ep93xx_eth_remove,
  702. .driver = {
  703. .name = "ep93xx-eth",
  704. },
  705. };
  706. module_platform_driver(ep93xx_eth_driver);
  707. MODULE_LICENSE("GPL");
  708. MODULE_ALIAS("platform:ep93xx-eth");