greth.h 3.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef GRETH_H
  3. #define GRETH_H
  4. #include <linux/phy.h>
  5. /* Register bits and masks */
  6. #define GRETH_RESET 0x40
  7. #define GRETH_MII_BUSY 0x8
  8. #define GRETH_MII_NVALID 0x10
  9. #define GRETH_CTRL_FD 0x10
  10. #define GRETH_CTRL_PR 0x20
  11. #define GRETH_CTRL_SP 0x80
  12. #define GRETH_CTRL_GB 0x100
  13. #define GRETH_CTRL_PSTATIEN 0x400
  14. #define GRETH_CTRL_MCEN 0x800
  15. #define GRETH_CTRL_DISDUPLEX 0x1000
  16. #define GRETH_STATUS_PHYSTAT 0x100
  17. #define GRETH_BD_EN 0x800
  18. #define GRETH_BD_WR 0x1000
  19. #define GRETH_BD_IE 0x2000
  20. #define GRETH_BD_LEN 0x7FF
  21. #define GRETH_TXEN 0x1
  22. #define GRETH_INT_TE 0x2
  23. #define GRETH_INT_TX 0x8
  24. #define GRETH_TXI 0x4
  25. #define GRETH_TXBD_STATUS 0x0001C000
  26. #define GRETH_TXBD_MORE 0x20000
  27. #define GRETH_TXBD_IPCS 0x40000
  28. #define GRETH_TXBD_TCPCS 0x80000
  29. #define GRETH_TXBD_UDPCS 0x100000
  30. #define GRETH_TXBD_CSALL (GRETH_TXBD_IPCS | GRETH_TXBD_TCPCS | GRETH_TXBD_UDPCS)
  31. #define GRETH_TXBD_ERR_LC 0x10000
  32. #define GRETH_TXBD_ERR_UE 0x4000
  33. #define GRETH_TXBD_ERR_AL 0x8000
  34. #define GRETH_INT_RE 0x1
  35. #define GRETH_INT_RX 0x4
  36. #define GRETH_RXEN 0x2
  37. #define GRETH_RXI 0x8
  38. #define GRETH_RXBD_STATUS 0xFFFFC000
  39. #define GRETH_RXBD_ERR_AE 0x4000
  40. #define GRETH_RXBD_ERR_FT 0x8000
  41. #define GRETH_RXBD_ERR_CRC 0x10000
  42. #define GRETH_RXBD_ERR_OE 0x20000
  43. #define GRETH_RXBD_ERR_LE 0x40000
  44. #define GRETH_RXBD_IP 0x80000
  45. #define GRETH_RXBD_IP_CSERR 0x100000
  46. #define GRETH_RXBD_UDP 0x200000
  47. #define GRETH_RXBD_UDP_CSERR 0x400000
  48. #define GRETH_RXBD_TCP 0x800000
  49. #define GRETH_RXBD_TCP_CSERR 0x1000000
  50. #define GRETH_RXBD_IP_FRAG 0x2000000
  51. #define GRETH_RXBD_MCAST 0x4000000
  52. /* Descriptor parameters */
  53. #define GRETH_TXBD_NUM 128
  54. #define GRETH_TXBD_NUM_MASK (GRETH_TXBD_NUM-1)
  55. #define GRETH_TX_BUF_SIZE 2048
  56. #define GRETH_RXBD_NUM 128
  57. #define GRETH_RXBD_NUM_MASK (GRETH_RXBD_NUM-1)
  58. #define GRETH_RX_BUF_SIZE 2048
  59. /* Buffers per page */
  60. #define GRETH_RX_BUF_PPGAE (PAGE_SIZE/GRETH_RX_BUF_SIZE)
  61. #define GRETH_TX_BUF_PPGAE (PAGE_SIZE/GRETH_TX_BUF_SIZE)
  62. /* How many pages are needed for buffers */
  63. #define GRETH_RX_BUF_PAGE_NUM (GRETH_RXBD_NUM/GRETH_RX_BUF_PPGAE)
  64. #define GRETH_TX_BUF_PAGE_NUM (GRETH_TXBD_NUM/GRETH_TX_BUF_PPGAE)
  65. /* Buffer size.
  66. * Gbit MAC uses tagged maximum frame size which is 1518 excluding CRC.
  67. * Set to 1520 to make all buffers word aligned for non-gbit MAC.
  68. */
  69. #define MAX_FRAME_SIZE 1520
  70. /* GRETH APB registers */
  71. struct greth_regs {
  72. u32 control;
  73. u32 status;
  74. u32 esa_msb;
  75. u32 esa_lsb;
  76. u32 mdio;
  77. u32 tx_desc_p;
  78. u32 rx_desc_p;
  79. u32 edclip;
  80. u32 hash_msb;
  81. u32 hash_lsb;
  82. };
  83. /* GRETH buffer descriptor */
  84. struct greth_bd {
  85. u32 stat;
  86. u32 addr;
  87. };
  88. struct greth_private {
  89. struct sk_buff *rx_skbuff[GRETH_RXBD_NUM];
  90. struct sk_buff *tx_skbuff[GRETH_TXBD_NUM];
  91. unsigned char *tx_bufs[GRETH_TXBD_NUM];
  92. unsigned char *rx_bufs[GRETH_RXBD_NUM];
  93. u16 tx_bufs_length[GRETH_TXBD_NUM];
  94. u16 tx_next;
  95. u16 tx_last;
  96. u16 tx_free; /* only used on 10/100Mbit */
  97. u16 rx_cur;
  98. struct greth_regs *regs; /* Address of controller registers. */
  99. struct greth_bd *rx_bd_base; /* Address of Rx BDs. */
  100. struct greth_bd *tx_bd_base; /* Address of Tx BDs. */
  101. dma_addr_t rx_bd_base_phys;
  102. dma_addr_t tx_bd_base_phys;
  103. int irq;
  104. struct device *dev; /* Pointer to platform_device->dev */
  105. struct net_device *netdev;
  106. struct napi_struct napi;
  107. spinlock_t devlock;
  108. struct mii_bus *mdio;
  109. unsigned int link;
  110. unsigned int speed;
  111. unsigned int duplex;
  112. u32 msg_enable;
  113. u8 phyaddr;
  114. u8 multicast;
  115. u8 gbit_mac;
  116. u8 mdio_int_en;
  117. u8 edcl;
  118. };
  119. #endif