em28xx-core.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
  4. //
  5. // Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
  6. // Markus Rechberger <mrechberger@gmail.com>
  7. // Mauro Carvalho Chehab <mchehab@kernel.org>
  8. // Sascha Sommer <saschasommer@freenet.de>
  9. // Copyright (C) 2012 Frank Schäfer <fschaefer.oss@googlemail.com>
  10. //
  11. // This program is free software; you can redistribute it and/or modify
  12. // it under the terms of the GNU General Public License as published by
  13. // the Free Software Foundation; either version 2 of the License, or
  14. // (at your option) any later version.
  15. //
  16. // This program is distributed in the hope that it will be useful,
  17. // but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. // GNU General Public License for more details.
  20. #include "em28xx.h"
  21. #include <linux/init.h>
  22. #include <linux/jiffies.h>
  23. #include <linux/list.h>
  24. #include <linux/module.h>
  25. #include <linux/slab.h>
  26. #include <linux/usb.h>
  27. #include <linux/vmalloc.h>
  28. #include <sound/ac97_codec.h>
  29. #include <media/v4l2-common.h>
  30. #define DRIVER_AUTHOR "Ludovico Cavedon <cavedon@sssup.it>, " \
  31. "Markus Rechberger <mrechberger@gmail.com>, " \
  32. "Mauro Carvalho Chehab <mchehab@kernel.org>, " \
  33. "Sascha Sommer <saschasommer@freenet.de>"
  34. MODULE_AUTHOR(DRIVER_AUTHOR);
  35. MODULE_DESCRIPTION(DRIVER_DESC);
  36. MODULE_LICENSE("GPL v2");
  37. MODULE_VERSION(EM28XX_VERSION);
  38. /* #define ENABLE_DEBUG_ISOC_FRAMES */
  39. static unsigned int core_debug;
  40. module_param(core_debug, int, 0644);
  41. MODULE_PARM_DESC(core_debug, "enable debug messages [core and isoc]");
  42. #define em28xx_coredbg(fmt, arg...) do { \
  43. if (core_debug) \
  44. dev_printk(KERN_DEBUG, &dev->intf->dev, \
  45. "core: %s: " fmt, __func__, ## arg); \
  46. } while (0)
  47. static unsigned int reg_debug;
  48. module_param(reg_debug, int, 0644);
  49. MODULE_PARM_DESC(reg_debug, "enable debug messages [URB reg]");
  50. #define em28xx_regdbg(fmt, arg...) do { \
  51. if (reg_debug) \
  52. dev_printk(KERN_DEBUG, &dev->intf->dev, \
  53. "reg: %s: " fmt, __func__, ## arg); \
  54. } while (0)
  55. /* FIXME: don't abuse core_debug */
  56. #define em28xx_isocdbg(fmt, arg...) do { \
  57. if (core_debug) \
  58. dev_printk(KERN_DEBUG, &dev->intf->dev, \
  59. "core: %s: " fmt, __func__, ## arg); \
  60. } while (0)
  61. /*
  62. * em28xx_read_reg_req()
  63. * reads data from the usb device specifying bRequest
  64. */
  65. int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
  66. char *buf, int len)
  67. {
  68. int ret;
  69. struct usb_device *udev = interface_to_usbdev(dev->intf);
  70. int pipe = usb_rcvctrlpipe(udev, 0);
  71. if (dev->disconnected)
  72. return -ENODEV;
  73. if (len > URB_MAX_CTRL_SIZE)
  74. return -EINVAL;
  75. mutex_lock(&dev->ctrl_urb_lock);
  76. ret = usb_control_msg(udev, pipe, req,
  77. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  78. 0x0000, reg, dev->urb_buf, len, HZ);
  79. if (ret < 0) {
  80. em28xx_regdbg("(pipe 0x%08x): IN: %02x %02x %02x %02x %02x %02x %02x %02x failed with error %i\n",
  81. pipe,
  82. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  83. req, 0, 0,
  84. reg & 0xff, reg >> 8,
  85. len & 0xff, len >> 8, ret);
  86. mutex_unlock(&dev->ctrl_urb_lock);
  87. return usb_translate_errors(ret);
  88. }
  89. if (len)
  90. memcpy(buf, dev->urb_buf, len);
  91. mutex_unlock(&dev->ctrl_urb_lock);
  92. em28xx_regdbg("(pipe 0x%08x): IN: %02x %02x %02x %02x %02x %02x %02x %02x <<< %*ph\n",
  93. pipe, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  94. req, 0, 0,
  95. reg & 0xff, reg >> 8,
  96. len & 0xff, len >> 8, len, buf);
  97. return ret;
  98. }
  99. /*
  100. * em28xx_read_reg_req()
  101. * reads data from the usb device specifying bRequest
  102. */
  103. int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
  104. {
  105. int ret;
  106. u8 val;
  107. ret = em28xx_read_reg_req_len(dev, req, reg, &val, 1);
  108. if (ret < 0)
  109. return ret;
  110. return val;
  111. }
  112. int em28xx_read_reg(struct em28xx *dev, u16 reg)
  113. {
  114. return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
  115. }
  116. EXPORT_SYMBOL_GPL(em28xx_read_reg);
  117. /*
  118. * em28xx_write_regs_req()
  119. * sends data to the usb device, specifying bRequest
  120. */
  121. int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
  122. int len)
  123. {
  124. int ret;
  125. struct usb_device *udev = interface_to_usbdev(dev->intf);
  126. int pipe = usb_sndctrlpipe(udev, 0);
  127. if (dev->disconnected)
  128. return -ENODEV;
  129. if (len < 1 || len > URB_MAX_CTRL_SIZE)
  130. return -EINVAL;
  131. mutex_lock(&dev->ctrl_urb_lock);
  132. memcpy(dev->urb_buf, buf, len);
  133. ret = usb_control_msg(udev, pipe, req,
  134. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  135. 0x0000, reg, dev->urb_buf, len, HZ);
  136. mutex_unlock(&dev->ctrl_urb_lock);
  137. if (ret < 0) {
  138. em28xx_regdbg("(pipe 0x%08x): OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>> %*ph failed with error %i\n",
  139. pipe,
  140. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  141. req, 0, 0,
  142. reg & 0xff, reg >> 8,
  143. len & 0xff, len >> 8, len, buf, ret);
  144. return usb_translate_errors(ret);
  145. }
  146. em28xx_regdbg("(pipe 0x%08x): OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>> %*ph\n",
  147. pipe,
  148. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  149. req, 0, 0,
  150. reg & 0xff, reg >> 8,
  151. len & 0xff, len >> 8, len, buf);
  152. if (dev->wait_after_write)
  153. msleep(dev->wait_after_write);
  154. return ret;
  155. }
  156. int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
  157. {
  158. return em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
  159. }
  160. EXPORT_SYMBOL_GPL(em28xx_write_regs);
  161. /* Write a single register */
  162. int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val)
  163. {
  164. return em28xx_write_regs(dev, reg, &val, 1);
  165. }
  166. EXPORT_SYMBOL_GPL(em28xx_write_reg);
  167. /*
  168. * em28xx_write_reg_bits()
  169. * sets only some bits (specified by bitmask) of a register, by first reading
  170. * the actual value
  171. */
  172. int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
  173. u8 bitmask)
  174. {
  175. int oldval;
  176. u8 newval;
  177. oldval = em28xx_read_reg(dev, reg);
  178. if (oldval < 0)
  179. return oldval;
  180. newval = (((u8)oldval) & ~bitmask) | (val & bitmask);
  181. return em28xx_write_regs(dev, reg, &newval, 1);
  182. }
  183. EXPORT_SYMBOL_GPL(em28xx_write_reg_bits);
  184. /*
  185. * em28xx_toggle_reg_bits()
  186. * toggles/inverts the bits (specified by bitmask) of a register
  187. */
  188. int em28xx_toggle_reg_bits(struct em28xx *dev, u16 reg, u8 bitmask)
  189. {
  190. int oldval;
  191. u8 newval;
  192. oldval = em28xx_read_reg(dev, reg);
  193. if (oldval < 0)
  194. return oldval;
  195. newval = (~oldval & bitmask) | (oldval & ~bitmask);
  196. return em28xx_write_reg(dev, reg, newval);
  197. }
  198. EXPORT_SYMBOL_GPL(em28xx_toggle_reg_bits);
  199. /*
  200. * em28xx_is_ac97_ready()
  201. * Checks if ac97 is ready
  202. */
  203. static int em28xx_is_ac97_ready(struct em28xx *dev)
  204. {
  205. unsigned long timeout = jiffies + msecs_to_jiffies(EM28XX_AC97_XFER_TIMEOUT);
  206. int ret;
  207. /* Wait up to 50 ms for AC97 command to complete */
  208. while (time_is_after_jiffies(timeout)) {
  209. ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
  210. if (ret < 0)
  211. return ret;
  212. if (!(ret & 0x01))
  213. return 0;
  214. msleep(5);
  215. }
  216. dev_warn(&dev->intf->dev,
  217. "AC97 command still being executed: not handled properly!\n");
  218. return -EBUSY;
  219. }
  220. /*
  221. * em28xx_read_ac97()
  222. * write a 16 bit value to the specified AC97 address (LSB first!)
  223. */
  224. int em28xx_read_ac97(struct em28xx *dev, u8 reg)
  225. {
  226. int ret;
  227. u8 addr = (reg & 0x7f) | 0x80;
  228. __le16 val;
  229. ret = em28xx_is_ac97_ready(dev);
  230. if (ret < 0)
  231. return ret;
  232. ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
  233. if (ret < 0)
  234. return ret;
  235. ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB,
  236. (u8 *)&val, sizeof(val));
  237. if (ret < 0)
  238. return ret;
  239. return le16_to_cpu(val);
  240. }
  241. EXPORT_SYMBOL_GPL(em28xx_read_ac97);
  242. /*
  243. * em28xx_write_ac97()
  244. * write a 16 bit value to the specified AC97 address (LSB first!)
  245. */
  246. int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val)
  247. {
  248. int ret;
  249. u8 addr = reg & 0x7f;
  250. __le16 value;
  251. value = cpu_to_le16(val);
  252. ret = em28xx_is_ac97_ready(dev);
  253. if (ret < 0)
  254. return ret;
  255. ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *)&value, 2);
  256. if (ret < 0)
  257. return ret;
  258. ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
  259. if (ret < 0)
  260. return ret;
  261. return 0;
  262. }
  263. EXPORT_SYMBOL_GPL(em28xx_write_ac97);
  264. struct em28xx_vol_itable {
  265. enum em28xx_amux mux;
  266. u8 reg;
  267. };
  268. static struct em28xx_vol_itable inputs[] = {
  269. { EM28XX_AMUX_VIDEO, AC97_VIDEO },
  270. { EM28XX_AMUX_LINE_IN, AC97_LINE },
  271. { EM28XX_AMUX_PHONE, AC97_PHONE },
  272. { EM28XX_AMUX_MIC, AC97_MIC },
  273. { EM28XX_AMUX_CD, AC97_CD },
  274. { EM28XX_AMUX_AUX, AC97_AUX },
  275. { EM28XX_AMUX_PCM_OUT, AC97_PCM },
  276. };
  277. static int set_ac97_input(struct em28xx *dev)
  278. {
  279. int ret, i;
  280. enum em28xx_amux amux = dev->ctl_ainput;
  281. /*
  282. * EM28XX_AMUX_VIDEO2 is a special case used to indicate that
  283. * em28xx should point to LINE IN, while AC97 should use VIDEO
  284. */
  285. if (amux == EM28XX_AMUX_VIDEO2)
  286. amux = EM28XX_AMUX_VIDEO;
  287. /* Mute all entres but the one that were selected */
  288. for (i = 0; i < ARRAY_SIZE(inputs); i++) {
  289. if (amux == inputs[i].mux)
  290. ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808);
  291. else
  292. ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000);
  293. if (ret < 0)
  294. dev_warn(&dev->intf->dev,
  295. "couldn't setup AC97 register %d\n",
  296. inputs[i].reg);
  297. }
  298. return 0;
  299. }
  300. static int em28xx_set_audio_source(struct em28xx *dev)
  301. {
  302. int ret;
  303. u8 input;
  304. if (dev->board.is_em2800) {
  305. if (dev->ctl_ainput == EM28XX_AMUX_VIDEO)
  306. input = EM2800_AUDIO_SRC_TUNER;
  307. else
  308. input = EM2800_AUDIO_SRC_LINE;
  309. ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
  310. if (ret < 0)
  311. return ret;
  312. }
  313. if (dev->has_msp34xx) {
  314. input = EM28XX_AUDIO_SRC_TUNER;
  315. } else {
  316. switch (dev->ctl_ainput) {
  317. case EM28XX_AMUX_VIDEO:
  318. input = EM28XX_AUDIO_SRC_TUNER;
  319. break;
  320. default:
  321. input = EM28XX_AUDIO_SRC_LINE;
  322. break;
  323. }
  324. }
  325. if (dev->board.mute_gpio && dev->mute)
  326. em28xx_gpio_set(dev, dev->board.mute_gpio);
  327. else
  328. em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
  329. ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
  330. if (ret < 0)
  331. return ret;
  332. usleep_range(10000, 11000);
  333. switch (dev->audio_mode.ac97) {
  334. case EM28XX_NO_AC97:
  335. break;
  336. default:
  337. ret = set_ac97_input(dev);
  338. }
  339. return ret;
  340. }
  341. struct em28xx_vol_otable {
  342. enum em28xx_aout mux;
  343. u8 reg;
  344. };
  345. static const struct em28xx_vol_otable outputs[] = {
  346. { EM28XX_AOUT_MASTER, AC97_MASTER },
  347. { EM28XX_AOUT_LINE, AC97_HEADPHONE },
  348. { EM28XX_AOUT_MONO, AC97_MASTER_MONO },
  349. { EM28XX_AOUT_LFE, AC97_CENTER_LFE_MASTER },
  350. { EM28XX_AOUT_SURR, AC97_SURROUND_MASTER },
  351. };
  352. int em28xx_audio_analog_set(struct em28xx *dev)
  353. {
  354. int ret, i;
  355. u8 xclk;
  356. if (dev->int_audio_type == EM28XX_INT_AUDIO_NONE)
  357. return 0;
  358. /*
  359. * It is assumed that all devices use master volume for output.
  360. * It would be possible to use also line output.
  361. */
  362. if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
  363. /* Mute all outputs */
  364. for (i = 0; i < ARRAY_SIZE(outputs); i++) {
  365. ret = em28xx_write_ac97(dev, outputs[i].reg, 0x8000);
  366. if (ret < 0)
  367. dev_warn(&dev->intf->dev,
  368. "couldn't setup AC97 register %d\n",
  369. outputs[i].reg);
  370. }
  371. }
  372. xclk = dev->board.xclk & 0x7f;
  373. if (!dev->mute)
  374. xclk |= EM28XX_XCLK_AUDIO_UNMUTE;
  375. ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk);
  376. if (ret < 0)
  377. return ret;
  378. usleep_range(10000, 11000);
  379. /* Selects the proper audio input */
  380. ret = em28xx_set_audio_source(dev);
  381. /* Sets volume */
  382. if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
  383. int vol;
  384. em28xx_write_ac97(dev, AC97_POWERDOWN, 0x4200);
  385. em28xx_write_ac97(dev, AC97_EXTENDED_STATUS, 0x0031);
  386. em28xx_write_ac97(dev, AC97_PCM_LR_ADC_RATE, 0xbb80);
  387. /* LSB: left channel - both channels with the same level */
  388. vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8);
  389. /* Mute device, if needed */
  390. if (dev->mute)
  391. vol |= 0x8000;
  392. /* Sets volume */
  393. for (i = 0; i < ARRAY_SIZE(outputs); i++) {
  394. if (dev->ctl_aoutput & outputs[i].mux)
  395. ret = em28xx_write_ac97(dev, outputs[i].reg,
  396. vol);
  397. if (ret < 0)
  398. dev_warn(&dev->intf->dev,
  399. "couldn't setup AC97 register %d\n",
  400. outputs[i].reg);
  401. }
  402. if (dev->ctl_aoutput & EM28XX_AOUT_PCM_IN) {
  403. int sel = ac97_return_record_select(dev->ctl_aoutput);
  404. /*
  405. * Use the same input for both left and right
  406. * channels
  407. */
  408. sel |= (sel << 8);
  409. em28xx_write_ac97(dev, AC97_REC_SEL, sel);
  410. }
  411. }
  412. return ret;
  413. }
  414. EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
  415. int em28xx_audio_setup(struct em28xx *dev)
  416. {
  417. int vid1, vid2, feat, cfg;
  418. u32 vid = 0;
  419. u8 i2s_samplerates;
  420. if (dev->chip_id == CHIP_ID_EM2870 ||
  421. dev->chip_id == CHIP_ID_EM2874 ||
  422. dev->chip_id == CHIP_ID_EM28174 ||
  423. dev->chip_id == CHIP_ID_EM28178) {
  424. /* Digital only device - don't load any alsa module */
  425. dev->int_audio_type = EM28XX_INT_AUDIO_NONE;
  426. dev->usb_audio_type = EM28XX_USB_AUDIO_NONE;
  427. return 0;
  428. }
  429. /* See how this device is configured */
  430. cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
  431. dev_info(&dev->intf->dev, "Config register raw data: 0x%02x\n", cfg);
  432. if (cfg < 0) { /* Register read error */
  433. /* Be conservative */
  434. dev->int_audio_type = EM28XX_INT_AUDIO_AC97;
  435. } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) == 0x00) {
  436. /* The device doesn't have vendor audio at all */
  437. dev->int_audio_type = EM28XX_INT_AUDIO_NONE;
  438. dev->usb_audio_type = EM28XX_USB_AUDIO_NONE;
  439. return 0;
  440. } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) != EM28XX_CHIPCFG_AC97) {
  441. dev->int_audio_type = EM28XX_INT_AUDIO_I2S;
  442. if (dev->chip_id < CHIP_ID_EM2860 &&
  443. (cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
  444. EM2820_CHIPCFG_I2S_1_SAMPRATE)
  445. i2s_samplerates = 1;
  446. else if (dev->chip_id >= CHIP_ID_EM2860 &&
  447. (cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
  448. EM2860_CHIPCFG_I2S_5_SAMPRATES)
  449. i2s_samplerates = 5;
  450. else
  451. i2s_samplerates = 3;
  452. dev_info(&dev->intf->dev, "I2S Audio (%d sample rate(s))\n",
  453. i2s_samplerates);
  454. /* Skip the code that does AC97 vendor detection */
  455. dev->audio_mode.ac97 = EM28XX_NO_AC97;
  456. goto init_audio;
  457. } else {
  458. dev->int_audio_type = EM28XX_INT_AUDIO_AC97;
  459. }
  460. dev->audio_mode.ac97 = EM28XX_AC97_OTHER;
  461. vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1);
  462. if (vid1 < 0) {
  463. /*
  464. * Device likely doesn't support AC97
  465. * Note: (some) em2800 devices without eeprom reports 0x91 on
  466. * CHIPCFG register, even not having an AC97 chip
  467. */
  468. dev_warn(&dev->intf->dev,
  469. "AC97 chip type couldn't be determined\n");
  470. dev->audio_mode.ac97 = EM28XX_NO_AC97;
  471. if (dev->usb_audio_type == EM28XX_USB_AUDIO_VENDOR)
  472. dev->usb_audio_type = EM28XX_USB_AUDIO_NONE;
  473. dev->int_audio_type = EM28XX_INT_AUDIO_NONE;
  474. goto init_audio;
  475. }
  476. vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2);
  477. if (vid2 < 0)
  478. goto init_audio;
  479. vid = vid1 << 16 | vid2;
  480. dev_warn(&dev->intf->dev, "AC97 vendor ID = 0x%08x\n", vid);
  481. feat = em28xx_read_ac97(dev, AC97_RESET);
  482. if (feat < 0)
  483. goto init_audio;
  484. dev_warn(&dev->intf->dev, "AC97 features = 0x%04x\n", feat);
  485. /* Try to identify what audio processor we have */
  486. if ((vid == 0xffffffff || vid == 0x83847650) && feat == 0x6a90)
  487. dev->audio_mode.ac97 = EM28XX_AC97_EM202;
  488. else if ((vid >> 8) == 0x838476)
  489. dev->audio_mode.ac97 = EM28XX_AC97_SIGMATEL;
  490. init_audio:
  491. /* Reports detected AC97 processor */
  492. switch (dev->audio_mode.ac97) {
  493. case EM28XX_NO_AC97:
  494. dev_info(&dev->intf->dev, "No AC97 audio processor\n");
  495. break;
  496. case EM28XX_AC97_EM202:
  497. dev_info(&dev->intf->dev,
  498. "Empia 202 AC97 audio processor detected\n");
  499. break;
  500. case EM28XX_AC97_SIGMATEL:
  501. dev_info(&dev->intf->dev,
  502. "Sigmatel audio processor detected (stac 97%02x)\n",
  503. vid & 0xff);
  504. break;
  505. case EM28XX_AC97_OTHER:
  506. dev_warn(&dev->intf->dev,
  507. "Unknown AC97 audio processor detected!\n");
  508. break;
  509. default:
  510. break;
  511. }
  512. return em28xx_audio_analog_set(dev);
  513. }
  514. EXPORT_SYMBOL_GPL(em28xx_audio_setup);
  515. const struct em28xx_led *em28xx_find_led(struct em28xx *dev,
  516. enum em28xx_led_role role)
  517. {
  518. if (dev->board.leds) {
  519. u8 k = 0;
  520. while (dev->board.leds[k].role >= 0 &&
  521. dev->board.leds[k].role < EM28XX_NUM_LED_ROLES) {
  522. if (dev->board.leds[k].role == role)
  523. return &dev->board.leds[k];
  524. k++;
  525. }
  526. }
  527. return NULL;
  528. }
  529. EXPORT_SYMBOL_GPL(em28xx_find_led);
  530. int em28xx_capture_start(struct em28xx *dev, int start)
  531. {
  532. int rc;
  533. const struct em28xx_led *led = NULL;
  534. if (dev->chip_id == CHIP_ID_EM2874 ||
  535. dev->chip_id == CHIP_ID_EM2884 ||
  536. dev->chip_id == CHIP_ID_EM28174 ||
  537. dev->chip_id == CHIP_ID_EM28178) {
  538. /* The Transport Stream Enable Register moved in em2874 */
  539. if (dev->dvb_xfer_bulk) {
  540. /* Max Tx Size = 188 * 256 = 48128 - LCM(188,512) * 2 */
  541. em28xx_write_reg(dev, (dev->ts == PRIMARY_TS) ?
  542. EM2874_R5D_TS1_PKT_SIZE :
  543. EM2874_R5E_TS2_PKT_SIZE,
  544. 0xff);
  545. } else {
  546. /* ISOC Maximum Transfer Size = 188 * 5 */
  547. em28xx_write_reg(dev, (dev->ts == PRIMARY_TS) ?
  548. EM2874_R5D_TS1_PKT_SIZE :
  549. EM2874_R5E_TS2_PKT_SIZE,
  550. dev->dvb_max_pkt_size_isoc / 188);
  551. }
  552. if (dev->ts == PRIMARY_TS)
  553. rc = em28xx_write_reg_bits(dev,
  554. EM2874_R5F_TS_ENABLE,
  555. start ? EM2874_TS1_CAPTURE_ENABLE : 0x00,
  556. EM2874_TS1_CAPTURE_ENABLE | EM2874_TS1_FILTER_ENABLE | EM2874_TS1_NULL_DISCARD);
  557. else
  558. rc = em28xx_write_reg_bits(dev,
  559. EM2874_R5F_TS_ENABLE,
  560. start ? EM2874_TS2_CAPTURE_ENABLE : 0x00,
  561. EM2874_TS2_CAPTURE_ENABLE | EM2874_TS2_FILTER_ENABLE | EM2874_TS2_NULL_DISCARD);
  562. } else {
  563. /* FIXME: which is the best order? */
  564. /* video registers are sampled by VREF */
  565. rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
  566. start ? 0x10 : 0x00, 0x10);
  567. if (rc < 0)
  568. return rc;
  569. if (start) {
  570. if (dev->is_webcam)
  571. rc = em28xx_write_reg(dev, 0x13, 0x0c);
  572. /* Enable video capture */
  573. rc = em28xx_write_reg(dev, 0x48, 0x00);
  574. if (rc < 0)
  575. return rc;
  576. if (dev->mode == EM28XX_ANALOG_MODE)
  577. rc = em28xx_write_reg(dev,
  578. EM28XX_R12_VINENABLE,
  579. 0x67);
  580. else
  581. rc = em28xx_write_reg(dev,
  582. EM28XX_R12_VINENABLE,
  583. 0x37);
  584. if (rc < 0)
  585. return rc;
  586. usleep_range(10000, 11000);
  587. } else {
  588. /* disable video capture */
  589. rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x27);
  590. }
  591. }
  592. if (dev->mode == EM28XX_ANALOG_MODE)
  593. led = em28xx_find_led(dev, EM28XX_LED_ANALOG_CAPTURING);
  594. else
  595. led = em28xx_find_led(dev, EM28XX_LED_DIGITAL_CAPTURING);
  596. if (led)
  597. em28xx_write_reg_bits(dev, led->gpio_reg,
  598. (!start ^ led->inverted) ?
  599. ~led->gpio_mask : led->gpio_mask,
  600. led->gpio_mask);
  601. return rc;
  602. }
  603. int em28xx_gpio_set(struct em28xx *dev, const struct em28xx_reg_seq *gpio)
  604. {
  605. int rc = 0;
  606. if (!gpio)
  607. return rc;
  608. if (dev->mode != EM28XX_SUSPEND) {
  609. em28xx_write_reg(dev, 0x48, 0x00);
  610. if (dev->mode == EM28XX_ANALOG_MODE)
  611. em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
  612. else
  613. em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
  614. usleep_range(10000, 11000);
  615. }
  616. /* Send GPIO reset sequences specified at board entry */
  617. while (gpio->sleep >= 0) {
  618. if (gpio->reg >= 0) {
  619. rc = em28xx_write_reg_bits(dev,
  620. gpio->reg,
  621. gpio->val,
  622. gpio->mask);
  623. if (rc < 0)
  624. return rc;
  625. }
  626. if (gpio->sleep > 0)
  627. msleep(gpio->sleep);
  628. gpio++;
  629. }
  630. return rc;
  631. }
  632. EXPORT_SYMBOL_GPL(em28xx_gpio_set);
  633. int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
  634. {
  635. if (dev->mode == set_mode)
  636. return 0;
  637. if (set_mode == EM28XX_SUSPEND) {
  638. dev->mode = set_mode;
  639. /* FIXME: add suspend support for ac97 */
  640. return em28xx_gpio_set(dev, dev->board.suspend_gpio);
  641. }
  642. dev->mode = set_mode;
  643. if (dev->mode == EM28XX_DIGITAL_MODE)
  644. return em28xx_gpio_set(dev, dev->board.dvb_gpio);
  645. else
  646. return em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
  647. }
  648. EXPORT_SYMBOL_GPL(em28xx_set_mode);
  649. /*
  650. *URB control
  651. */
  652. /*
  653. * URB completion handler for isoc/bulk transfers
  654. */
  655. static void em28xx_irq_callback(struct urb *urb)
  656. {
  657. struct em28xx *dev = urb->context;
  658. int i;
  659. switch (urb->status) {
  660. case 0: /* success */
  661. case -ETIMEDOUT: /* NAK */
  662. break;
  663. case -ECONNRESET: /* kill */
  664. case -ENOENT:
  665. case -ESHUTDOWN:
  666. return;
  667. default: /* error */
  668. em28xx_isocdbg("urb completion error %d.\n", urb->status);
  669. break;
  670. }
  671. /* Copy data from URB */
  672. spin_lock(&dev->slock);
  673. dev->usb_ctl.urb_data_copy(dev, urb);
  674. spin_unlock(&dev->slock);
  675. /* Reset urb buffers */
  676. for (i = 0; i < urb->number_of_packets; i++) {
  677. /* isoc only (bulk: number_of_packets = 0) */
  678. urb->iso_frame_desc[i].status = 0;
  679. urb->iso_frame_desc[i].actual_length = 0;
  680. }
  681. urb->status = 0;
  682. urb->status = usb_submit_urb(urb, GFP_ATOMIC);
  683. if (urb->status) {
  684. em28xx_isocdbg("urb resubmit failed (error=%i)\n",
  685. urb->status);
  686. }
  687. }
  688. /*
  689. * Stop and Deallocate URBs
  690. */
  691. void em28xx_uninit_usb_xfer(struct em28xx *dev, enum em28xx_mode mode)
  692. {
  693. struct urb *urb;
  694. struct em28xx_usb_bufs *usb_bufs;
  695. int i;
  696. em28xx_isocdbg("called %s in mode %d\n", __func__, mode);
  697. if (mode == EM28XX_DIGITAL_MODE)
  698. usb_bufs = &dev->usb_ctl.digital_bufs;
  699. else
  700. usb_bufs = &dev->usb_ctl.analog_bufs;
  701. for (i = 0; i < usb_bufs->num_bufs; i++) {
  702. urb = usb_bufs->urb[i];
  703. if (urb) {
  704. if (!irqs_disabled())
  705. usb_kill_urb(urb);
  706. else
  707. usb_unlink_urb(urb);
  708. usb_free_urb(urb);
  709. usb_bufs->urb[i] = NULL;
  710. }
  711. }
  712. kfree(usb_bufs->urb);
  713. kfree(usb_bufs->buf);
  714. usb_bufs->urb = NULL;
  715. usb_bufs->buf = NULL;
  716. usb_bufs->num_bufs = 0;
  717. em28xx_capture_start(dev, 0);
  718. }
  719. EXPORT_SYMBOL_GPL(em28xx_uninit_usb_xfer);
  720. /*
  721. * Stop URBs
  722. */
  723. void em28xx_stop_urbs(struct em28xx *dev)
  724. {
  725. int i;
  726. struct urb *urb;
  727. struct em28xx_usb_bufs *isoc_bufs = &dev->usb_ctl.digital_bufs;
  728. em28xx_isocdbg("called %s\n", __func__);
  729. for (i = 0; i < isoc_bufs->num_bufs; i++) {
  730. urb = isoc_bufs->urb[i];
  731. if (urb) {
  732. if (!irqs_disabled())
  733. usb_kill_urb(urb);
  734. else
  735. usb_unlink_urb(urb);
  736. }
  737. }
  738. em28xx_capture_start(dev, 0);
  739. }
  740. EXPORT_SYMBOL_GPL(em28xx_stop_urbs);
  741. /*
  742. * Allocate URBs
  743. */
  744. int em28xx_alloc_urbs(struct em28xx *dev, enum em28xx_mode mode, int xfer_bulk,
  745. int num_bufs, int max_pkt_size, int packet_multiplier)
  746. {
  747. struct em28xx_usb_bufs *usb_bufs;
  748. struct urb *urb;
  749. struct usb_device *udev = interface_to_usbdev(dev->intf);
  750. int i;
  751. int sb_size, pipe;
  752. int j, k;
  753. em28xx_isocdbg("em28xx: called %s in mode %d\n", __func__, mode);
  754. /*
  755. * Check mode and if we have an endpoint for the selected
  756. * transfer type, select buffer
  757. */
  758. if (mode == EM28XX_DIGITAL_MODE) {
  759. if ((xfer_bulk && !dev->dvb_ep_bulk) ||
  760. (!xfer_bulk && !dev->dvb_ep_isoc)) {
  761. dev_err(&dev->intf->dev,
  762. "no endpoint for DVB mode and transfer type %d\n",
  763. xfer_bulk > 0);
  764. return -EINVAL;
  765. }
  766. usb_bufs = &dev->usb_ctl.digital_bufs;
  767. } else if (mode == EM28XX_ANALOG_MODE) {
  768. if ((xfer_bulk && !dev->analog_ep_bulk) ||
  769. (!xfer_bulk && !dev->analog_ep_isoc)) {
  770. dev_err(&dev->intf->dev,
  771. "no endpoint for analog mode and transfer type %d\n",
  772. xfer_bulk > 0);
  773. return -EINVAL;
  774. }
  775. usb_bufs = &dev->usb_ctl.analog_bufs;
  776. } else {
  777. dev_err(&dev->intf->dev, "invalid mode selected\n");
  778. return -EINVAL;
  779. }
  780. /* De-allocates all pending stuff */
  781. em28xx_uninit_usb_xfer(dev, mode);
  782. usb_bufs->num_bufs = num_bufs;
  783. usb_bufs->urb = kcalloc(num_bufs, sizeof(void *), GFP_KERNEL);
  784. if (!usb_bufs->urb)
  785. return -ENOMEM;
  786. usb_bufs->buf = kcalloc(num_bufs, sizeof(void *), GFP_KERNEL);
  787. if (!usb_bufs->buf) {
  788. kfree(usb_bufs->urb);
  789. return -ENOMEM;
  790. }
  791. usb_bufs->max_pkt_size = max_pkt_size;
  792. if (xfer_bulk)
  793. usb_bufs->num_packets = 0;
  794. else
  795. usb_bufs->num_packets = packet_multiplier;
  796. dev->usb_ctl.vid_buf = NULL;
  797. dev->usb_ctl.vbi_buf = NULL;
  798. sb_size = packet_multiplier * usb_bufs->max_pkt_size;
  799. /* allocate urbs and transfer buffers */
  800. for (i = 0; i < usb_bufs->num_bufs; i++) {
  801. urb = usb_alloc_urb(usb_bufs->num_packets, GFP_KERNEL);
  802. if (!urb) {
  803. em28xx_uninit_usb_xfer(dev, mode);
  804. return -ENOMEM;
  805. }
  806. usb_bufs->urb[i] = urb;
  807. usb_bufs->buf[i] = kzalloc(sb_size, GFP_KERNEL);
  808. if (!usb_bufs->buf[i]) {
  809. em28xx_uninit_usb_xfer(dev, mode);
  810. for (i--; i >= 0; i--)
  811. kfree(usb_bufs->buf[i]);
  812. kfree(usb_bufs->buf);
  813. usb_bufs->buf = NULL;
  814. return -ENOMEM;
  815. }
  816. urb->transfer_flags = URB_FREE_BUFFER;
  817. if (xfer_bulk) { /* bulk */
  818. pipe = usb_rcvbulkpipe(udev,
  819. mode == EM28XX_ANALOG_MODE ?
  820. dev->analog_ep_bulk :
  821. dev->dvb_ep_bulk);
  822. usb_fill_bulk_urb(urb, udev, pipe, usb_bufs->buf[i],
  823. sb_size, em28xx_irq_callback, dev);
  824. } else { /* isoc */
  825. pipe = usb_rcvisocpipe(udev,
  826. mode == EM28XX_ANALOG_MODE ?
  827. dev->analog_ep_isoc :
  828. dev->dvb_ep_isoc);
  829. usb_fill_int_urb(urb, udev, pipe, usb_bufs->buf[i],
  830. sb_size, em28xx_irq_callback, dev, 1);
  831. urb->transfer_flags |= URB_ISO_ASAP;
  832. k = 0;
  833. for (j = 0; j < usb_bufs->num_packets; j++) {
  834. urb->iso_frame_desc[j].offset = k;
  835. urb->iso_frame_desc[j].length =
  836. usb_bufs->max_pkt_size;
  837. k += usb_bufs->max_pkt_size;
  838. }
  839. }
  840. urb->number_of_packets = usb_bufs->num_packets;
  841. }
  842. return 0;
  843. }
  844. EXPORT_SYMBOL_GPL(em28xx_alloc_urbs);
  845. /*
  846. * Allocate URBs and start IRQ
  847. */
  848. int em28xx_init_usb_xfer(struct em28xx *dev, enum em28xx_mode mode,
  849. int xfer_bulk, int num_bufs, int max_pkt_size,
  850. int packet_multiplier,
  851. int (*urb_data_copy)(struct em28xx *dev, struct urb *urb))
  852. {
  853. struct em28xx_dmaqueue *dma_q = &dev->vidq;
  854. struct em28xx_dmaqueue *vbi_dma_q = &dev->vbiq;
  855. struct em28xx_usb_bufs *usb_bufs;
  856. struct usb_device *udev = interface_to_usbdev(dev->intf);
  857. int i;
  858. int rc;
  859. int alloc;
  860. em28xx_isocdbg("em28xx: called %s in mode %d\n", __func__, mode);
  861. dev->usb_ctl.urb_data_copy = urb_data_copy;
  862. if (mode == EM28XX_DIGITAL_MODE) {
  863. usb_bufs = &dev->usb_ctl.digital_bufs;
  864. /* no need to free/alloc usb buffers in digital mode */
  865. alloc = 0;
  866. } else {
  867. usb_bufs = &dev->usb_ctl.analog_bufs;
  868. alloc = 1;
  869. }
  870. if (alloc) {
  871. rc = em28xx_alloc_urbs(dev, mode, xfer_bulk, num_bufs,
  872. max_pkt_size, packet_multiplier);
  873. if (rc)
  874. return rc;
  875. }
  876. if (xfer_bulk) {
  877. rc = usb_clear_halt(udev, usb_bufs->urb[0]->pipe);
  878. if (rc < 0) {
  879. dev_err(&dev->intf->dev,
  880. "failed to clear USB bulk endpoint stall/halt condition (error=%i)\n",
  881. rc);
  882. em28xx_uninit_usb_xfer(dev, mode);
  883. return rc;
  884. }
  885. }
  886. init_waitqueue_head(&dma_q->wq);
  887. init_waitqueue_head(&vbi_dma_q->wq);
  888. em28xx_capture_start(dev, 1);
  889. /* submit urbs and enables IRQ */
  890. for (i = 0; i < usb_bufs->num_bufs; i++) {
  891. rc = usb_submit_urb(usb_bufs->urb[i], GFP_KERNEL);
  892. if (rc) {
  893. dev_err(&dev->intf->dev,
  894. "submit of urb %i failed (error=%i)\n", i, rc);
  895. em28xx_uninit_usb_xfer(dev, mode);
  896. return rc;
  897. }
  898. }
  899. return 0;
  900. }
  901. EXPORT_SYMBOL_GPL(em28xx_init_usb_xfer);
  902. /*
  903. * Device control list
  904. */
  905. static LIST_HEAD(em28xx_devlist);
  906. static DEFINE_MUTEX(em28xx_devlist_mutex);
  907. /*
  908. * Extension interface
  909. */
  910. static LIST_HEAD(em28xx_extension_devlist);
  911. int em28xx_register_extension(struct em28xx_ops *ops)
  912. {
  913. struct em28xx *dev = NULL;
  914. mutex_lock(&em28xx_devlist_mutex);
  915. list_add_tail(&ops->next, &em28xx_extension_devlist);
  916. list_for_each_entry(dev, &em28xx_devlist, devlist) {
  917. if (ops->init) {
  918. ops->init(dev);
  919. if (dev->dev_next)
  920. ops->init(dev->dev_next);
  921. }
  922. }
  923. mutex_unlock(&em28xx_devlist_mutex);
  924. pr_info("em28xx: Registered (%s) extension\n", ops->name);
  925. return 0;
  926. }
  927. EXPORT_SYMBOL(em28xx_register_extension);
  928. void em28xx_unregister_extension(struct em28xx_ops *ops)
  929. {
  930. struct em28xx *dev = NULL;
  931. mutex_lock(&em28xx_devlist_mutex);
  932. list_for_each_entry(dev, &em28xx_devlist, devlist) {
  933. if (ops->fini) {
  934. if (dev->dev_next)
  935. ops->fini(dev->dev_next);
  936. ops->fini(dev);
  937. }
  938. }
  939. list_del(&ops->next);
  940. mutex_unlock(&em28xx_devlist_mutex);
  941. pr_info("em28xx: Removed (%s) extension\n", ops->name);
  942. }
  943. EXPORT_SYMBOL(em28xx_unregister_extension);
  944. void em28xx_init_extension(struct em28xx *dev)
  945. {
  946. const struct em28xx_ops *ops = NULL;
  947. mutex_lock(&em28xx_devlist_mutex);
  948. list_add_tail(&dev->devlist, &em28xx_devlist);
  949. list_for_each_entry(ops, &em28xx_extension_devlist, next) {
  950. if (ops->init) {
  951. ops->init(dev);
  952. if (dev->dev_next)
  953. ops->init(dev->dev_next);
  954. }
  955. }
  956. mutex_unlock(&em28xx_devlist_mutex);
  957. }
  958. void em28xx_close_extension(struct em28xx *dev)
  959. {
  960. const struct em28xx_ops *ops = NULL;
  961. mutex_lock(&em28xx_devlist_mutex);
  962. list_for_each_entry(ops, &em28xx_extension_devlist, next) {
  963. if (ops->fini) {
  964. if (dev->dev_next)
  965. ops->fini(dev->dev_next);
  966. ops->fini(dev);
  967. }
  968. }
  969. list_del(&dev->devlist);
  970. mutex_unlock(&em28xx_devlist_mutex);
  971. }
  972. int em28xx_suspend_extension(struct em28xx *dev)
  973. {
  974. const struct em28xx_ops *ops = NULL;
  975. dev_info(&dev->intf->dev, "Suspending extensions\n");
  976. mutex_lock(&em28xx_devlist_mutex);
  977. list_for_each_entry(ops, &em28xx_extension_devlist, next) {
  978. if (ops->suspend)
  979. ops->suspend(dev);
  980. if (dev->dev_next)
  981. ops->suspend(dev->dev_next);
  982. }
  983. mutex_unlock(&em28xx_devlist_mutex);
  984. return 0;
  985. }
  986. int em28xx_resume_extension(struct em28xx *dev)
  987. {
  988. const struct em28xx_ops *ops = NULL;
  989. dev_info(&dev->intf->dev, "Resuming extensions\n");
  990. mutex_lock(&em28xx_devlist_mutex);
  991. list_for_each_entry(ops, &em28xx_extension_devlist, next) {
  992. if (!ops->resume)
  993. continue;
  994. ops->resume(dev);
  995. if (dev->dev_next)
  996. ops->resume(dev->dev_next);
  997. }
  998. mutex_unlock(&em28xx_devlist_mutex);
  999. return 0;
  1000. }