pm.c 6.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271
  1. /*
  2. * Suspend/resume support. Currently supporting Armada XP only.
  3. *
  4. * Copyright (C) 2014 Marvell
  5. *
  6. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  7. *
  8. * This file is licensed under the terms of the GNU General Public
  9. * License version 2. This program is licensed "as is" without any
  10. * warranty of any kind, whether express or implied.
  11. */
  12. #include <linux/cpu_pm.h>
  13. #include <linux/delay.h>
  14. #include <linux/gpio.h>
  15. #include <linux/io.h>
  16. #include <linux/kernel.h>
  17. #include <linux/mbus.h>
  18. #include <linux/of_address.h>
  19. #include <linux/suspend.h>
  20. #include <asm/cacheflush.h>
  21. #include <asm/outercache.h>
  22. #include <asm/suspend.h>
  23. #include "coherency.h"
  24. #include "common.h"
  25. #include "pmsu.h"
  26. #define SDRAM_CONFIG_OFFS 0x0
  27. #define SDRAM_CONFIG_SR_MODE_BIT BIT(24)
  28. #define SDRAM_OPERATION_OFFS 0x18
  29. #define SDRAM_OPERATION_SELF_REFRESH 0x7
  30. #define SDRAM_DLB_EVICTION_OFFS 0x30c
  31. #define SDRAM_DLB_EVICTION_THRESHOLD_MASK 0xff
  32. static void (*mvebu_board_pm_enter)(void __iomem *sdram_reg, u32 srcmd);
  33. static void __iomem *sdram_ctrl;
  34. static int mvebu_pm_powerdown(unsigned long data)
  35. {
  36. u32 reg, srcmd;
  37. flush_cache_all();
  38. outer_flush_all();
  39. /*
  40. * Issue a Data Synchronization Barrier instruction to ensure
  41. * that all state saving has been completed.
  42. */
  43. dsb();
  44. /* Flush the DLB and wait ~7 usec */
  45. reg = readl(sdram_ctrl + SDRAM_DLB_EVICTION_OFFS);
  46. reg &= ~SDRAM_DLB_EVICTION_THRESHOLD_MASK;
  47. writel(reg, sdram_ctrl + SDRAM_DLB_EVICTION_OFFS);
  48. udelay(7);
  49. /* Set DRAM in battery backup mode */
  50. reg = readl(sdram_ctrl + SDRAM_CONFIG_OFFS);
  51. reg &= ~SDRAM_CONFIG_SR_MODE_BIT;
  52. writel(reg, sdram_ctrl + SDRAM_CONFIG_OFFS);
  53. /* Prepare to go to self-refresh */
  54. srcmd = readl(sdram_ctrl + SDRAM_OPERATION_OFFS);
  55. srcmd &= ~0x1F;
  56. srcmd |= SDRAM_OPERATION_SELF_REFRESH;
  57. mvebu_board_pm_enter(sdram_ctrl + SDRAM_OPERATION_OFFS, srcmd);
  58. return 0;
  59. }
  60. #define BOOT_INFO_ADDR 0x3000
  61. #define BOOT_MAGIC_WORD 0xdeadb002
  62. #define BOOT_MAGIC_LIST_END 0xffffffff
  63. /*
  64. * Those registers are accessed before switching the internal register
  65. * base, which is why we hardcode the 0xd0000000 base address, the one
  66. * used by the SoC out of reset.
  67. */
  68. #define MBUS_WINDOW_12_CTRL 0xd00200b0
  69. #define MBUS_INTERNAL_REG_ADDRESS 0xd0020080
  70. #define SDRAM_WIN_BASE_REG(x) (0x20180 + (0x8*x))
  71. #define SDRAM_WIN_CTRL_REG(x) (0x20184 + (0x8*x))
  72. static phys_addr_t mvebu_internal_reg_base(void)
  73. {
  74. struct device_node *np;
  75. __be32 in_addr[2];
  76. np = of_find_node_by_name(NULL, "internal-regs");
  77. BUG_ON(!np);
  78. /*
  79. * Ask the DT what is the internal register address on this
  80. * platform. In the mvebu-mbus DT binding, 0xf0010000
  81. * corresponds to the internal register window.
  82. */
  83. in_addr[0] = cpu_to_be32(0xf0010000);
  84. in_addr[1] = 0x0;
  85. return of_translate_address(np, in_addr);
  86. }
  87. static void mvebu_pm_store_armadaxp_bootinfo(u32 *store_addr)
  88. {
  89. phys_addr_t resume_pc;
  90. resume_pc = __pa_symbol(armada_370_xp_cpu_resume);
  91. /*
  92. * The bootloader expects the first two words to be a magic
  93. * value (BOOT_MAGIC_WORD), followed by the address of the
  94. * resume code to jump to. Then, it expects a sequence of
  95. * (address, value) pairs, which can be used to restore the
  96. * value of certain registers. This sequence must end with the
  97. * BOOT_MAGIC_LIST_END magic value.
  98. */
  99. writel(BOOT_MAGIC_WORD, store_addr++);
  100. writel(resume_pc, store_addr++);
  101. /*
  102. * Some platforms remap their internal register base address
  103. * to 0xf1000000. However, out of reset, window 12 starts at
  104. * 0xf0000000 and ends at 0xf7ffffff, which would overlap with
  105. * the internal registers. Therefore, disable window 12.
  106. */
  107. writel(MBUS_WINDOW_12_CTRL, store_addr++);
  108. writel(0x0, store_addr++);
  109. /*
  110. * Set the internal register base address to the value
  111. * expected by Linux, as read from the Device Tree.
  112. */
  113. writel(MBUS_INTERNAL_REG_ADDRESS, store_addr++);
  114. writel(mvebu_internal_reg_base(), store_addr++);
  115. /*
  116. * Ask the mvebu-mbus driver to store the SDRAM window
  117. * configuration, which has to be restored by the bootloader
  118. * before re-entering the kernel on resume.
  119. */
  120. store_addr += mvebu_mbus_save_cpu_target(store_addr);
  121. writel(BOOT_MAGIC_LIST_END, store_addr);
  122. }
  123. static int mvebu_pm_store_bootinfo(void)
  124. {
  125. u32 *store_addr;
  126. store_addr = phys_to_virt(BOOT_INFO_ADDR);
  127. if (of_machine_is_compatible("marvell,armadaxp"))
  128. mvebu_pm_store_armadaxp_bootinfo(store_addr);
  129. else
  130. return -ENODEV;
  131. return 0;
  132. }
  133. static int mvebu_enter_suspend(void)
  134. {
  135. int ret;
  136. ret = mvebu_pm_store_bootinfo();
  137. if (ret)
  138. return ret;
  139. cpu_pm_enter();
  140. cpu_suspend(0, mvebu_pm_powerdown);
  141. outer_resume();
  142. mvebu_v7_pmsu_idle_exit();
  143. set_cpu_coherent();
  144. cpu_pm_exit();
  145. return 0;
  146. }
  147. static int mvebu_pm_enter(suspend_state_t state)
  148. {
  149. switch (state) {
  150. case PM_SUSPEND_STANDBY:
  151. cpu_do_idle();
  152. break;
  153. case PM_SUSPEND_MEM:
  154. pr_warn("Entering suspend to RAM. Only special wake-up sources will resume the system\n");
  155. return mvebu_enter_suspend();
  156. default:
  157. return -EINVAL;
  158. }
  159. return 0;
  160. }
  161. static int mvebu_pm_valid(suspend_state_t state)
  162. {
  163. if (state == PM_SUSPEND_STANDBY)
  164. return 1;
  165. if (state == PM_SUSPEND_MEM && mvebu_board_pm_enter != NULL)
  166. return 1;
  167. return 0;
  168. }
  169. static const struct platform_suspend_ops mvebu_pm_ops = {
  170. .enter = mvebu_pm_enter,
  171. .valid = mvebu_pm_valid,
  172. };
  173. static int __init mvebu_pm_init(void)
  174. {
  175. if (!of_machine_is_compatible("marvell,armadaxp") &&
  176. !of_machine_is_compatible("marvell,armada370") &&
  177. !of_machine_is_compatible("marvell,armada380") &&
  178. !of_machine_is_compatible("marvell,armada390"))
  179. return -ENODEV;
  180. suspend_set_ops(&mvebu_pm_ops);
  181. return 0;
  182. }
  183. late_initcall(mvebu_pm_init);
  184. int __init mvebu_pm_suspend_init(void (*board_pm_enter)(void __iomem *sdram_reg,
  185. u32 srcmd))
  186. {
  187. struct device_node *np;
  188. struct resource res;
  189. np = of_find_compatible_node(NULL, NULL,
  190. "marvell,armada-xp-sdram-controller");
  191. if (!np)
  192. return -ENODEV;
  193. if (of_address_to_resource(np, 0, &res)) {
  194. of_node_put(np);
  195. return -ENODEV;
  196. }
  197. if (!request_mem_region(res.start, resource_size(&res),
  198. np->full_name)) {
  199. of_node_put(np);
  200. return -EBUSY;
  201. }
  202. sdram_ctrl = ioremap(res.start, resource_size(&res));
  203. if (!sdram_ctrl) {
  204. release_mem_region(res.start, resource_size(&res));
  205. of_node_put(np);
  206. return -ENOMEM;
  207. }
  208. of_node_put(np);
  209. mvebu_board_pm_enter = board_pm_enter;
  210. return 0;
  211. }